diff --git a/CTRL.o b/CTRL.o
index 855481c40f0490f2d92da359f84c3d1af3a13d1b..e9a3cd66682a35602e73e47a790bc538b8d3d86d 100644
Binary files a/CTRL.o and b/CTRL.o differ
diff --git a/CTRL.vhd b/CTRL.vhd
index e10b466f5320992ddd1dbd80399fb0211aca6fba..0ea0b56e03b5b0872c0cbea040e747c3972ffa9b 100644
--- a/CTRL.vhd
+++ b/CTRL.vhd
@@ -23,7 +23,6 @@ USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CTRL IS
PORT(
- Instr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OPCode : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
Func : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
RegDst : OUT STD_LOGIC;
@@ -41,66 +40,66 @@ END CTRL;
ARCHITECTURE ARC_CTRL OF CTRL IS
BEGIN
- PROCESS(OPCode)
- BEGIN
- CASE OPCode IS
- --TYPE R
- WHEN "000000" => RegDst <= '1';
- Jump <= '0';
- ALUSrc <= '0';
- MemtoReg <= '0';
- RegWrite <= '1';
- MemRead <= '0';
- MemWrite <= '0';
- Branch <= '0';
- ALUOp(1) <= '1';
- ALUOp(0) <= '0';
- --TYPE LW
- WHEN "100011" => RegDst <= '0';
- Jump <= '0';
- ALUSrc <= '1';
- MemtoReg <= '1';
- RegWrite <= '1';
- MemRead <= '1';
- MemWrite <= '0';
- Branch <= '0';
- ALUOp(1) <= '0';
- ALUOp(0) <= '0';
- --TYPE SW
- WHEN "101011" => RegDst <= '0'; --X
- Jump <= '0';
- ALUSrc <= '1';
- MemtoReg <= '0'; --X
- RegWrite <= '0';
- MemRead <= '0';
- MemWrite <= '1';
- Branch <= '0';
- ALUOp(1) <= '0';
- ALUOp(0) <= '0';
- --TYPE JUMP
- WHEN "000010" => RegDst <= '0'; --X
- Jump <= '1';
- ALUSrc <= '0';
- MemtoReg <= '0'; --X
- RegWrite <= '0';
- MemRead <= '0';
- MemWrite <= '0';
- Branch <= '0';
- ALUOp(1) <= '1';
- ALUOp(0) <= '0';
- --TYPE BEQ
- WHEN OTHERS => RegDst <= '0'; --X
- Jump <= '0';
- ALUSrc <= '0';
- MemtoReg <= '0'; --X
- RegWrite <= '0';
- MemRead <= '0';
- MemWrite <= '0';
- Branch <= '1';
- ALUOp(1) <= '0';
- ALUOp(0) <= '1';
-
- END CASE;
- END PROCESS;
+ PROCESS(OPCode)
+ BEGIN
+ CASE OPCode IS
+ --TYPE R
+ WHEN "000000" => RegDst <= '1';
+ Jump <= '0';
+ ALUSrc <= '0';
+ MemtoReg <= '0';
+ RegWrite <= '1';
+ MemRead <= '0';
+ MemWrite <= '0';
+ Branch <= '0';
+ ALUOp(1) <= '1';
+ ALUOp(0) <= '0';
+ --TYPE LW
+ WHEN "100011" => RegDst <= '0';
+ Jump <= '0';
+ ALUSrc <= '1';
+ MemtoReg <= '1';
+ RegWrite <= '1';
+ MemRead <= '1';
+ MemWrite <= '0';
+ Branch <= '0';
+ ALUOp(1) <= '0';
+ ALUOp(0) <= '0';
+ --TYPE SW
+ WHEN "101011" => RegDst <= '0'; --X
+ Jump <= '0';
+ ALUSrc <= '1';
+ MemtoReg <= '0'; --X
+ RegWrite <= '0';
+ MemRead <= '0';
+ MemWrite <= '1';
+ Branch <= '0';
+ ALUOp(1) <= '0';
+ ALUOp(0) <= '0';
+ --TYPE JUMP
+ WHEN "000010" => RegDst <= '0'; --X
+ Jump <= '1';
+ ALUSrc <= '0';
+ MemtoReg <= '0'; --X
+ RegWrite <= '0';
+ MemRead <= '0';
+ MemWrite <= '0';
+ Branch <= '0';
+ ALUOp(1) <= '1';
+ ALUOp(0) <= '0';
+ --TYPE BEQ
+ WHEN OTHERS => RegDst <= '0'; --X
+ Jump <= '0';
+ ALUSrc <= '0';
+ MemtoReg <= '0'; --X
+ RegWrite <= '0';
+ MemRead <= '0';
+ MemWrite <= '0';
+ Branch <= '1';
+ ALUOp(1) <= '0';
+ ALUOp(0) <= '1';
+
+ END CASE;
+ END PROCESS;
END ARC_CTRL;
diff --git a/CTRL_WB.o b/CTRL_WB.o
new file mode 100644
index 0000000000000000000000000000000000000000..88d2ec671c7c755b248d211f6559a5a96e711d14
Binary files /dev/null and b/CTRL_WB.o differ
diff --git a/CTRL_WB.vhd b/CTRL_WB.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ddca67b39a5ed686a6fc369a6d774c5e7f9294f3
--- /dev/null
+++ b/CTRL_WB.vhd
@@ -0,0 +1,24 @@
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY CTRL_WB IS
+ PORT (INSTR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+ WB :OUT STD_LOGIC
+ );
+END CTRL_WB;
+
+ARCHITECTURE ARC_CTRL_WB OF CTRL_WB IS
+
+BEGIN
+ PROCESS(INSTR)
+ BEGIN
+ IF INSTR = X"00000000" THEN
+ WB <= '0';
+ ELSE
+ WB <= '1';
+ END IF;
+ END PROCESS;
+END ARC_CTRL_WB;
+
+
diff --git a/EX_MEM_PIPE.o b/EX_MEM_PIPE.o
index 3b20dcd8f62aff83020166977536388927b1a45e..798bbba5248ccdb8e6e774231dd1616701497608 100644
Binary files a/EX_MEM_PIPE.o and b/EX_MEM_PIPE.o differ
diff --git a/EX_MEM_PIPE.vhd b/EX_MEM_PIPE.vhd
index 78e7cabaa42c2cab9215c2e39e1cabafa67987f5..d895281e2d6663050e1bb48fb6fdebcd1982f374 100644
--- a/EX_MEM_PIPE.vhd
+++ b/EX_MEM_PIPE.vhd
@@ -32,7 +32,7 @@ BEGIN
ALU_OUT <= X"00000000"; MTR_OUT <= '0';
REGB_OUT <= X"00000000";
DST_OUT <= "00000";
- ELSIF CLK'EVENT AND CLK = '1' THEN
+ ELSIF CLK'EVENT AND CLK = '0' THEN
WB_OUT <= WB_IN; MEM_R_OUT <= MEM_R_IN;
MEM_W_OUT <= MEM_W_IN; MTR_OUT <= MTR_IN;
REGB_OUT <= REGB_IN; ALU_OUT <= ALU_RESULT_IN;
diff --git a/FORWARD.o b/FORWARD.o
index 758920c7ff43150ea1fa4d7ae47f506e902f937e..d548522353c3ab6c4fab8de9fc7f02c99bd18eae 100644
Binary files a/FORWARD.o and b/FORWARD.o differ
diff --git a/FORWARD.vhd b/FORWARD.vhd
index 530dc6d5b90b299fb6494ae78984ff67d07a7183..8779da0e2114e5a2b62f1499860df8a52ec80a85 100644
--- a/FORWARD.vhd
+++ b/FORWARD.vhd
@@ -43,25 +43,25 @@ BEGIN
ELSIF CLK'EVENT AND CLK = '1' THEN
IF Rd_M = Reg_rs THEN
forw_a(1) <= '1';
- ELSIF
+ ELSE
forw_a(1) <= '0';
END IF;
IF Rd_M = Reg_rt THEN
forw_b(1) <= '1';
- ELSIF
+ ELSE
forw_b(1) <= '0';
END IF;
IF Rd_W = Reg_rs THEN
forw_a(0) <= '1';
- ELSIF
+ ELSE
forw_a(0) <= '0';
END IF;
IF Rd_W = Reg_rt THEN
forw_b(0) <= '1';
- ELSIF
+ ELSE
forw_b(0) <= '0';
END IF;
--forw_a(1) <= '1' WHEN Rd_M = Reg_rs ELSE '0';
diff --git a/ID_EX_PIPE.o b/ID_EX_PIPE.o
index 5a6fd7aa87ceddffcafb708e474cb345d9ae6dc1..6d653531fda22b295f09079cf7c25e957a2e03ed 100644
Binary files a/ID_EX_PIPE.o and b/ID_EX_PIPE.o differ
diff --git a/ID_EX_PIPE.vhd b/ID_EX_PIPE.vhd
index a20dbda31c9956828c4bda1d4a4475f7bde0c526..1d1a9189b25606c996453bd93e0f8b9a0e255ba3 100644
--- a/ID_EX_PIPE.vhd
+++ b/ID_EX_PIPE.vhd
@@ -49,7 +49,7 @@ BEGIN
ALU_SRC_OUT <= '0';
REGDST_OUT <= '0';
RS_OUT <= "00000"; RT_OUT <= "00000"; RD_OUT <= "00000";
- ELSIF CLK'EVENT AND CLK = '1' THEN
+ ELSIF CLK'EVENT AND CLK = '0' THEN
WB_OUT <= WB_IN; MEM_R_OUT <= MEM_R_IN;
MEM_W_OUT <= MEM_W_IN; FUNC_OUT <= FUNC_IN;
ALU_OP_OUT <= ALU_OP_IN; MTR_OUT <= MTR_IN;
diff --git a/IF_ID_PIPE.o b/IF_ID_PIPE.o
index 5541b6b804cfcd9f25b8b73d998a00a6060a0308..8df90865b11391dd87af313145febb94102934c2 100644
Binary files a/IF_ID_PIPE.o and b/IF_ID_PIPE.o differ
diff --git a/IF_ID_PIPE.vhd b/IF_ID_PIPE.vhd
index 0224760988129de0ccc763b789df54feefddcdfe..012a0e4290ba073e7b3fb61f3f6f5db3362ea51e 100644
--- a/IF_ID_PIPE.vhd
+++ b/IF_ID_PIPE.vhd
@@ -25,8 +25,10 @@ BEGIN
IF RESET = '1' THEN
OPCODE <= "000000"; REG_RS <= "00000"; REG_RT <= "00000";
REG_RD <= "00000"; SHAMT <= "00000"; FUNC <= "000000";
- IMMED <= "0000000000000000";
- ELSIF CLK'EVENT AND CLK = '1' THEN
+ IMMED <= X"0000";
+ INSTR_OUT <= X"00000000";
+ ELSIF CLK'EVENT AND CLK = '0' THEN
+ INSTR_OUT <= INSTR;
OPCODE <= INSTR(31 DOWNTO 26);
REG_RS <= INSTR(25 DOWNTO 21);
REG_RT <= INSTR(20 DOWNTO 16);
diff --git a/INST.o b/INST.o
index 5a23ebbc5f02bb3fb18445729fd50adcf5300d34..023454ffb6b381052caa9eb90dbcbbdfbff684db 100644
Binary files a/INST.o and b/INST.o differ
diff --git a/INST.vhd b/INST.vhd
index 69fcb6afbc6cb4d24c56cfdb6980d5431b562492..49cae71cb209bb708b8f0f05019857ccb6ecd082 100644
--- a/INST.vhd
+++ b/INST.vhd
@@ -35,8 +35,8 @@ ARCHITECTURE ARC_INST OF INST IS
TYPE MEMORY IS ARRAY (0 TO 255) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL PROGRAM : MEMORY := (X"00000000",X"00000000",X"00000000",
X"012A4820",X"012A4820",X"012A4820",
- X"00000000",X"00000000",X"00000000",
- X"00000000",X"00000000",X"00000000",
+ X"012A4820",X"012A4820",X"012A4820",
+ X"012A4820",X"012A4820",X"012A4820",
X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",
X"00000000",X"00000000",X"00000000",
diff --git a/MAIN_CTTRL.o b/MAIN_CTTRL.o
index 9b02e3ba9e745a21b56f5111b6d59b6a8c3dc374..63f5531eb811e9f5bae50cf86efac61d1babcff4 100644
Binary files a/MAIN_CTTRL.o and b/MAIN_CTTRL.o differ
diff --git a/MAIN_CTTRL.vhd b/MAIN_CTTRL.vhd
index 8b60228b6e851333688ab53973383d11e3d1c9cd..10528fdd83047e8fafce1b6bab7971e945c91d70 100644
--- a/MAIN_CTTRL.vhd
+++ b/MAIN_CTTRL.vhd
@@ -63,7 +63,6 @@ ARCHITECTURE ARC_MAIN_PROCESSOR OF MAIN_PROCESSOR IS
COMPONENT CTRL IS
PORT(
- Instr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OPCode : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
Func : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
RegDst : OUT STD_LOGIC;
@@ -313,6 +312,13 @@ ARCHITECTURE ARC_MAIN_PROCESSOR OF MAIN_PROCESSOR IS
);
END COMPONENT SUB_BR;
+ COMPONENT CTRL_WB IS
+ PORT (INSTR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ WB : OUT STD_LOGIC
+ );
+ END COMPONENT;
+
+
SIGNAL NOVO_PC : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL PC_OUT : STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL PC4_ID : STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -328,6 +334,8 @@ ARCHITECTURE ARC_MAIN_PROCESSOR OF MAIN_PROCESSOR IS
SIGNAL CTRL_ALUOP : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL CTRL_ALUSRC_EXT_B : STD_LOGIC;
SIGNAL CTRL_REGWRITE : STD_LOGIC;
+ SIGNAL WB_CTRL : STD_LOGIC;
+ SIGNAL WRITEBACK : STD_LOGIC;
SIGNAL OPCODE_ID : STD_LOGIC_VECTOR(5 DOWNTO 0);
SIGNAL INSTRUCTION_ID : STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -402,11 +410,15 @@ BEGIN
---------------------------------------------------------------------------
C_EXTEND_SIGNAL : EXTEND_SIGNAL PORT MAP(IMMED_ID,
EXTENDED_IMMED);
- C_CTRL : CTRL PORT MAP(INSTRUCTION_ID, OPCODE_ID, FUNC_ID, CTRL_SEL_RDRT, CTRL_JUMP,
+ C_CTRL : CTRL PORT MAP(OPCODE_ID, FUNC_ID, CTRL_SEL_RDRT, CTRL_JUMP,
CTRL_BRANCH, CTRL_MEMREAD,
CTRL_MEMTOREG, CTRL_ALUOP,
CTRL_MEMWRITE, CTRL_ALUSRC_EXT_B,
CTRL_REGWRITE);
+ -- regwrite
+ C_WB_CTRL: CTRL_WB PORT MAP(INSTRUCTION_ID, WB_CTRL);
+ AND_WB: AND_1 PORT MAP(WB_CTRL, CTRL_REGWRITE, WRITEBACK);
+
C_REG : REG PORT MAP(CLK, RESET, REGWRITE_WB, RS_ID,
RT_ID, REG_DST_WB, VALUE_WRREG,
REG_A_OUT, REG_B_OUT);
@@ -431,7 +443,7 @@ BEGIN
C_MX_4 : MX_4 PORT MAP(CTRL_JUMP, JUMP_ADDR, SEL_BR_PC4,
NOVO_PC);
- P_IDEX : ID_EX_PIPE PORT MAP(CLK, RESET, CTRL_REGWRITE,
+ P_IDEX : ID_EX_PIPE PORT MAP(CLK, RESET, WRITEBACK,
CTRL_MEMREAD, CTRL_MEMWRITE,
CTRL_MEMTOREG, CTRL_ALUOP,
CTRL_ALUSRC_EXT_B,
@@ -456,12 +468,12 @@ BEGIN
C_MX_2 : MX_2 PORT MAP(ALUSRC_EXT_B_EX, REG_B_OUT_EX,
EXT_IMMED_EX,
SEL_ALU_EXT_B);
- P_FRWD_M_B : MX_2 PORT MAP(FRWD_B(1), ALU_OUT_MEM, SEL_ALU_EXT_B, FRWD_B_OUT);
- P_FRWD_B : MX_2 PORT MAP(FRWD_B(0), ALU_OUT_WB, FRWD_B_OUT, ALU_SRC_B);
+ P_FRWD_M_B : MX_2 PORT MAP(FRWD_B(0), SEL_ALU_EXT_B, ALU_OUT_WB, FRWD_B_OUT);
+ P_FRWD_B : MX_2 PORT MAP(FRWD_B(1), FRWD_B_OUT, ALU_OUT_MEM, ALU_SRC_B);
-- ALU src a
- P_FRWD_M_A : MX_2 PORT MAP(FRWD_A(1), ALU_OUT_MEM, REG_A_OUT_EX, FRWD_A_OUT);
- P_FRWD_A : MX_2 PORT MAP(FRWD_A(0), ALU_OUT_WB, FRWD_A_OUT, ALU_SRC_A);
+ P_FRWD_M_A : MX_2 PORT MAP(FRWD_A(0), REG_A_OUT_EX, ALU_OUT_WB, FRWD_A_OUT);
+ P_FRWD_A : MX_2 PORT MAP(FRWD_A(1), FRWD_A_OUT, ALU_OUT_MEM, ALU_SRC_A);
C_ULA_CTRL : ULA_CTRL PORT MAP(ALUOP_EX, FUNC_EX, ULA_CTRL_OUT);
C_ULA : ULA PORT MAP(ALU_SRC_A, ALU_SRC_B, ULA_CTRL_OUT,
diff --git a/MEM_WB_PIPE.o b/MEM_WB_PIPE.o
index 95a39e52aa9cdd50c1c7ab9121d18117568d44fe..f0c9fcec1d1c4c8dd53ed06feed3de2b6b0146e4 100644
Binary files a/MEM_WB_PIPE.o and b/MEM_WB_PIPE.o differ
diff --git a/MEM_WB_PIPE.vhd b/MEM_WB_PIPE.vhd
index 9a99f05b94a3737970451326ee5c130045939d52..dd2266a77ff0d9d3465530ad626f3fa290450782 100644
--- a/MEM_WB_PIPE.vhd
+++ b/MEM_WB_PIPE.vhd
@@ -27,7 +27,7 @@ BEGIN
WB_OUT <= '0'; MTR_OUT <= '0';
MEM_OUT <= X"00000000"; ALU_OUT <= X"00000000";
RD_OUT <= "00000";
- ELSIF CLK'EVENT AND CLK = '1' THEN
+ ELSIF CLK'EVENT AND CLK = '0' THEN
WB_OUT <= WB_IN; MEM_OUT <= MEM_RES_IN;
ALU_OUT <= ALU_RES_IN; MTR_OUT <= MTR_IN;
RD_OUT <= RD_IN;
diff --git a/REG.vhd b/REG.vhd
index de10a400c5c14e0e5444bfafb9eeee8619f132c0..a22fff37440dff19da459ea2f441619b11ebe2d8 100644
--- a/REG.vhd
+++ b/REG.vhd
@@ -46,7 +46,7 @@ BEGIN
--REALIZA A LEITURA NO ENDEREO SELECIONADO
OUT_A <= REG_1(TO_INTEGER(UNSIGNED(IN_A)));
OUT_B <= REG_2(TO_INTEGER(UNSIGNED(IN_B)));
-
+
--PROCESSO DE LEITURA
PROCESS(CLK, RESET)
BEGIN
diff --git a/compile.sh b/compile.sh
index acfeb2f413cdac0e41dc7b7dabd9039437f57e74..a04fcd0f5d9bcfe1a72e05227776f0f32cf0e9b8 100755
--- a/compile.sh
+++ b/compile.sh
@@ -4,7 +4,7 @@ if [ $# -eq 3 ]; then
ghdl -a --ieee=synopsys -fexplicit *.vhd
ghdl -e --ieee=synopsys -fexplicit TB_MAIN_PROCESSOR
./tb_main_processor --stop-time=$1ns --vcd=$2
- gtkwave $2 $3
+ gtkwave $2 $3 > /dev/null 2>&1
else
echo "Uso: $0 <time> <dump>.vcd <config>.sav"
fi
diff --git a/config.sav b/config.sav
index a2e0c10efd132d32b76d53fd43c17c85e5957e0c..058956d123da752b2acad069de59fecd8b8e6aec 100644
--- a/config.sav
+++ b/config.sav
@@ -1,15 +1,16 @@
[*]
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
-[*] Fri Jun 24 09:19:54 2016
+[*] Thu Jun 30 11:44:58 2016
[*]
[dumpfile] "/nobackup/bcc/gvcc15/scMIPS/ondas.vcd"
-[dumpfile_mtime] "Fri Jun 24 09:06:09 2016"
-[dumpfile_size] 234135
+[dumpfile_mtime] "Thu Jun 30 11:43:01 2016"
+[dumpfile_size] 66547
[savefile] "/nobackup/bcc/gvcc15/scMIPS/config.sav"
[timestart] 0
-[size] 1366 704
+[size] 1366 702
[pos] 108 25
-*-27.748419 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-26.011454 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] uut.
[sst_width] 244
[signals_width] 188
[sst_expanded] 1
@@ -46,7 +47,6 @@ uut.ctrl_jump
@22
uut.jump_addr[31:0]
@200
--
-EXEC
-Dst reg
@28
@@ -59,9 +59,7 @@ uut.def_dest_reg[4:0]
uut.reg_dst_wb[4:0]
uut.reg_dst_mem[4:0]
uut.rs_ex[4:0]
-@23
uut.rt_ex[4:0]
-@22
uut.sel_alu_ext_b[31:0]
@28
uut.frwd_a[1:0]
diff --git a/e~tb_main_processor.o b/e~tb_main_processor.o
index 5b9d53682cbb17e73b3e8ac464f7a6f073ff286a..9e897c80f4c36f8e689064d445d401b7e83a8413 100644
Binary files a/e~tb_main_processor.o and b/e~tb_main_processor.o differ
diff --git a/ondas.vcd b/ondas.vcd
index 1b45f815a9c452ead90f5b53bf1505408d65981c..72f036c24f5456c6a7db5a0ee1787a123035f1a7 100644
--- a/ondas.vcd
+++ b/ondas.vcd
@@ -1,5 +1,5 @@
$date
- Wed Jun 29 15:36:01 2016
+ Thu Jun 30 10:27:25 2016
$end
$version
GHDL v0
@@ -26,83 +26,83 @@ $var reg 1 / ctrl_memtoreg $end
$var reg 2 0 ctrl_aluop[1:0] $end
$var reg 1 1 ctrl_alusrc_ext_b $end
$var reg 1 2 ctrl_regwrite $end
-$var reg 6 3 opcode_id[5:0] $end
-$var reg 32 4 instruction_id[31:0] $end
-$var reg 6 5 func_id[5:0] $end
-$var reg 5 6 rs_id[4:0] $end
-$var reg 5 7 rt_id[4:0] $end
-$var reg 5 8 rd_id[4:0] $end
-$var reg 16 9 immed_id[15:0] $end
-$var reg 32 : extended_immed[31:0] $end
-$var reg 32 ; reg_a_out[31:0] $end
-$var reg 32 < reg_b_out[31:0] $end
-$var reg 32 = sh_l_jump[31:0] $end
-$var reg 32 > sh_l_branch[31:0] $end
-$var reg 32 ? jump_addr[31:0] $end
-$var reg 32 @ branch_addr[31:0] $end
-$var reg 1 A rt_rd_eq $end
-$var reg 1 B take_branch $end
-$var reg 32 C sel_br_pc4[31:0] $end
-$var reg 32 D memory_out[31:0] $end
-$var reg 32 E memory_out_wb[31:0] $end
-$var reg 1 F memtoreg_wb $end
-$var reg 1 G memtoreg_mem $end
-$var reg 1 H memwrite_mem $end
-$var reg 1 I memread_mem $end
-$var reg 1 J memwrite_ex $end
-$var reg 1 K memread_ex $end
-$var reg 1 L memtoreg_ex $end
-$var reg 32 M value_wrreg[31:0] $end
-$var reg 32 N reg_b_out_mem[31:0] $end
-$var reg 32 O sel_alu_ext_b[31:0] $end
-$var reg 5 P rs_ex[4:0] $end
-$var reg 5 Q rt_ex[4:0] $end
-$var reg 5 R rd_ex[4:0] $end
-$var reg 5 S reg_dst_mem[4:0] $end
-$var reg 5 T reg_dst_wb[4:0] $end
-$var reg 1 U regwrite_ex $end
-$var reg 1 V regwrite_mem $end
-$var reg 1 W regwrite_wb $end
-$var reg 32 X ext_immed_ex[31:0] $end
-$var reg 1 Y sel_rdrt_ex $end
-$var reg 5 Z def_dest_reg[4:0] $end
-$var reg 32 [ reg_a_out_ex[31:0] $end
-$var reg 32 \ reg_b_out_ex[31:0] $end
-$var reg 2 ] aluop_ex[1:0] $end
-$var reg 32 ^ alu_out_wb[31:0] $end
-$var reg 32 _ alu_out_mem[31:0] $end
-$var reg 1 ` alusrc_ext_b_ex $end
-$var reg 6 a func_ex[5:0] $end
-$var reg 32 b alu_src_a[31:0] $end
-$var reg 32 c alu_src_b[31:0] $end
-$var reg 32 d alu_out[31:0] $end
-$var reg 3 e ula_ctrl_out[2:0] $end
-$var reg 2 f frwd_a[1:0] $end
-$var reg 2 g frwd_b[1:0] $end
-$var reg 32 h frwd_a_out[31:0] $end
-$var reg 32 i frwd_b_out[31:0] $end
+$var reg 1 3 wb_ctrl $end
+$var reg 1 4 writeback $end
+$var reg 6 5 opcode_id[5:0] $end
+$var reg 32 6 instruction_id[31:0] $end
+$var reg 6 7 func_id[5:0] $end
+$var reg 5 8 rs_id[4:0] $end
+$var reg 5 9 rt_id[4:0] $end
+$var reg 5 : rd_id[4:0] $end
+$var reg 16 ; immed_id[15:0] $end
+$var reg 32 < extended_immed[31:0] $end
+$var reg 32 = reg_a_out[31:0] $end
+$var reg 32 > reg_b_out[31:0] $end
+$var reg 32 ? sh_l_jump[31:0] $end
+$var reg 32 @ sh_l_branch[31:0] $end
+$var reg 32 A jump_addr[31:0] $end
+$var reg 32 B branch_addr[31:0] $end
+$var reg 1 C rt_rd_eq $end
+$var reg 1 D take_branch $end
+$var reg 32 E sel_br_pc4[31:0] $end
+$var reg 32 F memory_out[31:0] $end
+$var reg 32 G memory_out_wb[31:0] $end
+$var reg 1 H memtoreg_wb $end
+$var reg 1 I memtoreg_mem $end
+$var reg 1 J memwrite_mem $end
+$var reg 1 K memread_mem $end
+$var reg 1 L memwrite_ex $end
+$var reg 1 M memread_ex $end
+$var reg 1 N memtoreg_ex $end
+$var reg 32 O value_wrreg[31:0] $end
+$var reg 32 P reg_b_out_mem[31:0] $end
+$var reg 32 Q sel_alu_ext_b[31:0] $end
+$var reg 5 R rs_ex[4:0] $end
+$var reg 5 S rt_ex[4:0] $end
+$var reg 5 T rd_ex[4:0] $end
+$var reg 5 U reg_dst_mem[4:0] $end
+$var reg 5 V reg_dst_wb[4:0] $end
+$var reg 1 W regwrite_ex $end
+$var reg 1 X regwrite_mem $end
+$var reg 1 Y regwrite_wb $end
+$var reg 32 Z ext_immed_ex[31:0] $end
+$var reg 1 [ sel_rdrt_ex $end
+$var reg 5 \ def_dest_reg[4:0] $end
+$var reg 32 ] reg_a_out_ex[31:0] $end
+$var reg 32 ^ reg_b_out_ex[31:0] $end
+$var reg 2 _ aluop_ex[1:0] $end
+$var reg 32 ` alu_out_wb[31:0] $end
+$var reg 32 a alu_out_mem[31:0] $end
+$var reg 1 b alusrc_ext_b_ex $end
+$var reg 6 c func_ex[5:0] $end
+$var reg 32 d alu_src_a[31:0] $end
+$var reg 32 e alu_src_b[31:0] $end
+$var reg 32 f alu_out[31:0] $end
+$var reg 3 g ula_ctrl_out[2:0] $end
+$var reg 2 h frwd_a[1:0] $end
+$var reg 2 i frwd_b[1:0] $end
+$var reg 32 j frwd_a_out[31:0] $end
+$var reg 32 k frwd_b_out[31:0] $end
$scope module c_pc $end
-$var reg 1 j clk $end
-$var reg 1 k reset $end
-$var reg 1 l pc_w $end
-$var reg 32 m in_a[31:0] $end
-$var reg 32 n out_a[31:0] $end
-$upscope $end
-$scope module c_add_pc $end
+$var reg 1 l clk $end
+$var reg 1 m reset $end
+$var reg 1 n pc_w $end
$var reg 32 o in_a[31:0] $end
$var reg 32 p out_a[31:0] $end
$upscope $end
-$scope module c_inst $end
+$scope module c_add_pc $end
$var reg 32 q in_a[31:0] $end
$var reg 32 r out_a[31:0] $end
+$upscope $end
+$scope module c_inst $end
+$var reg 32 s in_a[31:0] $end
+$var reg 32 t out_a[31:0] $end
$comment program is not handled $end
$upscope $end
$scope module p_ifid $end
-$var reg 1 s clk $end
-$var reg 1 t reset $end
-$var reg 32 u instr[31:0] $end
-$var reg 32 v pc4_in[31:0] $end
-$var reg 32 w pc4_out[31:0] $end
+$var reg 1 u clk $end
+$var reg 1 v reset $end
+$var reg 32 w instr[31:0] $end
$var reg 32 x instr_out[31:0] $end
$var reg 6 y opcode[5:0] $end
$var reg 5 z reg_rs[4:0] $end
@@ -129,203 +129,212 @@ $var reg 1 -" memwrite $end
$var reg 1 ." alusrc $end
$var reg 1 /" regwrite $end
$upscope $end
+$scope module c_wb_ctrl $end
+$var reg 32 0" instr[31:0] $end
+$var reg 1 1" wb $end
+$upscope $end
+$scope module and_wb $end
+$var reg 1 2" branch $end
+$var reg 1 3" in_a $end
+$var reg 1 4" out_a $end
+$upscope $end
$scope module c_reg $end
-$var reg 1 0" clk $end
-$var reg 1 1" reset $end
-$var reg 1 2" regwrite $end
-$var reg 5 3" in_a[4:0] $end
-$var reg 5 4" in_b[4:0] $end
-$var reg 5 5" in_c[4:0] $end
-$var reg 32 6" in_d[31:0] $end
-$var reg 32 7" out_a[31:0] $end
-$var reg 32 8" out_b[31:0] $end
+$var reg 1 5" clk $end
+$var reg 1 6" reset $end
+$var reg 1 7" regwrite $end
+$var reg 5 8" in_a[4:0] $end
+$var reg 5 9" in_b[4:0] $end
+$var reg 5 :" in_c[4:0] $end
+$var reg 32 ;" in_d[31:0] $end
+$var reg 32 <" out_a[31:0] $end
+$var reg 32 =" out_b[31:0] $end
$comment reg_1 is not handled $end
$comment reg_2 is not handled $end
$upscope $end
$scope module c_sl_1 $end
-$var reg 32 9" in_a[31:0] $end
-$var reg 32 :" out_a[31:0] $end
+$var reg 32 >" in_a[31:0] $end
+$var reg 32 ?" out_a[31:0] $end
$upscope $end
$scope module c_concat $end
-$var reg 32 ;" in_a[31:0] $end
-$var reg 32 <" in_b[31:0] $end
-$var reg 32 =" out_a[31:0] $end
-$var reg 32 >" monta_out_s[31:0] $end
+$var reg 32 @" in_a[31:0] $end
+$var reg 32 A" in_b[31:0] $end
+$var reg 32 B" out_a[31:0] $end
+$var reg 32 C" monta_out_s[31:0] $end
$upscope $end
$scope module c_sl_2 $end
-$var reg 32 ?" in_a[31:0] $end
-$var reg 32 @" out_a[31:0] $end
+$var reg 32 D" in_a[31:0] $end
+$var reg 32 E" out_a[31:0] $end
$upscope $end
$scope module c_add $end
-$var reg 32 A" in_a[31:0] $end
-$var reg 32 B" in_b[31:0] $end
-$var reg 32 C" out_a[31:0] $end
+$var reg 32 F" in_a[31:0] $end
+$var reg 32 G" in_b[31:0] $end
+$var reg 32 H" out_a[31:0] $end
$upscope $end
$scope module c_sub_br $end
-$var reg 32 D" in_a[31:0] $end
-$var reg 32 E" in_b[31:0] $end
-$var reg 1 F" out_a $end
-$var reg 32 G" subtr[31:0] $end
+$var reg 32 I" in_a[31:0] $end
+$var reg 32 J" in_b[31:0] $end
+$var reg 1 K" out_a $end
+$var reg 32 L" subtr[31:0] $end
$upscope $end
$scope module c_and_1 $end
-$var reg 1 H" branch $end
-$var reg 1 I" in_a $end
-$var reg 1 J" out_a $end
+$var reg 1 M" branch $end
+$var reg 1 N" in_a $end
+$var reg 1 O" out_a $end
$upscope $end
$scope module c_mx_3 $end
-$var reg 32 K" in_a[31:0] $end
-$var reg 32 L" in_b[31:0] $end
-$var reg 1 M" in_c $end
-$var reg 32 N" out_a[31:0] $end
-$upscope $end
-$scope module c_mx_4 $end
-$var reg 1 O" jump $end
$var reg 32 P" in_a[31:0] $end
$var reg 32 Q" in_b[31:0] $end
-$var reg 32 R" out_a[31:0] $end
+$var reg 1 R" in_c $end
+$var reg 32 S" out_a[31:0] $end
+$upscope $end
+$scope module c_mx_4 $end
+$var reg 1 T" jump $end
+$var reg 32 U" in_a[31:0] $end
+$var reg 32 V" in_b[31:0] $end
+$var reg 32 W" out_a[31:0] $end
$upscope $end
$scope module p_idex $end
-$var reg 1 S" clk $end
-$var reg 1 T" reset $end
-$var reg 1 U" wb_in $end
-$var reg 1 V" mem_r_in $end
-$var reg 1 W" mem_w_in $end
-$var reg 1 X" mtr_in $end
-$var reg 2 Y" alu_op_in[1:0] $end
-$var reg 1 Z" alu_src_in $end
-$var reg 6 [" func_in[5:0] $end
-$var reg 1 \" regdst_in $end
-$var reg 5 ]" rs_in[4:0] $end
-$var reg 5 ^" rt_in[4:0] $end
-$var reg 5 _" rd_in[4:0] $end
-$var reg 32 `" inp_a[31:0] $end
-$var reg 32 a" inp_b[31:0] $end
-$var reg 32 b" ext_in[31:0] $end
-$var reg 1 c" wb_out $end
-$var reg 1 d" mem_r_out $end
-$var reg 1 e" mem_w_out $end
-$var reg 2 f" alu_op_out[1:0] $end
-$var reg 1 g" alu_src_out $end
-$var reg 6 h" func_out[5:0] $end
-$var reg 1 i" mtr_out $end
-$var reg 1 j" regdst_out $end
-$var reg 5 k" rs_out[4:0] $end
-$var reg 5 l" rt_out[4:0] $end
-$var reg 5 m" rd_out[4:0] $end
-$var reg 32 n" a_out[31:0] $end
-$var reg 32 o" b_out[31:0] $end
-$var reg 32 p" ext_out[31:0] $end
+$var reg 1 X" clk $end
+$var reg 1 Y" reset $end
+$var reg 1 Z" wb_in $end
+$var reg 1 [" mem_r_in $end
+$var reg 1 \" mem_w_in $end
+$var reg 1 ]" mtr_in $end
+$var reg 2 ^" alu_op_in[1:0] $end
+$var reg 1 _" alu_src_in $end
+$var reg 6 `" func_in[5:0] $end
+$var reg 1 a" regdst_in $end
+$var reg 5 b" rs_in[4:0] $end
+$var reg 5 c" rt_in[4:0] $end
+$var reg 5 d" rd_in[4:0] $end
+$var reg 32 e" inp_a[31:0] $end
+$var reg 32 f" inp_b[31:0] $end
+$var reg 32 g" ext_in[31:0] $end
+$var reg 1 h" wb_out $end
+$var reg 1 i" mem_r_out $end
+$var reg 1 j" mem_w_out $end
+$var reg 2 k" alu_op_out[1:0] $end
+$var reg 1 l" alu_src_out $end
+$var reg 6 m" func_out[5:0] $end
+$var reg 1 n" mtr_out $end
+$var reg 1 o" regdst_out $end
+$var reg 5 p" rs_out[4:0] $end
+$var reg 5 q" rt_out[4:0] $end
+$var reg 5 r" rd_out[4:0] $end
+$var reg 32 s" a_out[31:0] $end
+$var reg 32 t" b_out[31:0] $end
+$var reg 32 u" ext_out[31:0] $end
$upscope $end
$scope module c_mx_1 $end
-$var reg 1 q" regdst $end
-$var reg 5 r" in_a[4:0] $end
-$var reg 5 s" in_b[4:0] $end
-$var reg 5 t" out_a[4:0] $end
+$var reg 1 v" regdst $end
+$var reg 5 w" in_a[4:0] $end
+$var reg 5 x" in_b[4:0] $end
+$var reg 5 y" out_a[4:0] $end
$upscope $end
$scope module frwd_u $end
-$var reg 1 u" clk $end
-$var reg 1 v" reset $end
-$var reg 5 w" reg_rt[4:0] $end
-$var reg 5 x" reg_rs[4:0] $end
-$var reg 5 y" rd_m[4:0] $end
-$var reg 5 z" rd_w[4:0] $end
-$var reg 2 {" forw_a[1:0] $end
-$var reg 2 |" forw_b[1:0] $end
+$var reg 1 z" clk $end
+$var reg 1 {" reset $end
+$var reg 5 |" reg_rt[4:0] $end
+$var reg 5 }" reg_rs[4:0] $end
+$var reg 5 !# rd_m[4:0] $end
+$var reg 5 "# rd_w[4:0] $end
+$var reg 2 ## forw_a[1:0] $end
+$var reg 2 $# forw_b[1:0] $end
$upscope $end
$scope module c_mx_2 $end
-$var reg 1 }" alusrc $end
-$var reg 32 !# in_a[31:0] $end
-$var reg 32 "# in_b[31:0] $end
-$var reg 32 ## out_a[31:0] $end
+$var reg 1 %# alusrc $end
+$var reg 32 &# in_a[31:0] $end
+$var reg 32 '# in_b[31:0] $end
+$var reg 32 (# out_a[31:0] $end
$upscope $end
$scope module p_frwd_m_b $end
-$var reg 1 $# alusrc $end
-$var reg 32 %# in_a[31:0] $end
-$var reg 32 &# in_b[31:0] $end
-$var reg 32 '# out_a[31:0] $end
+$var reg 1 )# alusrc $end
+$var reg 32 *# in_a[31:0] $end
+$var reg 32 +# in_b[31:0] $end
+$var reg 32 ,# out_a[31:0] $end
$upscope $end
$scope module p_frwd_b $end
-$var reg 1 (# alusrc $end
-$var reg 32 )# in_a[31:0] $end
-$var reg 32 *# in_b[31:0] $end
-$var reg 32 +# out_a[31:0] $end
+$var reg 1 -# alusrc $end
+$var reg 32 .# in_a[31:0] $end
+$var reg 32 /# in_b[31:0] $end
+$var reg 32 0# out_a[31:0] $end
$upscope $end
$scope module p_frwd_m_a $end
-$var reg 1 ,# alusrc $end
-$var reg 32 -# in_a[31:0] $end
-$var reg 32 .# in_b[31:0] $end
-$var reg 32 /# out_a[31:0] $end
+$var reg 1 1# alusrc $end
+$var reg 32 2# in_a[31:0] $end
+$var reg 32 3# in_b[31:0] $end
+$var reg 32 4# out_a[31:0] $end
$upscope $end
$scope module p_frwd_a $end
-$var reg 1 0# alusrc $end
-$var reg 32 1# in_a[31:0] $end
-$var reg 32 2# in_b[31:0] $end
-$var reg 32 3# out_a[31:0] $end
+$var reg 1 5# alusrc $end
+$var reg 32 6# in_a[31:0] $end
+$var reg 32 7# in_b[31:0] $end
+$var reg 32 8# out_a[31:0] $end
$upscope $end
$scope module c_ula_ctrl $end
-$var reg 2 4# aluop[1:0] $end
-$var reg 6 5# in_a[5:0] $end
-$var reg 3 6# out_a[2:0] $end
+$var reg 2 9# aluop[1:0] $end
+$var reg 6 :# in_a[5:0] $end
+$var reg 3 ;# out_a[2:0] $end
$upscope $end
$scope module c_ula $end
-$var reg 32 7# in_a[31:0] $end
-$var reg 32 8# in_b[31:0] $end
-$var reg 3 9# in_c[2:0] $end
-$var reg 32 :# out_a[31:0] $end
-$var reg 1 ;# zero $end
-$var reg 32 <# data_rs[31:0] $end
-$var reg 32 =# data_rt[31:0] $end
-$var reg 3 ># ula_ctrl[2:0] $end
-$var reg 32 ?# data_alu_result[31:0] $end
+$var reg 32 <# in_a[31:0] $end
+$var reg 32 =# in_b[31:0] $end
+$var reg 3 ># in_c[2:0] $end
+$var reg 32 ?# out_a[31:0] $end
+$var reg 1 @# zero $end
+$var reg 32 A# data_rs[31:0] $end
+$var reg 32 B# data_rt[31:0] $end
+$var reg 3 C# ula_ctrl[2:0] $end
+$var reg 32 D# data_alu_result[31:0] $end
$upscope $end
$scope module p_exmem $end
-$var reg 1 @# clk $end
-$var reg 1 A# reset $end
-$var reg 1 B# wb_in $end
-$var reg 1 C# mem_r_in $end
-$var reg 1 D# mem_w_in $end
-$var reg 1 E# mtr_in $end
-$var reg 5 F# dst_in[4:0] $end
-$var reg 32 G# regb_in[31:0] $end
-$var reg 32 H# alu_result_in[31:0] $end
-$var reg 1 I# mtr_out $end
-$var reg 1 J# wb_out $end
-$var reg 1 K# mem_r_out $end
-$var reg 1 L# mem_w_out $end
-$var reg 5 M# dst_out[4:0] $end
-$var reg 32 N# regb_out[31:0] $end
-$var reg 32 O# alu_out[31:0] $end
+$var reg 1 E# clk $end
+$var reg 1 F# reset $end
+$var reg 1 G# wb_in $end
+$var reg 1 H# mem_r_in $end
+$var reg 1 I# mem_w_in $end
+$var reg 1 J# mtr_in $end
+$var reg 5 K# dst_in[4:0] $end
+$var reg 32 L# regb_in[31:0] $end
+$var reg 32 M# alu_result_in[31:0] $end
+$var reg 1 N# mtr_out $end
+$var reg 1 O# wb_out $end
+$var reg 1 P# mem_r_out $end
+$var reg 1 Q# mem_w_out $end
+$var reg 5 R# dst_out[4:0] $end
+$var reg 32 S# regb_out[31:0] $end
+$var reg 32 T# alu_out[31:0] $end
$upscope $end
$scope module c_mem $end
-$var reg 1 P# clk $end
-$var reg 1 Q# reset $end
-$var reg 1 R# memwrite $end
-$var reg 1 S# memread $end
-$var reg 32 T# in_a[31:0] $end
-$var reg 32 U# in_b[31:0] $end
-$var reg 32 V# out_a[31:0] $end
+$var reg 1 U# clk $end
+$var reg 1 V# reset $end
+$var reg 1 W# memwrite $end
+$var reg 1 X# memread $end
+$var reg 32 Y# in_a[31:0] $end
+$var reg 32 Z# in_b[31:0] $end
+$var reg 32 [# out_a[31:0] $end
$comment ram is not handled $end
-$var reg 32 W# adress[31:0] $end
+$var reg 32 \# adress[31:0] $end
$upscope $end
$scope module p_memwb $end
-$var reg 1 X# clk $end
-$var reg 1 Y# reset $end
-$var reg 1 Z# wb_in $end
-$var reg 32 [# mem_res_in[31:0] $end
-$var reg 32 \# alu_res_in[31:0] $end
-$var reg 1 ]# mtr_in $end
-$var reg 5 ^# rd_in[4:0] $end
-$var reg 1 _# wb_out $end
-$var reg 1 `# mtr_out $end
-$var reg 32 a# mem_out[31:0] $end
-$var reg 32 b# alu_out[31:0] $end
-$var reg 5 c# rd_out[4:0] $end
+$var reg 1 ]# clk $end
+$var reg 1 ^# reset $end
+$var reg 1 _# wb_in $end
+$var reg 32 `# mem_res_in[31:0] $end
+$var reg 32 a# alu_res_in[31:0] $end
+$var reg 1 b# mtr_in $end
+$var reg 5 c# rd_in[4:0] $end
+$var reg 1 d# wb_out $end
+$var reg 1 e# mtr_out $end
+$var reg 32 f# mem_out[31:0] $end
+$var reg 32 g# alu_out[31:0] $end
+$var reg 5 h# rd_out[4:0] $end
$upscope $end
$scope module c_mx_5 $end
-$var reg 1 d# memtoreg $end
-$var reg 32 e# in_a[31:0] $end
-$var reg 32 f# in_b[31:0] $end
-$var reg 32 g# out_a[31:0] $end
+$var reg 1 i# memtoreg $end
+$var reg 32 j# in_a[31:0] $end
+$var reg 32 k# in_b[31:0] $end
+$var reg 32 l# out_a[31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
@@ -336,7 +345,7 @@ $enddefinitions $end
1$
b00000000010000000000000000000100 %
b00000000010000000000000000000000 &
-b00000000010000000000000000000100 '
+bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU '
b00000000010000000000000000000100 (
b00000000000000000000000000000000 )
1*
@@ -347,77 +356,77 @@ b00000000000000000000000000000000 )
0/
b10 0
01
-02
-b000000 3
-bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU 4
+12
+03
+04
b000000 5
-b00000 6
-b00000 7
+b00000000000000000000000000000000 6
+b000000 7
b00000 8
-b0000000000000000 9
-b00000000000000000000000000000000 :
-b00000000000000000000000000000000 ;
+b00000 9
+b00000 :
+b0000000000000000 ;
b00000000000000000000000000000000 <
-bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU00 =
+b00000000000000000000000000000000 =
b00000000000000000000000000000000 >
-b0000UUUUUUUUUUUUUUUUUUUUUUUUUU00 ?
-b00000000010000000000000000000100 @
-1A
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-b00000000010000000000000000000100 C
-bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU D
-b00000000000000000000000000000000 E
-0F
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b00000000000000000000000000000000 O
-b00000 P
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b00000 R
b00000 S
b00000 T
-0U
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0W
-bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU X
+0X
0Y
-b00000 Z
-b00000000000000000000000000000000 [
-b00000000000000000000000000000000 \
-b00 ]
+bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU Z
+0[
+b00000 \
+b00000000000000000000000000000000 ]
b00000000000000000000000000000000 ^
-b00000000000000000000000000000000 _
-0`
-b000000 a
-b00000000000000000000000000000000 b
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+b00 _
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b00000000000000000000000000000000 d
-b010 e
-b00 f
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-b00000000010000000000000000000100 m
-b00000000010000000000000000000000 n
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b000000 y
b00000 z
b00000 {
@@ -437,354 +446,330 @@ b000000 &"
b10 ,"
0-"
0."
-0/"
-00"
-11"
+1/"
+b00000000000000000000000000000000 0"
+01"
02"
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diff --git a/tb_main_processor b/tb_main_processor
index d28dfc4b6264a1c180d2e48f085fd2b494c90b47..324f0d20308323495fb7f639a28396a9753704eb 100755
Binary files a/tb_main_processor and b/tb_main_processor differ
diff --git a/work-obj93.cf b/work-obj93.cf
index 7963c850b92020078df3bd09f44b6afd3188b19f..864399088d5c28fc9d8e418c8fb16052c32d1c06 100644
--- a/work-obj93.cf
+++ b/work-obj93.cf
@@ -1,82 +1,85 @@
v 3
-file . "SL_2.vhd" "20160616164459.000" "20160629144130.637":
- entity sl_2 at 21( 999) + 0 on 4165;
- architecture arc_sl_2 of sl_2 at 32( 1203) + 0 on 4166;
-file . "REG.vhd" "20160629170547.000" "20160629144130.530":
- entity reg at 21( 999) + 0 on 4161;
- architecture arc_reg of reg at 39( 1464) + 0 on 4162;
-file . "MX_5.vhd" "20160616164459.000" "20160629144130.439":
- entity mx_5 at 21( 999) + 0 on 4157;
- architecture arc_mx_5 of mx_5 at 32( 1252) + 0 on 4158;
-file . "MX_3.vhd" "20160616164459.000" "20160629144130.369":
- entity mx_3 at 21( 999) + 0 on 4153;
- architecture arc_mx_3 of mx_3 at 33( 1250) + 0 on 4154;
-file . "MX_1.vhd" "20160616164459.000" "20160629144130.288":
- entity mx_1 at 21( 999) + 0 on 4149;
- architecture arc_mx_1 of mx_1 at 33( 1261) + 0 on 4150;
-file . "MEM.vhd" "20160623172637.000" "20160629144130.169":
- entity mem at 21( 999) + 0 on 4145;
- architecture arc_mem of mem at 37( 1363) + 0 on 4146;
-file . "INST.vhd" "20160623173836.000" "20160629144129.965":
- entity inst at 21( 999) + 0 on 4141;
- architecture arc_inst of inst at 33( 1199) + 0 on 4142;
-file . "ID_EX_PIPE.vhd" "20160623192429.000" "20160629144129.856":
- entity id_ex_pipe at 1( 0) + 0 on 4137;
- architecture arc_id_ex_pipe of id_ex_pipe at 39( 1452) + 0 on 4138;
-file . "EXTEND.vhd" "20160616164459.000" "20160629153601.659":
- entity extend_signal at 23( 1082) + 0 on 4265;
- architecture arc_extend_signal of extend_signal at 34( 1306) + 0 on 4266;
-file . "CTRL.vhd" "20160629183559.000" "20160629153601.561":
- entity ctrl at 21( 999) + 0 on 4261;
- architecture arc_ctrl of ctrl at 41( 1549) + 0 on 4262;
-file . "AND.vhd" "20160616164459.000" "20160629153601.492":
- entity and_1 at 21( 1000) + 0 on 4257;
- architecture arc_and_1 of and_1 at 32( 1179) + 0 on 4258;
-file . "ADD_PC.vhd" "20160616164459.000" "20160629153601.421":
- entity add_pc at 21( 999) + 0 on 4253;
- architecture arc_add_pc of add_pc at 32( 1202) + 0 on 4254;
-file . "MAIN_CTTRL.vhd" "20160629174119.000" "20160629144130.052":
- entity main_processor at 21( 999) + 0 on 4143;
- architecture arc_main_processor of main_processor at 32( 1183) + 0 on 4144;
-file . "TB_MAIN_PROCESSOR.vhd" "20160629172443.000" "20160629144130.728":
- entity tb_main_processor at 28( 951) + 0 on 4169;
- architecture behavior of tb_main_processor at 38( 1200) + 0 on 4170;
-file . "PC.vhd" "20160622231950.000" "20160629144130.491":
- entity pc at 21( 1001) + 0 on 4159;
- architecture arc_pc of pc at 34( 1283) + 0 on 4160;
-file . "ADD.vhd" "20160616164459.000" "20160629153601.458":
- entity add at 21( 999) + 0 on 4255;
- architecture arc_add of add at 33( 1249) + 0 on 4256;
-file . "CONCAT.vhd" "20160616164459.000" "20160629153601.523":
- entity concat at 21( 1000) + 0 on 4259;
- architecture arc_concat of concat at 32( 1245) + 0 on 4260;
-file . "EX_MEM_PIPE.vhd" "20160624020713.000" "20160629153601.613":
- entity ex_mem_pipe at 1( 0) + 0 on 4263;
- architecture arc_ex_mem_pipe of ex_mem_pipe at 25( 763) + 0 on 4264;
-file . "IF_ID_PIPE.vhd" "20160629172006.000" "20160629144129.913":
- entity if_id_pipe at 1( 0) + 0 on 4139;
- architecture arc_if_id_pipe of if_id_pipe at 22( 699) + 0 on 4140;
-file . "MEM_WB_PIPE.vhd" "20160623111712.000" "20160629144130.227":
- entity mem_wb_pipe at 1( 0) + 0 on 4147;
- architecture arc_mem_wb_pipe of mem_wb_pipe at 21( 622) + 0 on 4148;
-file . "MX_2.vhd" "20160616164459.000" "20160629144130.324":
- entity mx_2 at 21( 999) + 0 on 4151;
- architecture arc_mx_2 of mx_2 at 33( 1267) + 0 on 4152;
-file . "MX_4.vhd" "20160616164459.000" "20160629144130.404":
- entity mx_4 at 21( 999) + 0 on 4155;
- architecture arc_mx_4 of mx_4 at 33( 1250) + 0 on 4156;
-file . "SL_1.vhd" "20160616164459.000" "20160629144130.594":
- entity sl_1 at 21( 999) + 0 on 4163;
- architecture arc_sl_1 of sl_1 at 32( 1205) + 0 on 4164;
-file . "SUB_BR.vhd" "20160623130105.000" "20160629144130.672":
- entity sub_br at 21( 999) + 0 on 4167;
- architecture arc_sub_br of sub_br at 33( 1239) + 0 on 4168;
-file . "ULA_CTRL.vhd" "20160616164459.000" "20160629144130.774":
- entity ula_ctrl at 21( 999) + 0 on 4171;
- architecture arc_ula_ctrl of ula_ctrl at 32( 1244) + 0 on 4172;
-file . "ULA.vhd" "20160616164459.000" "20160629144130.823":
- entity ula at 21( 999) + 0 on 4173;
- architecture arc_ula of ula at 37( 1399) + 0 on 4174;
-file . "FORWARD.vhd" "20160623180240.000" "20160629144129.814":
- entity frwd at 21( 997) + 0 on 4135;
- architecture arc_frwd of frwd at 35( 1458) + 0 on 4136;
+file . "CTRL_WB.vhd" "20160630121101.000" "20160630102721.963":
+ entity ctrl_wb at 1( 0) + 0 on 5227;
+ architecture arc_ctrl_wb of ctrl_wb at 11( 183) + 0 on 5228;
+file . "FORWARD.vhd" "20160630013649.000" "20160630102722.192":
+ entity frwd at 21( 997) + 0 on 5233;
+ architecture arc_frwd of frwd at 35( 1458) + 0 on 5234;
+file . "ULA.vhd" "20160616164459.000" "20160630102724.225":
+ entity ula at 21( 999) + 0 on 5271;
+ architecture arc_ula of ula at 37( 1399) + 0 on 5272;
+file . "ULA_CTRL.vhd" "20160616164459.000" "20160630102724.142":
+ entity ula_ctrl at 21( 999) + 0 on 5269;
+ architecture arc_ula_ctrl of ula_ctrl at 32( 1244) + 0 on 5270;
+file . "SUB_BR.vhd" "20160623130105.000" "20160630102723.977":
+ entity sub_br at 21( 999) + 0 on 5265;
+ architecture arc_sub_br of sub_br at 33( 1239) + 0 on 5266;
+file . "SL_1.vhd" "20160616164459.000" "20160630102723.837":
+ entity sl_1 at 21( 999) + 0 on 5261;
+ architecture arc_sl_1 of sl_1 at 32( 1205) + 0 on 5262;
+file . "MX_4.vhd" "20160616164459.000" "20160630102723.480":
+ entity mx_4 at 21( 999) + 0 on 5253;
+ architecture arc_mx_4 of mx_4 at 33( 1250) + 0 on 5254;
+file . "MX_2.vhd" "20160616164459.000" "20160630102723.345":
+ entity mx_2 at 21( 999) + 0 on 5249;
+ architecture arc_mx_2 of mx_2 at 33( 1267) + 0 on 5250;
+file . "MEM_WB_PIPE.vhd" "20160630132639.000" "20160630102723.186":
+ entity mem_wb_pipe at 1( 0) + 0 on 5245;
+ architecture arc_mem_wb_pipe of mem_wb_pipe at 21( 622) + 0 on 5246;
+file . "IF_ID_PIPE.vhd" "20160630132650.000" "20160630102722.431":
+ entity if_id_pipe at 1( 0) + 0 on 5237;
+ architecture arc_if_id_pipe of if_id_pipe at 20( 600) + 0 on 5238;
+file . "EX_MEM_PIPE.vhd" "20160630132613.000" "20160630102722.025":
+ entity ex_mem_pipe at 1( 0) + 0 on 5229;
+ architecture arc_ex_mem_pipe of ex_mem_pipe at 25( 763) + 0 on 5230;
+file . "CONCAT.vhd" "20160616164459.000" "20160630102721.754":
+ entity concat at 21( 1000) + 0 on 5223;
+ architecture arc_concat of concat at 32( 1245) + 0 on 5224;
+file . "ADD.vhd" "20160616164459.000" "20160630102721.576":
+ entity add at 21( 999) + 0 on 5219;
+ architecture arc_add of add at 33( 1249) + 0 on 5220;
+file . "PC.vhd" "20160622231950.000" "20160630102723.613":
+ entity pc at 21( 1001) + 0 on 5257;
+ architecture arc_pc of pc at 34( 1283) + 0 on 5258;
+file . "TB_MAIN_PROCESSOR.vhd" "20160629172443.000" "20160630102724.075":
+ entity tb_main_processor at 28( 951) + 0 on 5267;
+ architecture behavior of tb_main_processor at 38( 1200) + 0 on 5268;
+file . "MAIN_CTTRL.vhd" "20160630125828.000" "20160630102722.763":
+ entity main_processor at 21( 999) + 0 on 5241;
+ architecture arc_main_processor of main_processor at 32( 1183) + 0 on 5242;
+file . "ADD_PC.vhd" "20160616164459.000" "20160630102721.495":
+ entity add_pc at 21( 999) + 0 on 5217;
+ architecture arc_add_pc of add_pc at 32( 1202) + 0 on 5218;
+file . "AND.vhd" "20160616164459.000" "20160630102721.694":
+ entity and_1 at 21( 1000) + 0 on 5221;
+ architecture arc_and_1 of and_1 at 32( 1179) + 0 on 5222;
+file . "CTRL.vhd" "20160630121346.000" "20160630102721.824":
+ entity ctrl at 21( 999) + 0 on 5225;
+ architecture arc_ctrl of ctrl at 40( 1482) + 0 on 5226;
+file . "EXTEND.vhd" "20160616164459.000" "20160630102722.125":
+ entity extend_signal at 23( 1082) + 0 on 5231;
+ architecture arc_extend_signal of extend_signal at 34( 1306) + 0 on 5232;
+file . "ID_EX_PIPE.vhd" "20160630132521.000" "20160630102722.294":
+ entity id_ex_pipe at 1( 0) + 0 on 5235;
+ architecture arc_id_ex_pipe of id_ex_pipe at 39( 1452) + 0 on 5236;
+file . "INST.vhd" "20160630132720.000" "20160630102722.548":
+ entity inst at 21( 999) + 0 on 5239;
+ architecture arc_inst of inst at 33( 1199) + 0 on 5240;
+file . "MEM.vhd" "20160623172637.000" "20160630102723.078":
+ entity mem at 21( 999) + 0 on 5243;
+ architecture arc_mem of mem at 37( 1363) + 0 on 5244;
+file . "MX_1.vhd" "20160616164459.000" "20160630102723.275":
+ entity mx_1 at 21( 999) + 0 on 5247;
+ architecture arc_mx_1 of mx_1 at 33( 1261) + 0 on 5248;
+file . "MX_3.vhd" "20160616164459.000" "20160630102723.413":
+ entity mx_3 at 21( 999) + 0 on 5251;
+ architecture arc_mx_3 of mx_3 at 33( 1250) + 0 on 5252;
+file . "MX_5.vhd" "20160616164459.000" "20160630102723.546":
+ entity mx_5 at 21( 999) + 0 on 5255;
+ architecture arc_mx_5 of mx_5 at 32( 1252) + 0 on 5256;
+file . "REG.vhd" "20160630014027.000" "20160630102723.687":
+ entity reg at 21( 999) + 0 on 5259;
+ architecture arc_reg of reg at 39( 1464) + 0 on 5260;
+file . "SL_2.vhd" "20160616164459.000" "20160630102723.907":
+ entity sl_2 at 21( 999) + 0 on 5263;
+ architecture arc_sl_2 of sl_2 at 32( 1203) + 0 on 5264;