diff --git a/ADD.o b/ADD.o
new file mode 100644
index 0000000000000000000000000000000000000000..77c31d1fa21cbb6ee8d63e53a3179ad26fce6c8c
Binary files /dev/null and b/ADD.o differ
diff --git a/ADD_PC.o b/ADD_PC.o
new file mode 100644
index 0000000000000000000000000000000000000000..5d00b7d6d5d915a55b3a2ea523edea435c07c680
Binary files /dev/null and b/ADD_PC.o differ
diff --git a/AND.o b/AND.o
new file mode 100644
index 0000000000000000000000000000000000000000..9464fa1a68203ad8dc378dafcdaafab52eef6d1a
Binary files /dev/null and b/AND.o differ
diff --git a/CONCAT.o b/CONCAT.o
new file mode 100644
index 0000000000000000000000000000000000000000..fd6adeafd1b1baa0cbce5383e4cb49a637303751
Binary files /dev/null and b/CONCAT.o differ
diff --git a/CTRL.o b/CTRL.o
new file mode 100644
index 0000000000000000000000000000000000000000..855481c40f0490f2d92da359f84c3d1af3a13d1b
Binary files /dev/null and b/CTRL.o differ
diff --git a/CTRL.vhd b/CTRL.vhd
index 7f7d3fdb4a296c56aa28ae2777ad3da37eb80087..e10b466f5320992ddd1dbd80399fb0211aca6fba 100644
--- a/CTRL.vhd
+++ b/CTRL.vhd
@@ -23,6 +23,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CTRL IS
PORT(
+ Instr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OPCode : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
Func : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
RegDst : OUT STD_LOGIC;
@@ -100,10 +101,6 @@ BEGIN
ALUOp(0) <= '1';
END CASE;
- IF FUNC = "000000" THEN
- RegWrite <= '0';
- END IF;
END PROCESS;
-
END ARC_CTRL;
diff --git a/EXTEND.o b/EXTEND.o
new file mode 100644
index 0000000000000000000000000000000000000000..21b1d1ab3e66b11bfc69d7c5e07e9c95b75e3a2c
Binary files /dev/null and b/EXTEND.o differ
diff --git a/EX_MEM_PIPE.o b/EX_MEM_PIPE.o
new file mode 100644
index 0000000000000000000000000000000000000000..3b20dcd8f62aff83020166977536388927b1a45e
Binary files /dev/null and b/EX_MEM_PIPE.o differ
diff --git a/FORWARD.o b/FORWARD.o
new file mode 100644
index 0000000000000000000000000000000000000000..758920c7ff43150ea1fa4d7ae47f506e902f937e
Binary files /dev/null and b/FORWARD.o differ
diff --git a/FORWARD.vhd b/FORWARD.vhd
index a4d01e78e0ea0b91ba586f987548de1acff87c22..530dc6d5b90b299fb6494ae78984ff67d07a7183 100644
--- a/FORWARD.vhd
+++ b/FORWARD.vhd
@@ -43,19 +43,27 @@ BEGIN
ELSIF CLK'EVENT AND CLK = '1' THEN
IF Rd_M = Reg_rs THEN
forw_a(1) <= '1';
- forw_b(1) <= '0';
- ELSIF Rd_M = Reg_rt THEN
- forw_b(1) <= '1';
+ ELSIF
forw_a(1) <= '0';
END IF;
+ IF Rd_M = Reg_rt THEN
+ forw_b(1) <= '1';
+ ELSIF
+ forw_b(1) <= '0';
+ END IF;
+
IF Rd_W = Reg_rs THEN
forw_a(0) <= '1';
- forw_b(0) <= '0';
- ELSIF Rd_W = Reg_rt THEN
- forw_b(0) <= '1';
+ ELSIF
forw_a(0) <= '0';
END IF;
+
+ IF Rd_W = Reg_rt THEN
+ forw_b(0) <= '1';
+ ELSIF
+ forw_b(0) <= '0';
+ END IF;
--forw_a(1) <= '1' WHEN Rd_M = Reg_rs ELSE '0';
--forw_a(0) <= '1' WHEN Rd_W = Reg_rs ELSE '0';
--forw_b(1) <= '1' WHEN Rd_M = Reg_rt ELSE '0';
diff --git a/ID_EX_PIPE.o b/ID_EX_PIPE.o
new file mode 100644
index 0000000000000000000000000000000000000000..5a6fd7aa87ceddffcafb708e474cb345d9ae6dc1
Binary files /dev/null and b/ID_EX_PIPE.o differ
diff --git a/IF_ID_PIPE.o b/IF_ID_PIPE.o
new file mode 100644
index 0000000000000000000000000000000000000000..5541b6b804cfcd9f25b8b73d998a00a6060a0308
Binary files /dev/null and b/IF_ID_PIPE.o differ
diff --git a/IF_ID_PIPE.vhd b/IF_ID_PIPE.vhd
index 9c0859bd9c8a798194cbee5818861cfa93fad68d..0224760988129de0ccc763b789df54feefddcdfe 100644
--- a/IF_ID_PIPE.vhd
+++ b/IF_ID_PIPE.vhd
@@ -5,9 +5,7 @@ ENTITY IF_ID_PIPE IS
PORT (CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
INSTR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- PC4_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- PC4_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
INSTR_OUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
OPCODE : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
REG_RS : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
@@ -25,12 +23,10 @@ BEGIN
PROCESS (CLK, RESET)
BEGIN
IF RESET = '1' THEN
- PC4_OUT <= X"00400000"; -- MARS
OPCODE <= "000000"; REG_RS <= "00000"; REG_RT <= "00000";
REG_RD <= "00000"; SHAMT <= "00000"; FUNC <= "000000";
IMMED <= "0000000000000000";
ELSIF CLK'EVENT AND CLK = '1' THEN
- PC4_OUT <= PC4_IN;
OPCODE <= INSTR(31 DOWNTO 26);
REG_RS <= INSTR(25 DOWNTO 21);
REG_RT <= INSTR(20 DOWNTO 16);
diff --git a/INST.o b/INST.o
new file mode 100644
index 0000000000000000000000000000000000000000..5a23ebbc5f02bb3fb18445729fd50adcf5300d34
Binary files /dev/null and b/INST.o differ
diff --git a/MAIN_CTTRL.o b/MAIN_CTTRL.o
new file mode 100644
index 0000000000000000000000000000000000000000..9b02e3ba9e745a21b56f5111b6d59b6a8c3dc374
Binary files /dev/null and b/MAIN_CTTRL.o differ
diff --git a/MAIN_CTTRL.vhd b/MAIN_CTTRL.vhd
index 8dabe3542e9da3b78a14b7c4df154433cdaf78c7..8b60228b6e851333688ab53973383d11e3d1c9cd 100644
--- a/MAIN_CTTRL.vhd
+++ b/MAIN_CTTRL.vhd
@@ -63,6 +63,7 @@ ARCHITECTURE ARC_MAIN_PROCESSOR OF MAIN_PROCESSOR IS
COMPONENT CTRL IS
PORT(
+ Instr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OPCode : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
Func : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
RegDst : OUT STD_LOGIC;
@@ -208,9 +209,7 @@ ARCHITECTURE ARC_MAIN_PROCESSOR OF MAIN_PROCESSOR IS
PORT (CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
INSTR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- PC4_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
- PC4_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
INSTR_OUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
OPCODE : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
REG_RS : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
@@ -396,15 +395,14 @@ BEGIN
C_ADD_PC : ADD_PC PORT MAP(PC_OUT, PC_ADD4);
C_INST : INST PORT MAP(PC_OUT, INSTRUCTION);
P_IFID : IF_ID_PIPE PORT MAP(CLK, RESET, INSTRUCTION,
- PC_ADD4,
- PC4_ID, INSTRUCTION_ID, OPCODE_ID, RS_ID,
+ INSTRUCTION_ID, OPCODE_ID, RS_ID,
RT_ID, RD_ID, OPEN,
FUNC_ID, IMMED_ID);
-- nao usa o shamt
---------------------------------------------------------------------------
C_EXTEND_SIGNAL : EXTEND_SIGNAL PORT MAP(IMMED_ID,
EXTENDED_IMMED);
- C_CTRL : CTRL PORT MAP(OPCODE_ID, FUNC_ID, CTRL_SEL_RDRT, CTRL_JUMP,
+ C_CTRL : CTRL PORT MAP(INSTRUCTION_ID, OPCODE_ID, FUNC_ID, CTRL_SEL_RDRT, CTRL_JUMP,
CTRL_BRANCH, CTRL_MEMREAD,
CTRL_MEMTOREG, CTRL_ALUOP,
CTRL_MEMWRITE, CTRL_ALUSRC_EXT_B,
@@ -416,7 +414,7 @@ BEGIN
-- jump addr
C_SL_1 : SL_1 PORT MAP(INSTRUCTION_ID, SH_L_JUMP);
-- jump 00 aligned
- C_CONCAT : CONCAT PORT MAP(SH_L_JUMP, PC4_ID,
+ C_CONCAT : CONCAT PORT MAP(SH_L_JUMP, PC_ADD4,
JUMP_ADDR);
-- branch addr
@@ -427,8 +425,9 @@ BEGIN
C_SUB_BR : SUB_BR PORT MAP(REG_A_OUT, REG_B_OUT, RT_RD_EQ);
C_AND_1 : AND_1 PORT MAP(CTRL_BRANCH, RT_RD_EQ, TAKE_BRANCH);
- C_MX_3 : MX_3 PORT MAP(PC4_ID, BRANCH_ADDR, TAKE_BRANCH,
+ C_MX_3 : MX_3 PORT MAP(PC_ADD4, BRANCH_ADDR, TAKE_BRANCH,
SEL_BR_PC4);
+ -- jump take
C_MX_4 : MX_4 PORT MAP(CTRL_JUMP, JUMP_ADDR, SEL_BR_PC4,
NOVO_PC);
diff --git a/MEM.o b/MEM.o
new file mode 100644
index 0000000000000000000000000000000000000000..249e1f22e286421184d2bdc0cf3d353560656752
Binary files /dev/null and b/MEM.o differ
diff --git a/MEM_WB_PIPE.o b/MEM_WB_PIPE.o
new file mode 100644
index 0000000000000000000000000000000000000000..95a39e52aa9cdd50c1c7ab9121d18117568d44fe
Binary files /dev/null and b/MEM_WB_PIPE.o differ
diff --git a/MX_1.o b/MX_1.o
new file mode 100644
index 0000000000000000000000000000000000000000..25cc1d08caa79c055d16f5fea2edf49f606d0aed
Binary files /dev/null and b/MX_1.o differ
diff --git a/MX_2.o b/MX_2.o
new file mode 100644
index 0000000000000000000000000000000000000000..437a7fbd714085f0b598ef4257cfec749d6ded77
Binary files /dev/null and b/MX_2.o differ
diff --git a/MX_3.o b/MX_3.o
new file mode 100644
index 0000000000000000000000000000000000000000..1596870279aa2d2de05b2b6ad5ebfbfb51edee2f
Binary files /dev/null and b/MX_3.o differ
diff --git a/MX_4.o b/MX_4.o
new file mode 100644
index 0000000000000000000000000000000000000000..08f1a20adac84b64ccf30cf58d8649b081f1b2e2
Binary files /dev/null and b/MX_4.o differ
diff --git a/MX_5.o b/MX_5.o
new file mode 100644
index 0000000000000000000000000000000000000000..7cdc47a7e919365a562cd02728a45b32ec644d22
Binary files /dev/null and b/MX_5.o differ
diff --git a/PC.o b/PC.o
new file mode 100644
index 0000000000000000000000000000000000000000..aa4e889b27523f290306c2e5f39d99db4ec2bb49
Binary files /dev/null and b/PC.o differ
diff --git a/REG.o b/REG.o
new file mode 100644
index 0000000000000000000000000000000000000000..314857cfdc6564282ea62ff7f4a2d51d748483a6
Binary files /dev/null and b/REG.o differ
diff --git a/REG.vhd b/REG.vhd
index 1b1d51bd92b3779209f4b0a59122497ff8589ea1..de10a400c5c14e0e5444bfafb9eeee8619f132c0 100644
--- a/REG.vhd
+++ b/REG.vhd
@@ -54,28 +54,15 @@ BEGIN
REG_1(0) <= (OTHERS => '0');
REG_2(0) <= (OTHERS => '0');
- --t0
- REG_1(8) <= (0 => '1', OTHERS => '0'); --NO TEMOS A FUNO ADDI, ENTO
- REG_2(8) <= (0 => '1', OTHERS => '0'); --TEM QUE SER NA FORA BRUTA
-
--t1
REG_1(9) <= (0 => '1', OTHERS => '0');
REG_2(9) <= (0 => '1', OTHERS => '0');
- REG_1(10) <= (0 => '1', OTHERS => '0');
+ --t2
+ REG_1(10) <= (0 => '1', OTHERS => '0');
REG_2(10) <= (0 => '1', OTHERS => '0');
- REG_1(12) <= (0 => '0', 1 => '1', OTHERS => '0');
- REG_2(12) <= (0 => '0', 1 => '1', OTHERS => '0');
- REG_1(8) <= (0 => '1', OTHERS => '0');
- REG_2(8) <= (0 => '1', OTHERS => '0');
- REG_1(13) <= (0 => '0', 1 => '1', 2 => '1', OTHERS => '0');
- REG_2(13) <= (0 => '0', 1 => '1', 2 => '1', OTHERS => '0');
- -- a0
- REG_1(4) <= X"10010000";
- REG_2(4) <= X"10010000";
ELSIF CLK'EVENT AND CLK = '0' AND RegWrite = '1' THEN
REG_1(TO_INTEGER(UNSIGNED(IN_C))) <= IN_D;
REG_2(TO_INTEGER(UNSIGNED(IN_C))) <= IN_D;
-
END IF;
END PROCESS;
diff --git a/SL_1.o b/SL_1.o
new file mode 100644
index 0000000000000000000000000000000000000000..8b0812f0134945cd39bd8633e6cbdf8199f44682
Binary files /dev/null and b/SL_1.o differ
diff --git a/SL_2.o b/SL_2.o
new file mode 100644
index 0000000000000000000000000000000000000000..3d42deaa000b47ba77d68bf6031f0fc57d416bfe
Binary files /dev/null and b/SL_2.o differ
diff --git a/SUB_BR.o b/SUB_BR.o
new file mode 100644
index 0000000000000000000000000000000000000000..18b1a10cc853c25bf2e3bc161aa76185a678e05e
Binary files /dev/null and b/SUB_BR.o differ
diff --git a/TB_MAIN_PROCESSOR.o b/TB_MAIN_PROCESSOR.o
new file mode 100644
index 0000000000000000000000000000000000000000..096797263220ed6b3a4b0af12c1e9c2fa1fe2582
Binary files /dev/null and b/TB_MAIN_PROCESSOR.o differ
diff --git a/ULA.o b/ULA.o
new file mode 100644
index 0000000000000000000000000000000000000000..75cd629a3c9371739309b9b6494e5f6d0fb74465
Binary files /dev/null and b/ULA.o differ
diff --git a/ULA_CTRL.o b/ULA_CTRL.o
new file mode 100644
index 0000000000000000000000000000000000000000..64ad47af6c8785bfcfe2d653deb2cc55e688fccb
Binary files /dev/null and b/ULA_CTRL.o differ
diff --git a/compile.sh b/compile.sh
new file mode 100755
index 0000000000000000000000000000000000000000..acfeb2f413cdac0e41dc7b7dabd9039437f57e74
--- /dev/null
+++ b/compile.sh
@@ -0,0 +1,11 @@
+#!/bin/bash
+
+if [ $# -eq 3 ]; then
+ ghdl -a --ieee=synopsys -fexplicit *.vhd
+ ghdl -e --ieee=synopsys -fexplicit TB_MAIN_PROCESSOR
+ ./tb_main_processor --stop-time=$1ns --vcd=$2
+ gtkwave $2 $3
+else
+ echo "Uso: $0 <time> <dump>.vcd <config>.sav"
+fi
+
diff --git a/e~tb_main_processor.o b/e~tb_main_processor.o
new file mode 100644
index 0000000000000000000000000000000000000000..5b9d53682cbb17e73b3e8ac464f7a6f073ff286a
Binary files /dev/null and b/e~tb_main_processor.o differ
diff --git a/ondas.vcd b/ondas.vcd
index 5d4b810a25e0377278dd4e28d6cddbc5eac9c165..1b45f815a9c452ead90f5b53bf1505408d65981c 100644
--- a/ondas.vcd
+++ b/ondas.vcd
@@ -1,5 +1,5 @@
$date
- Fri Jun 24 06:26:19 2016
+ Wed Jun 29 15:36:01 2016
$end
$version
GHDL v0
@@ -334,9 +334,9 @@ $enddefinitions $end
1"
0#
1$
-b00000000010000000000000000000000 %
+b00000000010000000000000000000100 %
b00000000010000000000000000000000 &
-b00000000010000000000000000000000 '
+b00000000010000000000000000000100 '
b00000000010000000000000000000100 (
b00000000000000000000000000000000 )
1*
@@ -361,10 +361,10 @@ b00000000000000000000000000000000 <
bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU00 =
b00000000000000000000000000000000 >
b0000UUUUUUUUUUUUUUUUUUUUUUUUUU00 ?
-b00000000010000000000000000000000 @
+b00000000010000000000000000000100 @
1A
0B
-b00000000010000000000000000000000 C
+b00000000010000000000000000000100 C
bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU D
b00000000000000000000000000000000 E
0F
@@ -406,7 +406,7 @@ b00000000000000000000000000000000 i
0j
1k
1l
-b00000000010000000000000000000000 m
+b00000000010000000000000000000100 m
b00000000010000000000000000000000 n
b00000000010000000000000000000000 o
b00000000010000000000000000000100 p
@@ -416,7 +416,7 @@ b00000000000000000000000000000000 r
1t
b00000000000000000000000000000000 u
b00000000010000000000000000000100 v
-b00000000010000000000000000000000 w
+b00000000010000000000000000000100 w
bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU x
b000000 y
b00000 z
@@ -450,14 +450,14 @@ b00000000000000000000000000000000 8"
bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU 9"
bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU00 :"
bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU00 ;"
-b00000000010000000000000000000000 <"
+b00000000010000000000000000000100 <"
b0000UUUUUUUUUUUUUUUUUUUUUUUUUU00 ="
bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU >"
b00000000000000000000000000000000 ?"
b00000000000000000000000000000000 @"
-b00000000010000000000000000000000 A"
+b00000000010000000000000000000100 A"
b00000000000000000000000000000000 B"
-b00000000010000000000000000000000 C"
+b00000000010000000000000000000100 C"
b00000000000000000000000000000000 D"
b00000000000000000000000000000000 E"
1F"
@@ -465,14 +465,14 @@ b00000000000000000000000000000000 G"
0H"
1I"
0J"
-b00000000010000000000000000000000 K"
-b00000000010000000000000000000000 L"
+b00000000010000000000000000000100 K"
+b00000000010000000000000000000100 L"
0M"
-b00000000010000000000000000000000 N"
+b00000000010000000000000000000100 N"
0O"
b0000UUUUUUUUUUUUUUUUUUUUUUUUUU00 P"
-b00000000010000000000000000000000 Q"
-b00000000010000000000000000000000 R"
+b00000000010000000000000000000100 Q"
+b00000000010000000000000000000100 R"
0S"
1T"
0U"
@@ -622,27 +622,28 @@ b00000000000000000000000000000000 g#
#15000000
1!
1#
-b00000000010000000000000000000100 %
-b00000000010000000000000000000100 '
-b00000000010000000000000000000100 @
-b00000000010000000000000000000100 C
+b00000000010000000000000000001000 %
+b00000000010000000000000000000100 &
+b00000000010000000000000000001000 (
+b00000000010000000000000000001000 C
bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU E
1Y
b10 ]
b11 f
1j
-b00000000010000000000000000000100 m
+b00000000010000000000000000001000 m
+b00000000010000000000000000000100 n
+b00000000010000000000000000000100 o
+b00000000010000000000000000001000 p
+b00000000010000000000000000000100 q
1s
-b00000000010000000000000000000100 w
+b00000000010000000000000000001000 v
10"
-b00000000010000000000000000000100 <"
-b00000000010000000000000000000100 A"
-b00000000010000000000000000000100 C"
-b00000000010000000000000000000100 K"
-b00000000010000000000000000000100 L"
-b00000000010000000000000000000100 N"
-b00000000010000000000000000000100 Q"
-b00000000010000000000000000000100 R"
+b00000000010000000000000000001000 <"
+b00000000010000000000000000001000 K"
+b00000000010000000000000000001000 N"
+b00000000010000000000000000001000 Q"
+b00000000010000000000000000001000 R"
1S"
b10 f"
1j"
@@ -671,114 +672,27 @@ bUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU e#
#25000000
1!
1#
-b00000000010000000000000000000100 &
-b00000000010000000000000000001000 (
-1j
-b00000000010000000000000000000100 n
-b00000000010000000000000000000100 o
-b00000000010000000000000000001000 p
-b00000000010000000000000000000100 q
-1s
-b00000000010000000000000000001000 v
-10"
-1S"
-1u"
-1@#
-1P#
-1X#
-#30000000
-0!
-0#
-0j
-0s
-00"
-0S"
-0u"
-0@#
-0P#
-0X#
-#35000000
-1!
-1#
-b00000000010000000000000000001000 %
-b00000000010000000000000000001000 '
-b00000000010000000000000000001000 @
-b00000000010000000000000000001000 C
-1j
-b00000000010000000000000000001000 m
-1s
-b00000000010000000000000000001000 w
-10"
-b00000000010000000000000000001000 <"
-b00000000010000000000000000001000 A"
-b00000000010000000000000000001000 C"
-b00000000010000000000000000001000 K"
-b00000000010000000000000000001000 L"
-b00000000010000000000000000001000 N"
-b00000000010000000000000000001000 Q"
-b00000000010000000000000000001000 R"
-1S"
-1u"
-1@#
-1P#
-1X#
-#40000000
-0!
-0#
-0j
-0s
-00"
-0S"
-0u"
-0@#
-0P#
-0X#
-#45000000
-1!
-1#
+b00000000010000000000000000001100 %
b00000000010000000000000000001000 &
+b00000000010000000000000000001000 '
b00000000010000000000000000001100 (
+b00000000010000000000000000001000 @
+b00000000010000000000000000001100 C
1j
+b00000000010000000000000000001100 m
b00000000010000000000000000001000 n
b00000000010000000000000000001000 o
b00000000010000000000000000001100 p
b00000000010000000000000000001000 q
1s
b00000000010000000000000000001100 v
-10"
-1S"
-1u"
-1@#
-1P#
-1X#
-#50000000
-0!
-0#
-0j
-0s
-00"
-0S"
-0u"
-0@#
-0P#
-0X#
-#55000000
-1!
-1#
-b00000000010000000000000000001100 %
-b00000000010000000000000000001100 '
-b00000000010000000000000000001100 @
-b00000000010000000000000000001100 C
-1j
-b00000000010000000000000000001100 m
-1s
-b00000000010000000000000000001100 w
+b00000000010000000000000000001000 w
10"
b00000000010000000000000000001100 <"
-b00000000010000000000000000001100 A"
-b00000000010000000000000000001100 C"
+b00000000010000000000000000001000 A"
+b00000000010000000000000000001000 C"
b00000000010000000000000000001100 K"
-b00000000010000000000000000001100 L"
+b00000000010000000000000000001000 L"
b00000000010000000000000000001100 N"
b00000000010000000000000000001100 Q"
b00000000010000000000000000001100 R"
@@ -787,7 +701,7 @@ b00000000010000000000000000001100 R"
1@#
1P#
1X#
-#60000000
+#30000000
0!
0#
0j
@@ -798,13 +712,18 @@ b00000000010000000000000000001100 R"
0@#
0P#
0X#
-#65000000
+#35000000
1!
1#
+b00000000010000000000000000010000 %
b00000000010000000000000000001100 &
+b00000000010000000000000000001100 '
b00000000010000000000000000010000 (
b00000001001010100100100000100000 )
+b00000000010000000000000000001100 @
+b00000000010000000000000000010000 C
1j
+b00000000010000000000000000010000 m
b00000000010000000000000000001100 n
b00000000010000000000000000001100 o
b00000000010000000000000000010000 p
@@ -813,13 +732,22 @@ b00000001001010100100100000100000 r
1s
b00000001001010100100100000100000 u
b00000000010000000000000000010000 v
+b00000000010000000000000000001100 w
10"
+b00000000010000000000000000010000 <"
+b00000000010000000000000000001100 A"
+b00000000010000000000000000001100 C"
+b00000000010000000000000000010000 K"
+b00000000010000000000000000001100 L"
+b00000000010000000000000000010000 N"
+b00000000010000000000000000010000 Q"
+b00000000010000000000000000010000 R"
1S"
1u"
1@#
1P#
1X#
-#70000000
+#40000000
0!
0#
0j
@@ -830,11 +758,13 @@ b00000000010000000000000000010000 v
0@#
0P#
0X#
-#75000000
+#45000000
1!
1#
-b00000000010000000000000000010000 %
+b00000000010000000000000000010100 %
+b00000000010000000000000000010000 &
b00000000010000000000000000010000 '
+b00000000010000000000000000010100 (
b100000 5
b01001 6
b01010 7
@@ -845,10 +775,15 @@ b00000000000000000000000000000001 ;
b00000000000000000000000000000001 <
b00000000000000010010000010000000 >
b00000000010000010010000010010000 @
-b00000000010000000000000000010000 C
+b00000000010000000000000000010100 C
1j
-b00000000010000000000000000010000 m
+b00000000010000000000000000010100 m
+b00000000010000000000000000010000 n
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diff --git a/tb_main_processor b/tb_main_processor
new file mode 100755
index 0000000000000000000000000000000000000000..d28dfc4b6264a1c180d2e48f085fd2b494c90b47
Binary files /dev/null and b/tb_main_processor differ
diff --git a/teste.asm b/teste.asm
deleted file mode 100644
index 44b846ee3216a3e73e47f3710107f39ed7af0043..0000000000000000000000000000000000000000
--- a/teste.asm
+++ /dev/null
@@ -1,10 +0,0 @@
-for: beq $t4, $t5, end
- add $t1, $t1, $t4
- sw $t1, 0($a0)
- add $t4, $t4, $t0
- j for
- sw $t0, 0($a0)
-
-end: sw $t1, 0($a0)
- lw $t1, 0($a0)
- sw $t1, 0($a0)
\ No newline at end of file
diff --git a/work-obj93.cf b/work-obj93.cf
index 9bfe0d3b3bdde5e73c9266c6b161435efd5658ea..7963c850b92020078df3bd09f44b6afd3188b19f 100644
--- a/work-obj93.cf
+++ b/work-obj93.cf
@@ -1,82 +1,82 @@
v 3
-file . "FORWARD.vhd" "20160623180240.000" "20160624062613.243":
- entity frwd at 21( 997) + 0 on 3649;
- architecture arc_frwd of frwd at 35( 1458) + 0 on 3650;
-file . "ULA.vhd" "20160616164459.000" "20160624062615.370":
- entity ula at 21( 999) + 0 on 3687;
- architecture arc_ula of ula at 37( 1399) + 0 on 3688;
-file . "ULA_CTRL.vhd" "20160616164459.000" "20160624062615.284":
- entity ula_ctrl at 21( 999) + 0 on 3685;
- architecture arc_ula_ctrl of ula_ctrl at 32( 1244) + 0 on 3686;
-file . "SUB_BR.vhd" "20160623130105.000" "20160624062615.118":
- entity sub_br at 21( 999) + 0 on 3681;
- architecture arc_sub_br of sub_br at 33( 1239) + 0 on 3682;
-file . "SL_1.vhd" "20160616164459.000" "20160624062614.976":
- entity sl_1 at 21( 999) + 0 on 3677;
- architecture arc_sl_1 of sl_1 at 32( 1205) + 0 on 3678;
-file . "MX_4.vhd" "20160616164459.000" "20160624062614.557":
- entity mx_4 at 21( 999) + 0 on 3669;
- architecture arc_mx_4 of mx_4 at 33( 1250) + 0 on 3670;
-file . "MX_2.vhd" "20160616164459.000" "20160624062614.412":
- entity mx_2 at 21( 999) + 0 on 3665;
- architecture arc_mx_2 of mx_2 at 33( 1267) + 0 on 3666;
-file . "MEM_WB_PIPE.vhd" "20160623111712.000" "20160624062614.249":
- entity mem_wb_pipe at 1( 0) + 0 on 3661;
- architecture arc_mem_wb_pipe of mem_wb_pipe at 21( 622) + 0 on 3662;
-file . "IF_ID_PIPE.vhd" "20160623190335.000" "20160624062613.475":
- entity if_id_pipe at 1( 0) + 0 on 3653;
- architecture arc_if_id_pipe of if_id_pipe at 22( 699) + 0 on 3654;
-file . "EX_MEM_PIPE.vhd" "20160624020713.000" "20160624062613.066":
- entity ex_mem_pipe at 1( 0) + 0 on 3645;
- architecture arc_ex_mem_pipe of ex_mem_pipe at 25( 763) + 0 on 3646;
-file . "CONCAT.vhd" "20160616164459.000" "20160624062612.843":
- entity concat at 21( 1000) + 0 on 3641;
- architecture arc_concat of concat at 32( 1245) + 0 on 3642;
-file . "ADD.vhd" "20160616164459.000" "20160624062612.710":
- entity add at 21( 999) + 0 on 3637;
- architecture arc_add of add at 33( 1249) + 0 on 3638;
-file . "PC.vhd" "20160622231950.000" "20160624062614.699":
- entity pc at 21( 1001) + 0 on 3673;
- architecture arc_pc of pc at 34( 1283) + 0 on 3674;
-file . "TB_MAIN_PROCESSOR.vhd" "20160616164459.000" "20160624062615.216":
- entity tb_main_processor at 28( 951) + 0 on 3683;
- architecture behavior of tb_main_processor at 38( 1200) + 0 on 3684;
-file . "MAIN_CTTRL.vhd" "20160624092525.000" "20160624062613.827":
- entity main_processor at 21( 999) + 0 on 3657;
- architecture arc_main_processor of main_processor at 32( 1183) + 0 on 3658;
-file . "ADD_PC.vhd" "20160616164459.000" "20160624062612.626":
- entity add_pc at 21( 999) + 0 on 3635;
- architecture arc_add_pc of add_pc at 32( 1202) + 0 on 3636;
-file . "AND.vhd" "20160616164459.000" "20160624062612.780":
- entity and_1 at 21( 1000) + 0 on 3639;
- architecture arc_and_1 of and_1 at 32( 1179) + 0 on 3640;
-file . "CTRL.vhd" "20160624092610.000" "20160624062612.914":
- entity ctrl at 21( 999) + 0 on 3643;
- architecture arc_ctrl of ctrl at 40( 1482) + 0 on 3644;
-file . "EXTEND.vhd" "20160616164459.000" "20160624062613.168":
- entity extend_signal at 23( 1082) + 0 on 3647;
- architecture arc_extend_signal of extend_signal at 34( 1306) + 0 on 3648;
-file . "ID_EX_PIPE.vhd" "20160623192429.000" "20160624062613.338":
- entity id_ex_pipe at 1( 0) + 0 on 3651;
- architecture arc_id_ex_pipe of id_ex_pipe at 39( 1452) + 0 on 3652;
-file . "INST.vhd" "20160623173836.000" "20160624062613.596":
- entity inst at 21( 999) + 0 on 3655;
- architecture arc_inst of inst at 33( 1199) + 0 on 3656;
-file . "MEM.vhd" "20160623172637.000" "20160624062614.133":
- entity mem at 21( 999) + 0 on 3659;
- architecture arc_mem of mem at 37( 1363) + 0 on 3660;
-file . "MX_1.vhd" "20160616164459.000" "20160624062614.338":
- entity mx_1 at 21( 999) + 0 on 3663;
- architecture arc_mx_1 of mx_1 at 33( 1261) + 0 on 3664;
-file . "MX_3.vhd" "20160616164459.000" "20160624062614.482":
- entity mx_3 at 21( 999) + 0 on 3667;
- architecture arc_mx_3 of mx_3 at 33( 1250) + 0 on 3668;
-file . "MX_5.vhd" "20160616164459.000" "20160624062614.628":
- entity mx_5 at 21( 999) + 0 on 3671;
- architecture arc_mx_5 of mx_5 at 32( 1252) + 0 on 3672;
-file . "REG.vhd" "20160623173953.000" "20160624062614.772":
- entity reg at 21( 999) + 0 on 3675;
- architecture arc_reg of reg at 39( 1464) + 0 on 3676;
-file . "SL_2.vhd" "20160616164459.000" "20160624062615.047":
- entity sl_2 at 21( 999) + 0 on 3679;
- architecture arc_sl_2 of sl_2 at 32( 1203) + 0 on 3680;
+file . "SL_2.vhd" "20160616164459.000" "20160629144130.637":
+ entity sl_2 at 21( 999) + 0 on 4165;
+ architecture arc_sl_2 of sl_2 at 32( 1203) + 0 on 4166;
+file . "REG.vhd" "20160629170547.000" "20160629144130.530":
+ entity reg at 21( 999) + 0 on 4161;
+ architecture arc_reg of reg at 39( 1464) + 0 on 4162;
+file . "MX_5.vhd" "20160616164459.000" "20160629144130.439":
+ entity mx_5 at 21( 999) + 0 on 4157;
+ architecture arc_mx_5 of mx_5 at 32( 1252) + 0 on 4158;
+file . "MX_3.vhd" "20160616164459.000" "20160629144130.369":
+ entity mx_3 at 21( 999) + 0 on 4153;
+ architecture arc_mx_3 of mx_3 at 33( 1250) + 0 on 4154;
+file . "MX_1.vhd" "20160616164459.000" "20160629144130.288":
+ entity mx_1 at 21( 999) + 0 on 4149;
+ architecture arc_mx_1 of mx_1 at 33( 1261) + 0 on 4150;
+file . "MEM.vhd" "20160623172637.000" "20160629144130.169":
+ entity mem at 21( 999) + 0 on 4145;
+ architecture arc_mem of mem at 37( 1363) + 0 on 4146;
+file . "INST.vhd" "20160623173836.000" "20160629144129.965":
+ entity inst at 21( 999) + 0 on 4141;
+ architecture arc_inst of inst at 33( 1199) + 0 on 4142;
+file . "ID_EX_PIPE.vhd" "20160623192429.000" "20160629144129.856":
+ entity id_ex_pipe at 1( 0) + 0 on 4137;
+ architecture arc_id_ex_pipe of id_ex_pipe at 39( 1452) + 0 on 4138;
+file . "EXTEND.vhd" "20160616164459.000" "20160629153601.659":
+ entity extend_signal at 23( 1082) + 0 on 4265;
+ architecture arc_extend_signal of extend_signal at 34( 1306) + 0 on 4266;
+file . "CTRL.vhd" "20160629183559.000" "20160629153601.561":
+ entity ctrl at 21( 999) + 0 on 4261;
+ architecture arc_ctrl of ctrl at 41( 1549) + 0 on 4262;
+file . "AND.vhd" "20160616164459.000" "20160629153601.492":
+ entity and_1 at 21( 1000) + 0 on 4257;
+ architecture arc_and_1 of and_1 at 32( 1179) + 0 on 4258;
+file . "ADD_PC.vhd" "20160616164459.000" "20160629153601.421":
+ entity add_pc at 21( 999) + 0 on 4253;
+ architecture arc_add_pc of add_pc at 32( 1202) + 0 on 4254;
+file . "MAIN_CTTRL.vhd" "20160629174119.000" "20160629144130.052":
+ entity main_processor at 21( 999) + 0 on 4143;
+ architecture arc_main_processor of main_processor at 32( 1183) + 0 on 4144;
+file . "TB_MAIN_PROCESSOR.vhd" "20160629172443.000" "20160629144130.728":
+ entity tb_main_processor at 28( 951) + 0 on 4169;
+ architecture behavior of tb_main_processor at 38( 1200) + 0 on 4170;
+file . "PC.vhd" "20160622231950.000" "20160629144130.491":
+ entity pc at 21( 1001) + 0 on 4159;
+ architecture arc_pc of pc at 34( 1283) + 0 on 4160;
+file . "ADD.vhd" "20160616164459.000" "20160629153601.458":
+ entity add at 21( 999) + 0 on 4255;
+ architecture arc_add of add at 33( 1249) + 0 on 4256;
+file . "CONCAT.vhd" "20160616164459.000" "20160629153601.523":
+ entity concat at 21( 1000) + 0 on 4259;
+ architecture arc_concat of concat at 32( 1245) + 0 on 4260;
+file . "EX_MEM_PIPE.vhd" "20160624020713.000" "20160629153601.613":
+ entity ex_mem_pipe at 1( 0) + 0 on 4263;
+ architecture arc_ex_mem_pipe of ex_mem_pipe at 25( 763) + 0 on 4264;
+file . "IF_ID_PIPE.vhd" "20160629172006.000" "20160629144129.913":
+ entity if_id_pipe at 1( 0) + 0 on 4139;
+ architecture arc_if_id_pipe of if_id_pipe at 22( 699) + 0 on 4140;
+file . "MEM_WB_PIPE.vhd" "20160623111712.000" "20160629144130.227":
+ entity mem_wb_pipe at 1( 0) + 0 on 4147;
+ architecture arc_mem_wb_pipe of mem_wb_pipe at 21( 622) + 0 on 4148;
+file . "MX_2.vhd" "20160616164459.000" "20160629144130.324":
+ entity mx_2 at 21( 999) + 0 on 4151;
+ architecture arc_mx_2 of mx_2 at 33( 1267) + 0 on 4152;
+file . "MX_4.vhd" "20160616164459.000" "20160629144130.404":
+ entity mx_4 at 21( 999) + 0 on 4155;
+ architecture arc_mx_4 of mx_4 at 33( 1250) + 0 on 4156;
+file . "SL_1.vhd" "20160616164459.000" "20160629144130.594":
+ entity sl_1 at 21( 999) + 0 on 4163;
+ architecture arc_sl_1 of sl_1 at 32( 1205) + 0 on 4164;
+file . "SUB_BR.vhd" "20160623130105.000" "20160629144130.672":
+ entity sub_br at 21( 999) + 0 on 4167;
+ architecture arc_sub_br of sub_br at 33( 1239) + 0 on 4168;
+file . "ULA_CTRL.vhd" "20160616164459.000" "20160629144130.774":
+ entity ula_ctrl at 21( 999) + 0 on 4171;
+ architecture arc_ula_ctrl of ula_ctrl at 32( 1244) + 0 on 4172;
+file . "ULA.vhd" "20160616164459.000" "20160629144130.823":
+ entity ula at 21( 999) + 0 on 4173;
+ architecture arc_ula of ula at 37( 1399) + 0 on 4174;
+file . "FORWARD.vhd" "20160623180240.000" "20160629144129.814":
+ entity frwd at 21( 997) + 0 on 4135;
+ architecture arc_frwd of frwd at 35( 1458) + 0 on 4136;