diff --git a/cMIPS/bin/edMemory.sh b/cMIPS/bin/edMemory.sh
index ed3c4db73f2100ac5a93803407c51affaa211299..243de4036d7ef25f8e706377067226f511878bde 100755
--- a/cMIPS/bin/edMemory.sh
+++ b/cMIPS/bin/edMemory.sh
@@ -83,6 +83,15 @@ then
fi
done
+ # set up address for base of Page Table
+ VAR=x_DATA_MEM_SZ
+ NEW=$(egrep -h ${VAR} "${dfn}" | sed -n -e '/reg32/s/.*x"\(.*\)".*/\1/p')
+ OLD=$(egrep -h ${VAR} "${lnk}" | sed -n -e 's/.* = 0x\(.*\); .*/\1/p')
+ # echo -n -e "$NEW $OLD\n"
+ if [ -n "$OLD" ] ; then
+ sed -i -e '/'$VAR'/s/'$OLD'/'$NEW'/' "${lnk}"
+ fi
+
cp "${hdr}" "${hdr}"~
for VAR in $VARIABLES ; do
NEW=$(egrep -h ${VAR} "${dfn}"|sed -n -e '/reg32/s/.*x"\(.*\)".*/\1/p')
diff --git a/cMIPS/include/cMIPS.ld b/cMIPS/include/cMIPS.ld
index 8c65855e98e25ed563b1724b176201df9397f35b..0163f3d88dfd41689bcdf400b7c88f73186801f6 100644
--- a/cMIPS/include/cMIPS.ld
+++ b/cMIPS/include/cMIPS.ld
@@ -5,8 +5,10 @@ MEMORY
{
rom (rx) : ORIGIN = 0x00000000, /* x_INST_BASE_ADDR */
LENGTH = 0x00004000, /* x_INST_MEM_SZ */
- ram (!rx) : ORIGIN = 0x00040000, /* x_DATA_BASE_ADDR */
- LENGTH = 0x00040000 /* x_DATA_MEM_SZ */
+ ram (!rx) : ORIGIN = 0x00010000, /* x_DATA_BASE_ADDR */
+ LENGTH = 0x00020000, /* x_DATA_MEM_SZ */
+ io (!rx) : ORIGIN = 0x0f000000, /* not used, do not remove */
+ LENGTH = 0x00020000 /* edMemory.sh needs thess lines */
}
SECTIONS
@@ -15,25 +17,29 @@ SECTIONS
{
*(.text .text.*)
_etext = . ; /* end of text constant (from Xinu) */
-
} > rom
- .rodata : { *(.rodata .rodata.*) } > ram
- .rodata1 : { *(.rodata1) } > ram
- .data ALIGN(0x10) :
+ .data :
{
+ _bdata = . ; /* begin of data constant */
*(.data .data.*)
_edata = . ; /* end of data constant (from Xinu) */
} > ram
.data1 : { *(.data1) } > ram
- .sdata : { *(.sdata .sdata.*) } > ram
+ .rodata : { *(.rodata .rodata.*) } > ram
+ .rodata1 : { *(.rodata1) } > ram
.lit8 : { *(.lit8) } > ram
.lit4 : { *(.lit4) } > ram
+ .sdata : { *(.sdata .sdata.*) } > ram
.sbss : { *(.sbss .sbss.*) *(.scommon .scommon.*) } > ram
- .bss ALIGN(0x10) :
+ .bss :
{
*(.bss .bss.*) *(COMMON)
_end = . ; /* end of image constant (from Xinu) */
-
} > ram
+
+ end_RAM = 0x00020000; /* x_DATA_MEM_SZ */
+ half_RAM = (end_RAM / 2);
+ base_TP = ( _bdata + half_RAM );
+ .TP base_TP : { *(.TP) } > ram
}
diff --git a/cMIPS/include/start.s b/cMIPS/include/start.s
index 253956c3b703903706b660a15442233bc3392959..6ef659a47690194de8269db2493219542e9a279e 100644
--- a/cMIPS/include/start.s
+++ b/cMIPS/include/start.s
@@ -340,3 +340,16 @@ _excp_BFC0:
## main(), normal code starts below -- do not edit next line
.org x_ENTRY_POINT,0
+
+ ##
+ ##===============================================================
+ ## reserve first two pages for the Page Table
+ ##
+
+ .section .TP,"aw",@progbits
+_TP: .skip (2*4096), 0
+_endTP:
+
+
+
+
diff --git a/cMIPS/tests/badVAddrMM.expected b/cMIPS/tests/badVAddrMM.expected
index 5ef844debad96f190e6cfd500215998f0637d3c2..8e26563645b1376fc768472b478e8a7aa3960f09 100644
--- a/cMIPS/tests/badVAddrMM.expected
+++ b/cMIPS/tests/badVAddrMM.expected
@@ -1,20 +1,20 @@
00000000
[
08800014
-00000818
-0f000001
+0000081c
+00000001
]
00000001
[
08800014
-00000818
-0f000002
+0000081c
+00000002
]
00000002
[
08800014
-00000818
-0f000003
+0000081c
+00000003
]
00000003
@@ -22,20 +22,20 @@
00000003
[
08800010
-00000858
-00040001
+00000860
+00000001
]
00000002
[
08800010
-00000858
-00040002
+00000860
+00000002
]
00000001
[
08800010
-00000858
-00040003
+00000860
+00000003
]
00000000
@@ -43,15 +43,15 @@
00000000
[
08800014
-000008a0
-0f000001
+000008ac
+00000001
]
00000001
00000002
[
08800014
-000008b8
-0f000003
+000008c4
+00000003
]
00000003
@@ -59,14 +59,14 @@
00000003
[
08800010
-000008f0
-00040001
+00000900
+00000001
]
00000002
00000002
[
08800010
-00000910
-00040003
+00000920
+00000003
]
00000001
diff --git a/cMIPS/tests/badVAddrMM.s b/cMIPS/tests/badVAddrMM.s
index 0323e7240f05fbe7ec4914803fbcdc363598d58a..c27a2074766e8c502f45755637042177f2f688f2 100644
--- a/cMIPS/tests/badVAddrMM.s
+++ b/cMIPS/tests/badVAddrMM.s
@@ -68,7 +68,8 @@ excp_180:
sw $k0, 0($14)
mfc0 $k0, cop0_BadVAddr # print BadVAddr
- sw $k0, 0($14)
+ xor $k0, $k0, $30 # mask off top address bits,
+ sw $k0, 0($14) # show only bits that differ
addiu $k1, $zero, -4 # -4 = 0xffff.fffc
and $15, $15, $k1 # fix the invalid address
@@ -116,6 +117,7 @@ _excp_BFC0:
##
main: la $14, x_IO_BASE_ADDR # used by exception handler
+ move $30, $14 # keep safe copy of base address for handlr
la $15, x_IO_BASE_ADDR # used to generate misaligned references
li $7, 3 # do 4 rounds for each type of exception
li $3, 0 # exception handler decreaments $7
@@ -141,6 +143,7 @@ next: li $29, '\n' # to separate output
##
la $15, x_DATA_BASE_ADDR
+ move $30, $15 # keep safe copy of base address for handlr
la $18, x_IO_BASE_ADDR
li $7, 3 # do 3 rounds
li $3, 0
@@ -169,6 +172,7 @@ after: li $29, '\n' # to separate output
##
la $14, x_IO_BASE_ADDR # used by exception handler
+ move $30, $14 # keep safe copy of base address for handlr
la $15, x_IO_BASE_ADDR
li $7, 3
li $3, 0
@@ -187,10 +191,11 @@ here2: sh $3, 0($15) # causes no exception: addr & 00
-next2: li $29, '\n' # to separate output
+next2: li $29, '\n' # to separate output
sw $29, x_IO_ADDR_RANGE($14)
sw $29, x_IO_ADDR_RANGE($14)
la $15, x_DATA_BASE_ADDR
+ move $30, $15 # keep safe copy of base address for handlr
la $18, x_IO_BASE_ADDR
li $7, 3
la $3, 0
diff --git a/cMIPS/tests/jaljr.s b/cMIPS/tests/jaljr.s
index fc34b9f3a8fc56db9ff441bc06db33c8f4998566..c0da3b098cc92056daf42b6c77c3161d1aac73ac 100644
--- a/cMIPS/tests/jaljr.s
+++ b/cMIPS/tests/jaljr.s
@@ -5,34 +5,38 @@
.globl _start
.ent _start
_start: la $16, x_IO_BASE_ADDR
- la $15,(x_DATA_BASE_ADDR+0x10)
+ la $15, (x_DATA_BASE_ADDR+0x10)
la $5, snd
- li $3,1
- li $4,5
- move $8,$zero
- move $31,$zero
- addi $29,$0,100
-snd: sw $31, 0($16) # $31 <- 0,snd+4
- add $8,$8,$3 # $8 <- 1, 7,13,19,25,31,
- add $8,$8,$4 # $8 <- 6,12,18,24,30,36,
- add $9,$8,$8 # $9 <- 12,24,36,48,60,72,
- sw $9, 4($16)
- slt $28,$9,$29
- beq $28,$0,.L1
+ li $3, 1
+ li $4, 5
+
+ move $8, $zero
+ move $31, $zero
+ addi $29, $0, 100
+
+snd: sw $31, 0($16) # $31 <- 0,snd+4
+ add $8, $8, $3 # $8 <- 1, 7,13,19,25,31,
+ add $8, $8, $4 # $8 <- 6,12,18,24,30,36,
+ add $9, $8, $8 # $9 <- 12,24,36,48,60,72,
+ sw $9, 0($16)
+ slt $28, $9, $29
+ beq $28, $0, L1
nop
- jr $5
+ jr $5
nop
-.L1: move $8,$0
-trd: sw $31, 0($16) # $31 <- 0,snd+4
- add $8,$8,$3 # $8 <- 1, 7,13,19,25,31,
- add $8,$8,$4 # $8 <- 6,12,18,24,30,36,
- add $9,$8,$8 # $9 <- 12,24,36,48,60,72,
- sw $9, 4($16)
- slt $28,$9,$29
- beq $28,$0,end
+
+L1: move $8,$0
+trd: sw $31, 0($16) # $31 <- 0,snd+4
+ add $8, $8, $3 # $8 <- 1, 7,13,19,25,31,
+ add $8, $8, $4 # $8 <- 6,12,18,24,30,36,
+ add $9, $8, $8 # $9 <- 12,24,36,48,60,72,
+ sw $9, 0($16)
+ slt $28, $9, $29
+ beq $28, $0, end
nop
jal trd
nop
+
end: nop
nop
wait
diff --git a/cMIPS/tests/lwFWDsw2.expected b/cMIPS/tests/lwFWDsw2.expected
index 08575e2ce64111a799543dd5eb22762949663bff..3fdc224e83062dd9c07f5494ce3848a61de29d3a 100644
--- a/cMIPS/tests/lwFWDsw2.expected
+++ b/cMIPS/tests/lwFWDsw2.expected
@@ -1,4 +1,4 @@
-00040010
+00000010
fffffff6
00000014
fffffff7
diff --git a/cMIPS/tests/lwFWDsw2.s b/cMIPS/tests/lwFWDsw2.s
index f71dc69d189e6d5719b5e8067d738f5a95965578..f458ab5125eb33c4fc358dfd3a52fc23e5f2bf26 100644
--- a/cMIPS/tests/lwFWDsw2.s
+++ b/cMIPS/tests/lwFWDsw2.s
@@ -2,16 +2,19 @@
.text
.align 2
.set noreorder
+
.globl _start
.ent _start
_start: nop
la $17, x_DATA_BASE_ADDR # base address of RAM
+ move $30, $17 # keep safe copy of base address
addiu $15, $17, 4*4 # $15 <- &RAM[4]
la $16, x_IO_BASE_ADDR # address to print out results
addi $3, $0, -10 # value to print = -10
addi $5, $0, 4 # scan from RAM[4]..RAM[24]
addi $9, $0, 10 # stop when done 20 loops = +10
sw $15, 0($17) # save pointer to RAM[0]
+ xor $15, $15, $30 # mask off address, keep least sign bits
sw $15, 0($16) # and print it out
nop
@@ -24,15 +27,18 @@ snd: lw $15, 0($17) # reload pointer from RAM
sw $15, 0($17) # store pointer to RAM[0]
nop
nop
- lw $15, 0($17) # reload pointer
+ lw $15, 0($17) # reload pointer, forwarding $15
sw $15, 0($15) # store pointer to RAM[i]
nop
lw $15, 0($15) # reload pointer from RAM[i]
- andi $15, $15, 0x00ff # mask off address, keep least sign bits
- sw $15, 0($16) # and print it out, forwarding $15
+ xor $15, $15, $30 # mask off address, keep least sign bits
+ sw $15, 0($16) # and print it out
nop
slt $8,$3,$9 # done?
bne $8,$0,snd
+ nop
+ nop
+ nop
nop
wait
nop
diff --git a/cMIPS/tests/mmu_refill.s b/cMIPS/tests/mmu_refill.s
index bdf19cea87901def55d3951653dabc8e2daf845c..55c5bf88dfd1e684839e8cfa33ca5b15fb8928d6 100644
--- a/cMIPS/tests/mmu_refill.s
+++ b/cMIPS/tests/mmu_refill.s
@@ -1,6 +1,8 @@
##
## Cause a TLB miss on a fetch, then copy a mapping from page table
##
+ ## This test breaks if the base of RAM is below 0x0001.0000 since
+ ## cop0_Context maps only addresses ABOVE 0x0001.xxxx
##
## EntryHi : EntryLo0 : EntryLo1
## VPN2 g ASID : PPN0 ccc0 d0 v0 g0 : PPN1 ccc1 d1 v1 g1
diff --git a/cMIPS/tests/mmu_tlbwi.expected b/cMIPS/tests/mmu_tlbwi.expected
index 1a4d0eb4c0bf838af0b31ee9df606919f24a684b..582e4e8e1ff93a62b6e86cd4e731b9e902ce641c 100644
--- a/cMIPS/tests/mmu_tlbwi.expected
+++ b/cMIPS/tests/mmu_tlbwi.expected
@@ -28,10 +28,6 @@
0000091b
00000c1b
6
-00044000
-00001107
-00001147
+ok6
7
-00046000
-00001187
-000011c7
+ok7
diff --git a/cMIPS/tests/mmu_tlbwi.s b/cMIPS/tests/mmu_tlbwi.s
index 44d656f309d35a4ec775538cc25976fa46a82019..e59e8043c4a778b7259c273577c07e622746325a 100644
--- a/cMIPS/tests/mmu_tlbwi.s
+++ b/cMIPS/tests/mmu_tlbwi.s
@@ -224,21 +224,74 @@ read3: tlbr # read TLB at index = 3
sw $24, 0($31)
+ ## to make the test position-independent, compute the contents
+ ## and then compare these to those read from the TLB
+ ## test will break if MMU is initialized with different page #s
+ .set PAGE_SZ, 4096
+ .set TAG_MASK, 0xfffff000 # 4Kbyte pages
+ .set TAG_G, 0x00000000 # mark pages as global
+
+# .set MMU_ini_tag_RAM6, ((x_RAM_PPN_6 & TAG_MASK) | TAG_G)
+
+# .set x_RAM_PPN_6, (x_DATA_BASE_ADDR + 6*PAGE_SZ)
+# .set MMU_ini_dat_RAM6, (((x_RAM_PPN_6 >>12) <<6) | 0b000111) # d,v,g=1
+
+# .set x_RAM_PPN_7, (x_DATA_BASE_ADDR + 7*PAGE_SZ)
+# .set MMU_ini_dat_RAM7, (((x_RAM_PPN_7 >>12) <<6) | 0b000111) # d,v,g=1
+
+
# read from MMU(6)
addi $1, $1, 1
- addi $30, $1, '0'
+ addi $30, $1, '0'
sw $30, x_IO_ADDR_RANGE($31)
li $30, '\n'
sw $30, x_IO_ADDR_RANGE($31)
+ # compute mappings for MMU(6)
+ .set x_RAM_PPN_4, (x_DATA_BASE_ADDR + 4*PAGE_SZ)
+ .set MMU_ini_dat_RAM4, (((x_RAM_PPN_4 >>12) <<6) | 0b000111) # d,v,g=1
+
+ .set x_RAM_PPN_5, (x_DATA_BASE_ADDR + 5*PAGE_SZ)
+ .set MMU_ini_dat_RAM5, (((x_RAM_PPN_5 >>12) <<6) | 0b000111) # d,v,g=1
+
+ .set MMU_ini_tag_RAM4, ((x_RAM_PPN_4 & TAG_MASK) | TAG_G)
+
+ la $13, MMU_ini_tag_RAM4
+ # sw $13, 0($31)
+ la $14, MMU_ini_dat_RAM4
+ # sw $14, 0($31)
+ la $15, MMU_ini_dat_RAM5
+ # sw $15, 0($31)
+
+
mtc0 $1, cop0_Index
tlbr # index = 6
mfc0 $23, cop0_EntryHi
- sw $23, 0($31)
+ # sw $23, 0($31)
+
+ bne $23, $13, error
+ nop
+
mfc0 $24, cop0_EntryLo0
- sw $24, 0($31)
- mfc0 $24, cop0_EntryLo1
- sw $24, 0($31)
+ # sw $24, 0($31)
+
+ bne $24, $14, error
+ nop
+
+ mfc0 $25, cop0_EntryLo1
+ # sw $25, 0($31)
+
+ bne $25, $15, error
+ nop
+
+ok6: li $30, 'o'
+ sw $30, x_IO_ADDR_RANGE($31)
+ li $30, 'k'
+ sw $30, x_IO_ADDR_RANGE($31)
+ li $30, '6'
+ sw $30, x_IO_ADDR_RANGE($31)
+ li $30, '\n'
+ sw $30, x_IO_ADDR_RANGE($31)
# read from MMU(7)
@@ -248,16 +301,66 @@ read3: tlbr # read TLB at index = 3
li $30, '\n'
sw $30, x_IO_ADDR_RANGE($31)
+ # compute mappings for MMU(7)
+
+ .set x_RAM_PPN_6, (x_DATA_BASE_ADDR + 6*PAGE_SZ)
+ .set MMU_ini_dat_RAM6, (((x_RAM_PPN_6 >>12) <<6) | 0b000111) # d,v,g=1
+
+ .set x_RAM_PPN_7, (x_DATA_BASE_ADDR + 7*PAGE_SZ)
+ .set MMU_ini_dat_RAM7, (((x_RAM_PPN_7 >>12) <<6) | 0b000111) # d,v,g=1
+
+ .set MMU_ini_tag_RAM6, ((x_RAM_PPN_6 & TAG_MASK) | TAG_G)
+
+ la $13, MMU_ini_tag_RAM6
+ # sw $13, 0($31)
+ la $14, MMU_ini_dat_RAM6
+ # sw $14, 0($31)
+ la $15, MMU_ini_dat_RAM7
+ # sw $15, 0($31)
+
mtc0 $1, cop0_Index
tlbr # index = 7
mfc0 $23, cop0_EntryHi
- sw $23, 0($31)
+ # sw $23, 0($31)
+
+ bne $23, $13, error
+ nop
+
mfc0 $24, cop0_EntryLo0
- sw $24, 0($31)
- mfc0 $24, cop0_EntryLo1
- sw $24, 0($31)
+ # sw $24, 0($31)
+
+ bne $24, $14, error
+ nop
+ mfc0 $25, cop0_EntryLo1
+ # sw $25, 0($31)
+ bne $25, $15, error
+ nop
+
+ok7: li $30, 'o'
+ sw $30, x_IO_ADDR_RANGE($31)
+ li $30, 'k'
+ sw $30, x_IO_ADDR_RANGE($31)
+ li $30, '7'
+ sw $30, x_IO_ADDR_RANGE($31)
+ li $30, '\n'
+ sw $30, x_IO_ADDR_RANGE($31)
+ j _exit
+
+
+error: li $30, 'e'
+ sw $30, x_IO_ADDR_RANGE($31)
+ li $30, 'r'
+ sw $30, x_IO_ADDR_RANGE($31)
+ sw $30, x_IO_ADDR_RANGE($31)
+ li $30, 'o'
+ sw $30, x_IO_ADDR_RANGE($31)
+ li $30, 'r'
+ sw $30, x_IO_ADDR_RANGE($31)
+ li $30, '\n'
+ sw $30, x_IO_ADDR_RANGE($31)
+
nop
nop
_exit: nop
diff --git a/cMIPS/vhdl/core.vhd b/cMIPS/vhdl/core.vhd
index 943c1694b6334e4128fcc1217c646b39777b39ae..18fe79a8f170e2b454b94027cf665bec81fb53da 100644
--- a/cMIPS/vhdl/core.vhd
+++ b/cMIPS/vhdl/core.vhd
@@ -565,7 +565,7 @@ architecture rtl of core is
constant func_table : t_function_mem := (
-- i wreg selB oper muxC trap mov syn PCsel excp
- (iSLL, '0','0',opSLL, "001",'1','0','0',"00","00"), --sll=0, EHB
+ (iSLL, '0','0',opSLL, "001",'0','0','0',"00","00"), --sll=0, EHB
(NIL, '1','0',opNOP, "001",'0','0','0',"00","00"), --1, FlPoint
(iSRL, '0','0',opSRL, "001",'0','0','0',"00","00"), --srl=2
(iSRA, '0','0',opSRA, "001",'0','0','0',"00","00"), --sra=3