diff --git a/cMIPS/include/structUart.h b/cMIPS/include/structUart.h
index 1572b41bb2163200db5108e248deb13e9574967e..c2fa9080934f9ba3d81e9ecb6f3ef0032f247d94 100644
--- a/cMIPS/include/structUart.h
+++ b/cMIPS/include/structUart.h
@@ -2,18 +2,18 @@
#define __STRUCTUART__
typedef struct UARTdriver {
-int rx_hd ; // reception queue head index
-int rx_tl ; // reception queue tail index
-char rx_q [16]; // reception queue
-int tx_hd ; // transmission queue head index
-int tx_tl ; // transmission queue tail index
-char tx_q [16]; // transmission queue
-int nrx ; // number of characters in rx_queue
-int ntx ; // number of spaces in tx_queue
+ int rx_hd ; // reception queue head index
+ int rx_tl ; // reception queue tail index
+ char rx_q [16]; // reception queue
+ int tx_hd ; // transmission queue head index
+ int tx_tl ; // transmission queue tail index
+ char tx_q [16]; // transmission queue
+ int nrx ; // number of characters in rx_queue
+ int ntx ; // number of spaces in tx_queue
} UARTdriver;
typedef struct control { // control register fields (uses only ls byte)
- int ign : 24, // ignore uppermost bits
+ unsigned int ign : 24, // ignore uppermost bits
rts : 1, // Request to Send output (bit 7)
ign2 : 2, // bits 6,5 ignored
intTX : 1, // interrupt on TX buffer empty (bit 4)
@@ -22,35 +22,29 @@ typedef struct control { // control register fields (uses only ls byte)
} Tcontrol;
typedef struct status { // status register fields (uses only ls byte)
- int ign : 24, // ignore uppermost bits
- ign7 : 1, // ignored (bit 7)
- txEmpty : 1, // TX register is empty (bit 6)
- rxFull : 1, // octet available from RX register (bit 5)
- int_TX_empt: 1, // interrupt pending on TX empty (bit 4)
- int_RX_full: 1, // interrupt pending on RX full (bit 3)
- ign2 : 1, // ignored (bit 2)
- framing : 1, // framing error (bit 1)
- overun : 1; // overun error (bit 0)
-} Tstatus;
+ unsigned int ign : 24, // ignore uppermost bits
+ ign7 : 1, // ignored (bit 7)
+ txEmpty : 1, // TX register is empty (bit 6)
+ rxFull : 1, // octet available from RX register (bit 5)
+ int_TX_empt: 1, // interrupt pending on TX empty (bit 4)
+ int_RX_full: 1, // interrupt pending on RX full (bit 3)
+ ign2 : 1, // ignored (bit 2)
+ framing : 1, // framing error (bit 1)
+ overun : 1; // overun error (bit 0)
+} Tstatus;
typedef union ctlStat { // control + status on same address
- Tcontrol ctl; // write-only
- Tstatus stat; // read-only
+ Tcontrol ctl; // write-only
+ Tstatus stat; // read-only
} TctlStat;
typedef union data { // data registers on same address
- int tx; // write-only
- int rx; // read-only
+ int tx; // write-only
+ int rx; // read-only
} Tdata;
-/*****************************************************
-?typedef struct serial { **
-? TctlStat cs; // @ (int *)IO_UART_ADDR **
-?} **
-*****************************************************/
-
typedef struct serial {
- TctlStat cs; // @ (int *)IO_UART_ADDR
- Tdata d; // @ (int *)(IO_UART_ADDR+1)
+ TctlStat cs; // @ (int *)IO_UART_ADDR
+ Tdata d; // @ (int *)(IO_UART_ADDR+1)
} Tserial;
#endif
diff --git a/cMIPS/serial.inp b/cMIPS/serial.inp
index 15134bdec23a345e5987e25f1fd697d0a553d472..f98e928dd92f29a59385f0c3de6f5b395f9dd2e8 100644
--- a/cMIPS/serial.inp
+++ b/cMIPS/serial.inp
@@ -44,3 +44,4 @@ f
2a
2b
+
diff --git a/cMIPS/tests/handlerUART.s b/cMIPS/tests/handlerUART.s
index 68251591a599a6cb34c024ea31c1e83369d253ac..2c4d73912e3fe8009bd0e30cc5acf761aa8e0433 100644
--- a/cMIPS/tests/handlerUART.s
+++ b/cMIPS/tests/handlerUART.s
@@ -107,7 +107,7 @@ UARTrxinter:
overrun:
jal print
- li $a0, 111
+ li $a0, 64017
# move $a0, $7
# do something if rx queue is full or tx is empty
# set overrun bit on uart statusReg
diff --git a/cMIPS/tests/jedidafu.c b/cMIPS/tests/jedidafu.c
index ec077d668472eb761480c1ae62c23f7d70bb4a90..eaa8b3bff79918ca29432468519b20a16cdbe108 100644
--- a/cMIPS/tests/jedidafu.c
+++ b/cMIPS/tests/jedidafu.c
@@ -1,58 +1,66 @@
#include "cMIPS.h"
#include "../include/vetorFib.h"
+#include "../include/structUart.h"
#define MAXPOW 7
-typedef struct UARTdriver {
-int rx_hd ; // reception queue head index
-int rx_tl ; // reception queue tail index
-char rx_q [16]; // reception queue
-int tx_hd ; // transmission queue head index
-int tx_tl ; // transmission queue tail index
-char tx_q [16]; // transmission queue
-int nrx ; // number of characters in rx_queue
-int ntx ; // number of spaces in tx_queue
-} UARTdriver ;
+
extern UARTdriver Ud ;
+volatile Tserial *uart; // tell GCC not to optimize away code
+
+int proberx () {
+ return Ud.nrx;
+}
+
+int probetx () {
+ return Ud.ntx;
+}
+int ctrl_util(int speed, int trx, int ttx, int rts) {
+ int ctl = 0;
+ ctl |= speed;
+ ctl |= trx<<3;
+ ctl |= ttx<<4;
+ ctl |= rts<<6;
+ return ctl;
+}
+
+void ioctl(int ctl){
+ Tcontrol aux;
+ aux.speed = ctl;
+ aux.intRX = ctl>>3;
+ aux.intTX = ctl>>4;
+ aux.rts = ctl>>6;
+ uart->cs.ctl= aux;
+}
+
+int iostat(){
+ int stat = 0;
+ stat |= uart->cs.stat.overun;
+ stat |= uart->cs.stat.framing<<1;
+ stat |= uart->cs.stat.int_RX_full<<3;
+ stat |= uart->cs.stat.int_TX_empt<<4;
+ stat |= uart->cs.stat.rxFull<<5;
+ stat |= uart->cs.stat.txEmpty<<6;
+ return stat;
+}
+
+int Putc (char c) {
+ int ntx = Ud.ntx;
+ if (ntx == 0)
+ return 0;
+ if (ntx == 16 && uart->cs.stat.txEmpty) // Empty Q && Tx
+ uart->d.tx = (unsigned int) c; // 32-bits
+ else { // Sending smthng
+ disableInterr();
+ Ud.ntx--;
+ // INCREMENTS AND THEN STORE
+ Ud.tx_tl = (Ud.tx_tl+1)&0xF; // modulo 16
+ Ud.tx_q[Ud.tx_tl] = c;
+ enableInterr();
+ }
+ return 1;
+}
-typedef struct control { // control register fields (uses only ls byte)
- int ign : 24, // ignore uppermost bits
- rts : 1, // Request to Send output (bit 7)
- ign2 : 2, // bits 6,5 ignored
- intTX : 1, // interrupt on TX buffer empty (bit 4)
- intRX : 1, // interrupt on RX buffer full (bit 3)
- speed : 3; // 4,8,16..256 tx-rx clock data rates (bits 0..2)
-} Tcontrol;
-
-typedef struct status { // status register fields (uses only ls byte)
- unsigned int ign : 24, // ignore uppermost 3 bytes
- cts : 1, // Clear To Send input=1 (bit 7)
- txEmpty : 1, // TX register is empty (bit 6)
- rxFull : 1, // octet available from RX register (bit 5)
- int_TX_empt: 1, // interrupt pending on TX empty (bit 4)
- int_RX_full: 1, // interrupt pending on RX full (bit 3)
- ign1 : 1, // ignored (bit 2)
- framing : 1, // framing error (bit 1)
- overun : 1; // overun error (bit 0)
-} Tstatus;
-
-
-typedef union ctlStat { // control + status on same address
- Tcontrol ctl; // write-only
- Tstatus stat; // read-only
-} TctlStat;
-
-typedef union data { // data registers on same address
- int tx; // write-only
- int rx; // read-only
-} Tdata;
-
-typedef struct serial {
- TctlStat cs;
- Tdata d;
-} Tserial;
-
- volatile Tserial *uart; // tell GCC not to optimize away code
char Getc () {
char c ;
if ( Ud.nrx > 0) {
@@ -68,9 +76,6 @@ char Getc () {
return c ;
}
-int proberx () {
- return Ud.nrx;
-}
int Strlen (char *c) {
int i= 0;
while(c[i++]-10);
@@ -85,28 +90,9 @@ int pow16 (int ex) {
return (ex%2?ret*16:ret);
}
-int hex2int (char *hex) {
- int s= Strlen(hex), i, ans= 0;
- #if 0
- Test Signal...
- switch (hex[0]) {
- case 'F':
- case 'f':
- case 'E':
- case 'e':
- case 'D':
- case 'd':
- case 'C':
- case 'c':
- case 'B':
- case 'b':
- case 'A':
- case 'a':
- case '9':
- ans = hex[0]*pow16(s-1);
- }
- #endif
- for (i= 0; i< s; i++) {
+int hex2int (int tam, char *hex) {
+ int i, ans= 0;
+ for (i = 0; i < tam; i++) {
hex[i]-= 48;
if (hex[i] > 9)
hex[i] -= 7;
@@ -114,10 +100,11 @@ int hex2int (char *hex) {
hex[i] -= 32;
if(hex[i] < 0)
hex[i]=0;
- ans += hex[i] * pow16(s-(i+1));
+ ans += hex[i] * pow16(tam-(i+1));
}
return ans;
}
+
int int2hex (char *c, int i) {
int j= 0, val;
int p;
@@ -138,105 +125,78 @@ int int2hex (char *c, int i) {
c[j] = 0;
return j-1;
}
-int Putc (char c) {
- int ntx = Ud.ntx;
- if (ntx == 0)
- return 0;
- if (ntx == 16 && uart->cs.stat.txEmpty) // Empty Q && Tx
- uart->d.tx = (unsigned int) c; // 32-bits
- else { // Sending smthng
- disableInterr();
- Ud.ntx--;
- // INCREMENTS AND THEN STORE
- Ud.tx_tl = (Ud.tx_tl+1)&0xF; // modulo 16
- Ud.tx_q[Ud.tx_tl] = c;
- enableInterr();
- }
- return 1;
-}
+
int main(void) { // receive a string through the UART serial interface
- int i, j;
- volatile int state;
- volatile Tstatus status;
- char filona[145], c;
- int hdona=0;
- int tlona=0;
- int filonx = 0;
- int valfib, qt, rxz, q;
- char p[15];
- Tcontrol ctrl;
-
- uart = (void *)IO_UART_ADDR; // bottom of UART address range
-
- ctrl.ign = 0;
- ctrl.rts = 0; // make RTS=0 to hold RemoteUnit
- ctrl.ign2 = 0;
- ctrl.intTX = 1;
- ctrl.intRX = 1;
- ctrl.speed = 2; // operate at the second highest data rate
- uart->cs.ctl = ctrl;
-
- i = -1;
-
- ctrl.ign = 0;
- ctrl.rts = 1; // make RTS=1 to activate RemoteUnit
- ctrl.ign2 = 0;
- ctrl.intTX = 1;
- ctrl.intRX = 1;
- ctrl.speed = 2; // operate at the second highest data rate
- uart->cs.ctl = ctrl;
- Ud.ntx = 16;
- do {
- state = i = i+1;
- // se tirar fode (b520 vira 15)
- while(!proberx()) to_stdout('-');//i = 1 - i;
- //to_stdout('\0');
- // es
- while((c=Getc()) != -1){
- filona[tlona] = c;
+ int i, j;
+ volatile int state;
+ volatile Tstatus status;
+ char filona[145], c;
+ int hdona=0;
+ int tlona=0;
+ int filonx = 0;
+ int valfib, qt, rxz, q;
+ int fim = 0;
+ char p[15];
+ Tcontrol ctrl;
+ uart = (void *)IO_UART_ADDR; // bottom of UART address range
+
+ i = -1;
+ ioctl(ctrl_util(2, 1, 1, 1));
+ Ud.ntx = 16;
+
+ do {
+ state = i = i+1;
// se tirar fode (b520 vira 15)
- to_stdout('*');
+ while(!proberx()) to_stdout('-');//i = 1 - i;
//to_stdout('\0');
// es
- tlona++;
- tlona%=145;
- if(c=='\n'){
- filonx++;
- filona[tlona] = 10;
+ while((c=Getc()) != -1){
+ filona[tlona] = c;
+ // se tirar fode (b520 vira 15)
+ to_stdout('*');
+ //to_stdout('\0');
+ // es
+ tlona++;
+ tlona%=145;
+ if(c=='\n'){
+ filonx++;
+ filona[tlona] = 10;
+ }
}
- }
- while(filonx > 0){
- qt = Strlen(filona+hdona);
- valfib = hex2int((filona+hdona));
- valfib = buf[valfib];
- hdona += qt+1;
- hdona %= 145;
- //print(valfib);
- qt = int2hex(p, valfib);
- j = -1;
- do {
- j++;
- while(((rxz = proberx())<10) && !(q=Putc(p[j])));
- while((c=Getc()) != -1){
- filona[tlona] = c;
- tlona++;
- tlona%=145;
- if(c=='\n'){
- filonx++;
- filona[tlona] = 10;
- }
- }
- if(!q)
- j--;
-
- } while (p[j] != 0);
- filonx--;
- }
-
- } while (i<20);
+ while(filonx > 0){
+ qt = Strlen(filona+hdona);
+ valfib = hex2int(qt, (filona+hdona));
+ valfib = buf[valfib];
+ hdona += qt+1;
+ hdona %= 145;
+ qt = int2hex(p, valfib);
+ j = -1;
+ do {
+ j++;
+ while(((rxz = proberx())<10) && !(q=Putc(p[j])));
+ while((c=Getc()) != -1){
+ filona[tlona] = c;
+ tlona++;
+ tlona%=145;
+ if(c=='\n'){
+ filonx++;
+ filona[tlona] = 10;
+ }
+ }
+ if(!q)
+ j--;
+
+ } while (p[j] != 0);
+ filonx--;
+ }
+ if(filonx == 0 && !fim)
+ fim = 1;
+ else if (filonx == 0 && fim)
+ return state+i;
+ } while (i<20);
- return(state+i);
+ return(state+i);
}