From 4cfe60e242db416c325740834cdd7fdc2b86fede Mon Sep 17 00:00:00 2001
From: Roberto Hexsel <roberto@inf.ufpr.br>
Date: Thu, 23 Jul 2015 11:56:26 -0300
Subject: [PATCH] improved exception testing

---
 cMIPS/tests/badVAddr.expected   |  14 +-
 cMIPS/tests/badVAddr.s          |  53 +++++++-
 cMIPS/tests/badVAddrMM.expected |  20 +--
 cMIPS/tests/badVAddrMM.s        |  52 +++++++-
 cMIPS/tests/counter.expected    |  81 ++----------
 cMIPS/tests/counter.s           | 225 +++++++++++++++++++++++++-------
 cMIPS/tests/doTests.sh          |   4 +-
 cMIPS/tests/mmu_double.s        |  39 +++++-
 cMIPS/tests/mmu_double2.s       |  42 +++++-
 cMIPS/tests/mmu_inval.s         |  44 +++++++
 cMIPS/tests/mmu_inval2.s        |  47 +++++++
 cMIPS/tests/mmu_mod.s           |  45 +++++++
 cMIPS/tests/mmu_mod2.s          |  48 ++++++-
 cMIPS/tests/mmu_refill.s        |  44 +++++++
 cMIPS/tests/mmu_refill2.s       |  42 ++++++
 cMIPS/tests/mmu_refill3.s       |  42 ++++++
 16 files changed, 693 insertions(+), 149 deletions(-)

diff --git a/cMIPS/tests/badVAddr.expected b/cMIPS/tests/badVAddr.expected
index 98580e3..76fe8c6 100644
--- a/cMIPS/tests/badVAddr.expected
+++ b/cMIPS/tests/badVAddr.expected
@@ -1,16 +1,16 @@
-00000518
+00000818
 [
 08800010
-00000519
+00000819
 ]
-00000519
+00000819
 [
 08800010
-0000051a
+0000081a
 ]
-0000051a
+0000081a
 [
 08800010
-0000051b
+0000081b
 ]
-0000051b
+0000081b
diff --git a/cMIPS/tests/badVAddr.s b/cMIPS/tests/badVAddr.s
index 4f10da1..ce34944 100644
--- a/cMIPS/tests/badVAddr.s
+++ b/cMIPS/tests/badVAddr.s
@@ -26,6 +26,30 @@ _exit:	nop	# flush pipeline
 	nop
 	.end _start
 	
+        .set noreorder
+        .set noat
+	
+        .org x_EXCEPTION_0000,0
+_excp_0000:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x01
+        nop
+        .org x_EXCEPTION_0100,0
+_excp_0100:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x02
+        nop
+
 	.org    x_EXCEPTION_0180,0 # exception vector_180
 	.global excp_180
 	.ent    excp_180
@@ -53,12 +77,37 @@ excp_180:
 	eret
 	.end excp_180
 
+        .org x_EXCEPTION_0200,0
+_excp_0200:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x03
+        nop
+        .org x_EXCEPTION_BFC0,0
+_excp_BFC0:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x04
+        nop
+
+
 
-	.org x_ENTRY_POINT,0	# normal code start
+	##
+	## 
+	##
+	.org 0x00000800,0	# well above normal code start
 main:	la $14, x_IO_BASE_ADDR  # used by handler
 	la $15, x_IO_BASE_ADDR
 	li $7, 3
-	la $3, here		# address for misaigned fetches
+	la $3, here		# address for misaligned fetches
 	nop
 
 here:	sw    $3, 0($15)
diff --git a/cMIPS/tests/badVAddrMM.expected b/cMIPS/tests/badVAddrMM.expected
index fafd121..5ef844d 100644
--- a/cMIPS/tests/badVAddrMM.expected
+++ b/cMIPS/tests/badVAddrMM.expected
@@ -1,19 +1,19 @@
 00000000
 [
 08800014
-00000518
+00000818
 0f000001
 ]
 00000001
 [
 08800014
-00000518
+00000818
 0f000002
 ]
 00000002
 [
 08800014
-00000518
+00000818
 0f000003
 ]
 00000003
@@ -22,19 +22,19 @@
 00000003
 [
 08800010
-00000558
+00000858
 00040001
 ]
 00000002
 [
 08800010
-00000558
+00000858
 00040002
 ]
 00000001
 [
 08800010
-00000558
+00000858
 00040003
 ]
 00000000
@@ -43,14 +43,14 @@
 00000000
 [
 08800014
-000005a0
+000008a0
 0f000001
 ]
 00000001
 00000002
 [
 08800014
-000005b8
+000008b8
 0f000003
 ]
 00000003
@@ -59,14 +59,14 @@
 00000003
 [
 08800010
-000005f0
+000008f0
 00040001
 ]
 00000002
 00000002
 [
 08800010
-00000610
+00000910
 00040003
 ]
 00000001
diff --git a/cMIPS/tests/badVAddrMM.s b/cMIPS/tests/badVAddrMM.s
index a6aa4d9..0323e72 100644
--- a/cMIPS/tests/badVAddrMM.s
+++ b/cMIPS/tests/badVAddrMM.s
@@ -27,6 +27,31 @@ _exit:	nop	# flush pipeline
 	.end _start
 	
 
+        .set noreorder
+        .set noat
+	
+        .org x_EXCEPTION_0000,0
+_excp_0000:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x01
+        nop
+        .org x_EXCEPTION_0100,0
+_excp_0100:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x02
+        nop
+
+
 	.org x_EXCEPTION_0180,0  # exception vector_180
 	.global excp_180
 	.ent    excp_180
@@ -58,8 +83,33 @@ excp_180:
 	.end excp_180
 
 
-	.org x_ENTRY_POINT,0    # normal code start
+        .org x_EXCEPTION_0200,0
+_excp_0200:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x03
+        nop
+        .org x_EXCEPTION_BFC0,0
+_excp_BFC0:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x04
+        nop
+
 
+	##
+	##==============================================================
+	##
+	.org 0x00000800,0	# well above normal code 
+	##
 	##
 	## do 4 stores: 1st aligned, 2nd, 3rd, 4th misaligned,
 	##   hence 3 exceptions of type AddrError store=x14
diff --git a/cMIPS/tests/counter.expected b/cMIPS/tests/counter.expected
index 810ac6b..3e27f3e 100644
--- a/cMIPS/tests/counter.expected
+++ b/cMIPS/tests/counter.expected
@@ -1,82 +1,17 @@
-0000001e
-00000027
-00000030
-
+int
 40808000
-0000003f
-00000076
-
-00000039
-00000053
-0000005c
-00000065
-0000006e
-
+int
 40808000
-0000007d
-000000b4
-
-00000077
-00000091
-0000009a
-000000a3
-000000ac
-
+int
 40808000
-000000bb
-000000f2
-
-000000b5
-000000cf
-000000d8
-000000e1
-000000ea
-
+int
 40808000
-000000f9
-00000130
-
-000000f3
-0000010d
-00000116
-0000011f
-00000128
-
+int
 40808000
-00000137
-0000016e
-
-00000131
-0000014b
-00000154
-0000015d
-00000166
-
+int
 40808000
-00000175
-000001ac
-
-0000016f
-00000189
-00000192
-0000019b
-000001a4
-
+int
 40808000
-000001b3
-000001ea
-
-000001ad
-000001c7
-000001d0
-000001d9
-000001e2
 
-40808000
-000001f1
-00000228
+ok
 
-000001eb
-00000205
-0000020f
-00000215
diff --git a/cMIPS/tests/counter.s b/cMIPS/tests/counter.s
index 7576608..05b669f 100644
--- a/cMIPS/tests/counter.s
+++ b/cMIPS/tests/counter.s
@@ -1,21 +1,16 @@
 # Testing the internal counter is difficult because it counts clock cycles
 # rather than instructions -- if the I/O or memory latencies change then
 # the simulation output also changes and comparisons are impossible.
-# To perform comparisons the trick is to only update the counter when the
-# PC is updated, thus counting instructions.  If there are any stalls,
-# the counter also stalls and the simulation outputs are the same
-# regardless of the relative latencies.
 
-	# mips-as -O0 -EL -mips32r2
 	.include "cMIPS.s"
 	.text
 	.align 2
 	.set noat
 	.set noreorder
+	.set numCy, 64
 	.global _start
 	.global _exit
-	.global exit
-	.ent _start
+
 _start: nop
         li   $k0, cop0_STATUS_reset # RESET, kernel mode, all else disabled
         mtc0 $k0, cop0_STATUS
@@ -27,7 +22,7 @@ _start: nop
 
 	la   $15,x_IO_BASE_ADDR
 	nop
-	jal main
+	j    main
 	nop
 exit:	
 _exit:	nop	# flush pipeline
@@ -38,77 +33,215 @@ _exit:	nop	# flush pipeline
 	wait	# then stop VHDL simulation
 	nop
 	nop
-	.end _start
+
 	
+        .org x_EXCEPTION_0000,0
+_excp_0000:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x01
+        nop
+        .org x_EXCEPTION_0100,0
+_excp_0100:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x02
+        nop
 	.org x_EXCEPTION_0180,0
-	.global _excp_180
-	.global excp_180
-	.ent _excp_180
-excp_180:	
 _excp_180:
-        mfc0  $k0,cop0_CAUSE	# read CAUSE and
-	sw    $k0,0($15)       	#   print it
-	eret
-	.end _excp_180
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x03
+	nop
 
-	
+	#
+	# interrupt handler ------------------------------------------------
+	#
 	.org x_EXCEPTION_0200,0
-	.ent _excp_200
-excp_200:	
 _excp_200:	
-	sw    $13, x_IO_ADDR_RANGE($15) # blank line
-        mfc0  $k0, cop0_CAUSE	# read CAUSE and
-	sw    $k0, 0($15)      	#   print it
-	mfc0  $k1, cop0_COUNT  	# print current COUNT
-	sw    $k1, 0($15)
-	addiu $k1, $k1,(64-9) 	# interrupt again in approx 64 cycles
+	mfc0  $k1, cop0_COUNT  	# read current COUNT
+	#sw    $k1, 0($15)
+	addi  $22, $22, numCy   # interval elapsed?
+	#sw    $22, 0($15)     	# show old+numCycles
+	slt   $k0, $22, $k1     # COUNT >= old+numcy ?
+	beq   $k0, $zero, err3
+	nop
+
+	addiu $k1, $k1, numCy 	# interrupt again in numCy cycles
 	mtc0  $k1, cop0_COMPARE
-	sw    $k1, 4($15)      	# show new limit
+	#sw    $k1, 0($15)      	# show new limit
+	
+	li    $30, 'i'
+        sw    $30, x_IO_ADDR_RANGE($15)
+	li    $30, 'n'
+        sw    $30, x_IO_ADDR_RANGE($15)
+	li    $30, 't'
+        sw    $30, x_IO_ADDR_RANGE($15)
+	sw    $13, x_IO_ADDR_RANGE($15) # blank line
 
-	li   $k0, 0x1800ff01   	# enable interrupts
-        mtc0 $k0, cop0_STATUS
-	sw   $13, x_IO_ADDR_RANGE($15) # blank line
+	mfc0  $k0, cop0_CAUSE	# read CAUSE and
+	lui   $k1, 0x7fff	#   mask-off branch-delay bit
+	ori   $k1, $k1, 0xffff
+	and   $k0, $k0, $k1
+	sw    $k0, 0($15)      	# print CAUSE
+	
+	li    $k0, 0x1800ff01   	# enable interrupts
+        mtc0  $k0, cop0_STATUS
+	ehb
+	eret
+
+err3:	
+	li    $30, 'i'
+        sw    $30, x_IO_ADDR_RANGE($15)
+	li    $30, 'n'
+        sw    $30, x_IO_ADDR_RANGE($15)
+	li    $30, 't'
+        sw    $30, x_IO_ADDR_RANGE($15)
+	li    $30, 'E'
+        sw    $30, x_IO_ADDR_RANGE($15)
+	li    $30, 'r'
+        sw    $30, x_IO_ADDR_RANGE($15)
+	li    $30, 'r'
+        sw    $30, x_IO_ADDR_RANGE($15)
+	sw    $13, x_IO_ADDR_RANGE($15) # blank line
+	sw    $22, 0($15)
+
+	li    $k0, 0x1800ff00   	# disable interrupts
+        mtc0  $k0, cop0_STATUS
+	ehb
 	eret
-	.end _excp_200
+
+	
+
+        .org x_EXCEPTION_BFC0,0
+_excp_BFC0:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x04
+        nop
 
 
+        ##
+        ##-----------------------------------------------------------------
+        ##
+	.set TRUE,  1
+	.set FALSE, 0
+	
 	.org x_ENTRY_POINT,0
 main:	la    $15, x_IO_BASE_ADDR
  	li    $13, '\n'
 
-	addiu $5,$zero,(64-9)   # interrupt again in approx 64 cycles
+	addiu $5,$zero, numCy  	# interrupt again in numCy cycles
 	mtc0  $5,cop0_COMPARE
 
+	# enable Counter
 	mfc0  $5,cop0_CAUSE
 	li    $6,0xf7ffffff    	# CAUSE(DisableCount) <= 0
 	and   $5,$5,$6
 	mtc0  $5,cop0_CAUSE   	# enable counter
 
+	li    $20, TRUE		# counting is monotonic?
+	li    $21, 0		# old value
+	li    $22, 0		# old value for interrupts
+	
 	addiu $11,$12,1        	# this is a NOP
 
-here:	addiu $11,$12,2	        # this is a NOP
-	mfc0  $16,cop0_COUNT   	# print current COUNT
-	sw    $16,0($15)
-	slti  $1,$16,0x200     	# COUNT > 0x200 => stop counter and program
-	beq   $1,$zero,there
+	#
+	# check if counting increases monotolically
+	#
+here:	addiu $11, $12, 2	# this is a NOP
+	mfc0  $16, cop0_COUNT   # read current COUNT
+	#sw    $16, 0($15)	# print current COUNT
+	slt   $1, $21, $16	# old < new?
+	beq   $1, $zero, err1	# no, stop simulation
+	nop
+
+	move  $21, $16          # old <- new
+	
+	slti  $1, $16, 0x200   	# COUNT > 0x200 => stop counter and program
+	beq   $1, $zero, there
 	addiu $11,$12,3		# this is a NOP
 	addiu $11,$12,4		# this is a NOP
 	b here
 	addiu $11,$12,5		# this is a NOP
 
-	sw    $13, x_IO_ADDR_RANGE($15)
-there:	mfc0  $5,cop0_CAUSE
+	#
+	# check if the counter stops
+	#
+there:	sw    $13, x_IO_ADDR_RANGE($15) # print a newline
+	mfc0  $5,cop0_CAUSE
 	lui   $6,0x0880        	# CAUSE(DisableCount) <= 1
-	or    $5,$5,$6
-	mtc0  $5,cop0_CAUSE   	# disable counter
+	or    $5, $5, $6
+	mtc0  $5, cop0_CAUSE   	# disable counter
 	addiu $11,$12,6		# this is a NOP
-	mfc0  $16,cop0_COUNT   	# print current COUNT
-	sw    $16,0($15)
+	mfc0  $18, cop0_COUNT  	# print current COUNT
+	#sw    $18, 0($15)
 	addiu $11,$12,7		# this is a NOP
 	addiu $11,$12,8		# this is a NOP
 	addiu $11,$12,9		# this is a NOP
 	addiu $11,$12,10	# this is a NOP
-	mfc0  $16,cop0_COUNT   	# print current COUNT
-	sw    $16,0($15)
-	j exit
+	mfc0  $19, cop0_COUNT  	# print current COUNT
+	#sw    $19, 0($15)
+	bne   $18, $19, err2    # did counter stop?
 	nop
+
+	# nothing wrong
+ok:	li   $30, 'o'
+        sw   $30, x_IO_ADDR_RANGE($15)
+        li   $30, 'k'
+        sw   $30, x_IO_ADDR_RANGE($15)
+	sw   $13, x_IO_ADDR_RANGE($15) # print a newline
+	j exit
+	sw   $13, x_IO_ADDR_RANGE($15) # print a newline
+
+	
+	# non-monotonic
+err1:	li   $30, 'n'
+        sw   $30, x_IO_ADDR_RANGE($15)
+        li   $30, 'o'
+        sw   $30, x_IO_ADDR_RANGE($15)
+        li   $30, 'n'
+        sw   $30, x_IO_ADDR_RANGE($15)
+        li   $30, 'M'
+        sw   $30, x_IO_ADDR_RANGE($15)
+        li   $30, 'o'
+        sw   $30, x_IO_ADDR_RANGE($15)
+        li   $30, 'n'
+        sw   $30, x_IO_ADDR_RANGE($15)
+	j exit
+	sw   $13, x_IO_ADDR_RANGE($15) # print a newline
+
+	
+	# counter did not stop
+err2:	li   $30, 'n'
+        sw   $30, x_IO_ADDR_RANGE($15)
+        li   $30, 'o'
+        sw   $30, x_IO_ADDR_RANGE($15)
+        li   $30, 't'
+        sw   $30, x_IO_ADDR_RANGE($15)
+        li   $30, 'S'
+        sw   $30, x_IO_ADDR_RANGE($15)
+        li   $30, 't'
+        sw   $30, x_IO_ADDR_RANGE($15)
+        li   $30, 'o'
+        sw   $30, x_IO_ADDR_RANGE($15)
+        li   $30, 'p'
+        sw   $30, x_IO_ADDR_RANGE($15)
+	j exit
+	sw   $13, x_IO_ADDR_RANGE($15) # print a newline
diff --git a/cMIPS/tests/doTests.sh b/cMIPS/tests/doTests.sh
index bd027c7..de6d677 100755
--- a/cMIPS/tests/doTests.sh
+++ b/cMIPS/tests/doTests.sh
@@ -70,7 +70,7 @@ a_FUN="jaljr jr_2 jal_fun_jr jalr_jr bltzal_fun_jr"
 a_OTH="mult div sll slr movz wsbh_seb extract insert"
 a_BHW="lbsb lhsh lwsw lwswIncr swlw lwl_lwr"
 a_MEM="lwSweepRAM"
-a_CTR="teq_tne teq_jal tlt_tlti tltu_tgeu eiDI ll_sc overflow"
+a_CTR="teq_tne teq_jal tlt_tlti tltu_tgeu eiDI ll_sc overflow counter"
 a_COP="mtc0CAUSE2 mtc0EPC syscall break mfc0CONFIG badVAddr badVAddrMM"
 a_MMU="mmu_index mmu_tlbwi mmu_tlbp mmu_tlbwr mmu_context"
 a_EXC="mmu_refill mmu_refill2 mmu_refill3 mmu_inval mmu_inval2 mmu_mod mmu_mod2 mmu_double mmu_double2"
@@ -78,8 +78,6 @@ a_EXC="mmu_refill mmu_refill2 mmu_refill3 mmu_inval mmu_inval2 mmu_mod mmu_mod2
 ## these tests MUST be run with FAKE CACHES
 # a_IOs="kbd7seg" 
 
-## these tests are timing dependent and MUST be run with memory latency=0
-# a_TIM="counter"
 
 
 ## force an update of all include files with edMemory.sh
diff --git a/cMIPS/tests/mmu_double.s b/cMIPS/tests/mmu_double.s
index dd6ac74..b4db6f1 100644
--- a/cMIPS/tests/mmu_double.s
+++ b/cMIPS/tests/mmu_double.s
@@ -55,11 +55,11 @@ _start:	li   $k0, 0x10000000
         ## exception vector_0000 TLBrefill, from See MIPS Run pg 145
         ##
         .org x_EXCEPTION_0000,0
-        .ent _excp_100
+        .ent _excp_000
         .set noreorder
         .set noat
 
-_excp_100:  mfc0 $k1, cop0_Context
+_excp_000:  mfc0 $k1, cop0_Context
         lw   $k0, 0($k1)           # k0 <- TP[Context.lo]
         lw   $k1, 8($k1)           # k1 <- TP[Context.hi]
         mtc0 $k0, cop0_EntryLo0    # EntryLo0 <- k0 = even element
@@ -78,9 +78,21 @@ _excp_100:  mfc0 $k1, cop0_Context
 	sw   $30, x_IO_ADDR_RANGE($20)
 
 	eret
-        .end _excp_100
+        .end _excp_000
 
 
+	.org x_EXCEPTION_0100,0
+_excp_0100:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x02
+        nop
+	
+
 	##
         ##================================================================
         ## general exception vector_0180
@@ -114,6 +126,27 @@ _excp_180: tlbp         # probe for the guilty entry
         eret			# return to the EPC saved on the first fault
         .end _excp_180		#   the second fault refills TLB
 
+
+_excp_0200:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x03
+        nop
+        .org x_EXCEPTION_BFC0,0
+_excp_BFC0:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x04
+        nop
+
 	
 	##
         ##================================================================
diff --git a/cMIPS/tests/mmu_double2.s b/cMIPS/tests/mmu_double2.s
index 8742a23..d429277 100644
--- a/cMIPS/tests/mmu_double2.s
+++ b/cMIPS/tests/mmu_double2.s
@@ -55,11 +55,11 @@ _start:	li   $k0, 0x10000000
         ## exception vector_0000 TLBrefill, from See MIPS Run pg 145
         ##
         .org x_EXCEPTION_0000,0
-        .ent _excp_100
+        .ent _excp_000
         .set noreorder
         .set noat
 
-_excp_100:  mfc0 $k1, cop0_Context
+_excp_000:  mfc0 $k1, cop0_Context
         lw   $k0, 0($k1)           # k0 <- TP[Context.lo]
         lw   $k1, 8($k1)           # k1 <- TP[Context.hi]
         mtc0 $k0, cop0_EntryLo0    # EntryLo0 <- k0 = even element
@@ -78,9 +78,23 @@ _excp_100:  mfc0 $k1, cop0_Context
 	sw   $30, x_IO_ADDR_RANGE($20)
 
 	eret
-        .end _excp_100
+        .end _excp_000
 
 
+        .org x_EXCEPTION_0100,0
+_excp_0100:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x02
+        nop
+
+
+	
+
 	##
         ##================================================================
         ## general exception vector_0180
@@ -114,6 +128,28 @@ _excp_180: tlbp         # probe for the guilty entry
         eret			# return to the EPC saved on the first fault
         .end _excp_180		#   the second fault refills TLB
 
+
+_excp_0200:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x03
+        nop
+        .org x_EXCEPTION_BFC0,0
+_excp_BFC0:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x04
+        nop
+
+
 	
 	##
         ##================================================================
diff --git a/cMIPS/tests/mmu_inval.s b/cMIPS/tests/mmu_inval.s
index ecf0975..b9099eb 100644
--- a/cMIPS/tests/mmu_inval.s
+++ b/cMIPS/tests/mmu_inval.s
@@ -44,6 +44,29 @@ _start:	li   $k0, 0x10000000
 	nop
 	.end _start
 	
+
+        .org x_EXCEPTION_0000,0
+_excp_0000:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x01
+        nop
+                .org x_EXCEPTION_0100,0
+_excp_0100:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x02
+        nop
+
+
 	##
         ##================================================================
         ## general exception vector_0180
@@ -80,6 +103,27 @@ _excp:	tlbp		# probe for the guilty entry
         .end _excp
 
 
+_excp_0200:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x03
+        nop
+        .org x_EXCEPTION_BFC0,0
+_excp_BFC0:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x04
+        nop
+
+
 	##
         ##================================================================
         ## normal code starts here
diff --git a/cMIPS/tests/mmu_inval2.s b/cMIPS/tests/mmu_inval2.s
index 36e3ac4..e171c0d 100644
--- a/cMIPS/tests/mmu_inval2.s
+++ b/cMIPS/tests/mmu_inval2.s
@@ -43,6 +43,30 @@ _start:	li   $k0, 0x10000000
 	j main
 	nop
 	.end _start
+
+
+
+        .org x_EXCEPTION_0000,0
+_excp_0000:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x01
+        nop
+                .org x_EXCEPTION_0100,0
+_excp_0100:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x02
+        nop
+
 	
 	##
         ##================================================================
@@ -78,6 +102,29 @@ _excp:	tlbp		# probe for the guilty entry
 	eret
         .end _excp
 
+
+
+_excp_0200:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x03
+        nop
+        .org x_EXCEPTION_BFC0,0
+_excp_BFC0:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x04
+        nop
+
+	
 	##
         ##================================================================
         ## normal code starts here
diff --git a/cMIPS/tests/mmu_mod.s b/cMIPS/tests/mmu_mod.s
index d705110..0eb529b 100644
--- a/cMIPS/tests/mmu_mod.s
+++ b/cMIPS/tests/mmu_mod.s
@@ -44,6 +44,30 @@ _start:	li   $k0, 0x10000000
 	j main
 	nop
 	.end _start
+
+
+
+	.org x_EXCEPTION_0000,0
+_excp_0000:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x01
+        nop
+	        .org x_EXCEPTION_0100,0
+_excp_0100:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x02
+        nop
+
 	
 	##
         ##================================================================
@@ -85,6 +109,27 @@ _excp:	tlbp		# probe for the guilty entry
 	eret
         .end _excp
 
+
+_excp_0200:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x03
+        nop
+        .org x_EXCEPTION_BFC0,0
+_excp_BFC0:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x04
+        nop
+
 	##
         ##================================================================
         ## normal code starts here
diff --git a/cMIPS/tests/mmu_mod2.s b/cMIPS/tests/mmu_mod2.s
index c318f1a..1da9106 100644
--- a/cMIPS/tests/mmu_mod2.s
+++ b/cMIPS/tests/mmu_mod2.s
@@ -44,7 +44,30 @@ _start:	li   $k0, 0x10000000
 	j main
 	nop
 	.end _start
-	
+
+
+	.org x_EXCEPTION_0000,0
+_excp_0000:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x01
+        nop
+                .org x_EXCEPTION_0100,0
+_excp_0100:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x02
+        nop
+
+
 	##
         ##================================================================
         ## general exception vector_0180
@@ -86,6 +109,29 @@ _excp:	tlbp		# probe for the guilty entry
 	eret
         .end _excp
 
+
+_excp_0200:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x03
+        nop
+        .org x_EXCEPTION_BFC0,0
+_excp_BFC0:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x04
+        nop
+
+
+	
 	##
         ##================================================================
         ## normal code starts here
diff --git a/cMIPS/tests/mmu_refill.s b/cMIPS/tests/mmu_refill.s
index 3e16fb9..bdf19ce 100644
--- a/cMIPS/tests/mmu_refill.s
+++ b/cMIPS/tests/mmu_refill.s
@@ -74,6 +74,50 @@ _excp:  mfc0 $k1, cop0_Context
 	eret
         .end _excp
 
+
+        .org x_EXCEPTION_0100,0
+_excp_0100:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x02
+        nop
+        .org x_EXCEPTION_0180,0
+_excp_0180:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x02
+        nop
+_excp_0200:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x03
+        nop
+        .org x_EXCEPTION_BFC0,0
+_excp_BFC0:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x04
+        nop
+
+
+
+
 	##
         ##================================================================
         ## normal code starts here
diff --git a/cMIPS/tests/mmu_refill2.s b/cMIPS/tests/mmu_refill2.s
index 471e44e..38ad488 100644
--- a/cMIPS/tests/mmu_refill2.s
+++ b/cMIPS/tests/mmu_refill2.s
@@ -86,6 +86,48 @@ _excp:  mfc0 $k1, cop0_Context
 	eret
         .end _excp
 
+        .org x_EXCEPTION_0100,0
+_excp_0100:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x02
+        nop
+        .org x_EXCEPTION_0180,0
+_excp_0180:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x02
+        nop
+_excp_0200:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x03
+        nop
+        .org x_EXCEPTION_BFC0,0
+_excp_BFC0:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x04
+        nop
+
+
+
 	##
         ##================================================================
         ## normal code starts here
diff --git a/cMIPS/tests/mmu_refill3.s b/cMIPS/tests/mmu_refill3.s
index 292354a..3e7f29b 100644
--- a/cMIPS/tests/mmu_refill3.s
+++ b/cMIPS/tests/mmu_refill3.s
@@ -98,6 +98,48 @@ _ex_w:	tlbwi                      # update TLB
 	eret
         .end _excp
 
+
+	        .org x_EXCEPTION_0100,0
+_excp_0100:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x02
+        nop
+        .org x_EXCEPTION_0180,0
+_excp_0180:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x02
+        nop
+_excp_0200:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x03
+        nop
+        .org x_EXCEPTION_BFC0,0
+_excp_BFC0:
+        la   $k0, x_IO_BASE_ADDR
+        mfc0 $k1, cop0_CAUSE
+        sw   $k1, 0($k0)        # print CAUSE, flush pipe and stop simulation
+        nop
+        nop
+        nop
+        wait 0x04
+        nop
+
+
 	##
         ##================================================================
         ## normal code starts here
-- 
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