diff --git a/cMIPS/vhdl/fpu.vhd b/cMIPS/vhdl/fpu.vhd index c848afca54a7f87be648b7386548682616f20a96..b612728754196be5570b69c66488a099bb3aab62 100644 --- a/cMIPS/vhdl/fpu.vhd +++ b/cMIPS/vhdl/fpu.vhd @@ -836,17 +836,13 @@ architecture estrutural of FPU is --pronto,wt_out : out std_logic); --end component div32float; - signal wt,wt0,pt0,selA_mul,selB_mul,selC_mul, wt_st0 : std_logic ; - signal wt1,pt1,selA_sum,selB_sum,selC_sum : std_logic ; - signal wt2,pt2,selA_div,selB_div,selC_div : std_logic ; - signal RES_MUL,RES_SUM,RES_DIV : std_logic_vector(31 DOWNTO 0) ; + signal wt,wt0,pt0,selA_mul,selB_mul,selC_mul, wt_mul, wt_st0 : std_logic; + signal wt1,pt1,selA_sum,selB_sum,selC_sum : std_logic; + signal wt2,pt2,selA_div,selB_div,selC_div : std_logic; + signal RES_MUL,RES_SUM,RES_DIV : std_logic_vector(31 DOWNTO 0); begin - U_WAIT_ON_READS: component wait_states - generic map (1) port map (rst,clk,selC_mul,wt_st0); - - U_Mult_float: mult32float port map (data_inp,clk,rst,'0',selA_mul,selB_mul,selC_mul,RES_MUL,pt0,wt0); @@ -884,7 +880,12 @@ begin --selB_div <= '1' when sel = '0' and addr = "0101" and wr = '0' else '0'; --selC_div <= '1' when sel = '0' and addr = "0100" and wr = '1' else '0'; - rdy <= not(wt_st0) and not((wt0 and selC_mul)); -- or (wt1 and selC_sum)); --or (wt2 and selC_div)); + wt_mul <= not(selC_mul); + + U_WAIT_ON_READS: component wait_states + generic map (1) port map (rst, clk, wt_mul, wt_st0); + + rdy <= not(wt_st0 or (wt0 and selC_mul)); -- or (wt1 and selC_sum)); --or (wt2 and selC_div)); data_out <= RES_MUL when selC_mul = '1' else RES_SUM when selC_sum = '1' else diff --git a/cMIPS/vhdl/io.vhd b/cMIPS/vhdl/io.vhd index 2a850f32bc448309665bedb699da201d890ab098..cc5244a50f0ba779818af7b13ff2eab85b263a00 100644 --- a/cMIPS/vhdl/io.vhd +++ b/cMIPS/vhdl/io.vhd @@ -735,7 +735,7 @@ begin U_WAIT2: FFD port map (clk, rst, '1', wait1, wait2); - rdy <= not(wait1) and not(wait2) and waiting; + rdy <= not(wait1 or wait2 or waiting); -- wait for 260ns sel_rs <= addr when sel = '0' else RS; U_INPUT_RS: FFD port map (clk, rst, '1', sel_rs, RS); @@ -745,7 +745,7 @@ begin U_OUTPUT: registerN generic map (NUM_BITS, START_VALUE) port map (clk, rst, lcd_read, out_data, data_out(NUM_BITS-1 downto 0)); - data_out(31 downto NUM_BITS) <= (others => '0'); + data_out(31 downto NUM_BITS) <= (others => 'X'); -- TESTING ONLY out_data <= b"00000000" when RW = '1' else (others => 'X'); @@ -827,46 +827,46 @@ begin when st_init => lcd_enable <= '0'; -- disable lcd_read <= '1'; - waiting <= '1'; + waiting <= '0'; when st_idle => lcd_enable <= '0'; -- disable lcd_read <= '1'; - waiting <= '1'; + waiting <= '0'; when st_n | st_n1 => lcd_enable <= '0'; -- disable, waiting for setup lcd_read <= '1'; - waiting <= '0'; + waiting <= '1'; when st_n2 | st_n3 | st_n4 | st_n5 | st_n6 | st_n7 => lcd_enable <= '1'; -- enable, waiting lcd_read <= '1'; - waiting <= '0'; + waiting <= '1'; when st_n8 => lcd_enable <= '1'; -- enable, still waiting lcd_read <= '0'; - waiting <= '0'; + waiting <= '1'; when st_n9 => lcd_enable <= '1'; -- enable, still waiting lcd_read <= '1'; - waiting <= '0'; + waiting <= '1'; when st_na => lcd_enable <= '0'; -- disable, still waiting lcd_read <= '1'; - waiting <= '0'; + waiting <= '1'; when st_nb => lcd_enable <= '0'; -- disable, stop waiting lcd_read <= '1'; -- hold inp data for 40ns - waiting <= '1'; + waiting <= '0'; when others => lcd_enable <= '0'; -- disable - waiting <= '1'; + waiting <= '0'; end case; end process U_st_outputs;