From eea4da3af4b1d82df34ab8197b1b64e8830451c5 Mon Sep 17 00:00:00 2001 From: Roberto Hexsel <roberto@inf.ufpr.br> Date: Fri, 1 Apr 2016 18:28:31 -0300 Subject: [PATCH] incomplete SDRAM controller --- cMIPS/vhdl/sdram.vhd | 122 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 cMIPS/vhdl/sdram.vhd diff --git a/cMIPS/vhdl/sdram.vhd b/cMIPS/vhdl/sdram.vhd new file mode 100644 index 0000000..0e0ec2f --- /dev/null +++ b/cMIPS/vhdl/sdram.vhd @@ -0,0 +1,122 @@ +-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +-- cMIPS, a VHDL model of the classical five stage MIPS pipeline. +-- Copyright (C) 2013 Roberto Andre Hexsel +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, version 3. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <http://www.gnu.org/licenses/>. +-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + + + + +-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +-- SDRAM controller for Macnica's development board Mercurio IV +-- IS42S16320B, 512Mbit SDRAM, 146MHz, 32Mx16bit +-- +-- design premise: banks are not interleaved; BA0,BA1 are MS address bits +-- +-- TODO: +-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +use work.p_wires.all; +use work.p_memory.all; + +entity SDRAM_controller is + port (rst : in std_logic; -- FPGA reset + clk : in std_logic; -- 100MHz clock + + hcs : in std_logic; -- host side chip select + rdy : in std_logic; -- tell CPU to wait + wr : in std_logic; -- host side write enable + bsel : in reg4; -- byte select + haddr : in reg26; -- host side address + hDinp : in reg32; -- host side data input + hDout : out reg32; -- host side data output + + cke : out std_logic; -- ram side clock enable + scs : out std_logic; -- ram side chip select + ras : out std_logic; -- ram side RAS + cas : out std_logic; -- ram side CAS + we : out std_logic; -- ram side write enable + dqm0 : out std_logic; -- ram side byte0 output enable + dqm1 : out std_logic; -- ram side byte0 output enable + ba0 : out std_logic; -- ram side bank select 0 + ba1 : out std_logic; -- ram side bank select 1 + saddr : out reg12; -- ram side address + sdata :inout reg16); -- ram side data + + type sdram_cmd is (cmd_NOP, cmd_PALL, cmd_ARF, cmd_LMR, cmd_ACT, + cmd_RD, cmd_WR, cmd_invalid); + +end entity SDRAM_controller; + + +architecture simple of SDRAM_controller is + + component registerN is + generic (NUM_BITS: integer; INIT_VAL: std_logic_vector); + port(clk, rst, ld: in std_logic; + D: in std_logic_vector; + Q: out std_logic_vector); + end component registerN; + + signal reset_done, same_row : boolean := FALSE; + signal addr : reg26; + signal last_row : reg13; + signal col_bits : reg10; + signal rwo_bits : reg13; + +begin -- simple + + + U_address: registerN generic map (26, b"00"&x"000000") + port map (clk, rst, hcs, haddr, addr); + + row_bits <= addr(23 downto 11); + col_bits <= addr(10 downto 1); + ba0 <= addr(24); + ba1 <= addr(25); + + U_last_row: registerN generic map (13, '0'&x"000") + port map (clk, rst, active, haddr(23 downto 11), last_row); + + + + + + + + + + + -- purpose: wait for 100us after reset + U_rst_100us: process (clk2x,rst) + variable cnt : integer := 0; + begin -- process clk2x + if rst = '0' then + cnt := 0; + reset_done <= FALSE; + elsif rising_edge(clk) then + cnt := cnt + 1; + if cnt = 10000 then -- 100us elapsed + reset_done <= TRUE; + wait; + end if; + end if; + end process clk2x; + + +end simple; + + -- GitLab