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tests

Forked from Roberto Hexsel / cMIPS

31 commits behind, 8 commits ahead of the upstream repository.

Talvez rx esteja pronto

Jedian authored 9 years ago

Signed-off-by: Jedian <jmb15@c3sl.ufpr.br>

708410d2

708410d2 9 years ago

Name	Last commit	Last update
..
FPU_m.c
FPU_m.expected
bXtz.expected
bXtz.s
badVAddr.expected
badVAddr.s
badVAddrMM.expected
badVAddrMM.s
beq_dlySlot.expected
beq_dlySlot.s
bltzal_fun_jr.expected
bltzal_fun_jr.s
break.expected
break.s
break_n.s
bubble.c
bubble.expected
busError_d.expected
busError_d.s
busError_i.expected
busError_i.s
ccitt16.c
ccitt16.expected
counter.expected
counter.s
dCacheTst.expected
dCacheTst.s
dCacheTstB.expected
dCacheTstB.s
dCacheTstH.expected
dCacheTstH.s
data.bin
dct-int.c
dijkstra_input.h
div.expected
div.s
divmul.c
divmul.expected
doTests.sh
dump.data
echo.c
eiDI.expected
eiDI.s
extCounter.c
extCounter.expected
extCounterInt.c
extCounterInt.expected
extract.expected
extract.s
fat.c
fat.expected
fib.c
fib.expected
fwdAddAddAddSw.expected
fwdAddAddAddSw.s
fwd_SW.expected
fwd_SW.s
gcd.c
gcd.expected
genVector.c
handlerUARTjedi.s
handlerUARTjedi2.s
infiniteLoop.s
input.data
insert.expected
insert.s
insertion.c
insertion.expected
interrJR_dlySlot.expected
interrJR_dlySlot.s
interr_x2.expected
interr_x2.s
interrupt.expected
interrupt.s
jal_fun_jr.expected
jal_fun_jr.s
jaljr.expected
jaljr.s
jallwjr.expected
jallwjr.s
jalr_jr.expected
jalr_jr.s
jr_2.expected
jr_2.s
jr_dlySlot.expected
jr_dlySlot.s
kbd7seg.expected
kbd7segMacnica.s
lbUsbUCache.expected
lbUsbUCache.s
lbsb.expected
lbsb.s
lbsbCache.expected
lbsbCache.s
lhUshUCache.expected
lhUshUCache.s
lhsh.expected
lhsh.s
ll_sc.expected
ll_sc.s