diff --git a/reg128.vhd b/reg128.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..04e7c25bd3ec061b9dc466d6b4665ffbd37a0dc5
--- /dev/null
+++ b/reg128.vhd
@@ -0,0 +1,24 @@
+library ieee;                                                                       
+use ieee.std_logic_1164.all;                                                        
+use ieee.numeric_std.all;
+
+entity reg64 is
+    port(
+        clk:    in std_logic;
+        rst:  in std_logic;
+        inp:    in std_logic_vector(127 downto 0);
+        outp:   out std_logic_vector(127 downto 0)
+    );
+end reg64;
+
+architecture arc_reg64 of reg64 is
+begin
+    process(clk, rst)
+        begin
+            if rst =  '1' then
+                outp <= x"00000000000000000000000000000000";
+            elsif clk'event and clk = '1' then
+                outp <= inp;
+            end if;
+    end process;
+end architecture arc_reg64;
diff --git a/reg64.vhd b/reg64.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a8602ff3f0ada64ad987cedd84311eec75732617
--- /dev/null
+++ b/reg64.vhd
@@ -0,0 +1,24 @@
+library ieee;                                                                       
+use ieee.std_logic_1164.all;                                                        
+use ieee.numeric_std.all;
+
+entity reg64 is
+    port(
+        clk:    in std_logic;
+        rst:  in std_logic;
+        inp:    in std_logic_vector(63 downto 0);
+        outp:   out std_logic_vector(63 downto 0)
+    );
+end reg64;
+
+architecture arc_reg64 of reg64 is
+begin
+    process(clk, rst)
+        begin
+            if rst =  '1' then
+                outp <= x"0000000000000000";
+            elsif clk'event and clk = '1' then
+                outp <= inp;
+            end if;
+    end process;
+end architecture arc_reg64;