diff --git a/mux.vhd b/mux.vhd new file mode 100644 index 0000000000000000000000000000000000000000..dc9499ea52054558282f467cffabdd18820593ea --- /dev/null +++ b/mux.vhd @@ -0,0 +1,48 @@ +-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +-- complete implementation of patterson and hennessy single cycle mips processor +-- copyright (c) 2015 darci luiz tomasi junior +-- +-- this program is free software: you can redistribute it and/or modify +-- it under the terms of the gnu general public license as published by +-- the free software foundation, version 3. +-- +-- this program is distributed in the hope that it will be useful, +-- but without any warranty; without even the implied warranty of +-- merchantability or fitness for a particular purpose. see the +-- gnu general public license for more details. +-- +-- you should have received a copy of the gnu general public license +-- along with this program. if not, see <http://www.gnu.org/licenses/>. +-- +-- engineer: darci luiz tomasi junior +-- e-mail: dltj007@gmail.com +-- date : 08/07/2015 - 19:11 +-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +library ieee; +use ieee.std_logic_1164.all; + +entity mux is + port( + in_a : in std_logic_vector(31 downto 0); + in_b : in std_logic_vector(31 downto 0); + in_c : in std_logic_vector(31 downto 0); + sel : in std_logic_vector(1 downto 0); + out_a : out std_logic_vector(31 downto 0) + ); +end mux; + +architecture arc_mux of mux is + +begin + process(sel, in_a, in_b, in_c) + begin + if sel = "00" then + out_a <= in_a; + elsif sel = "01" then + out_a <= in_b; + elsif sel = "10" then + out_a <= in_c; + end if; + end process; +end arc_mux; +