diff --git a/forward.vhd b/forward.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..10f31d0a9b1bb0200c5061664dd584787feb9b70
--- /dev/null
+++ b/forward.vhd
@@ -0,0 +1,55 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity forward is
+    port(
+        reset :  in  std_logic;
+        rs    :  in  std_logic_vector(4 downto 0);
+        rt    :  in  std_logic_vector(4 downto 0);
+        writeMm: in  std_logic;
+        rd_mm :  in  std_logic_vector(4 downto 0);
+        writeWb: in  std_logic;
+        rd_wb :  in  std_logic_vector(4 downto 0);
+        sela  :  out std_logic_vector(1 downto 0);
+        selb  :  out std_logic_vector(1 downto 0)
+    );
+end forward;
+
+architecture arc_forward of forward is
+begin
+    process(reset, rs, rt, rd_mm, rd_wb, writeMm, writeMm)
+    begin
+        if reset = '1' or (writeMm = '0' and writeWb = '0') then
+            sela <= "00";
+            selb <= "00";
+        else
+            if writeWb = '1' then
+                if (rs = rd_wb) then
+                    sela <= "10";
+                else
+                    sela <= "00";
+                end if;
+                if (rt = rd_wb) then
+                    selb <= "10";
+                else
+                    selb <= "00";
+                end if;
+            end if;
+            -- Memory forwarding has priority
+            if writeMm = '1' then
+                if (rs = rd_mm) then
+                    sela <= "01";
+                else
+                    sela <= "00";
+                end if;
+                if (rt = rd_mm) then
+                    selb <= "01";
+                else
+                    selb <= "00";
+                end if;
+            end if;
+        end if;
+
+    end process;
+end architecture arc_forward;
diff --git a/main_cttrl.vhd b/main_cttrl.vhd
index d75260d54f616830471962c09651f523902356ce..23a9db16732141800493b650dad5903155acbde5 100644
--- a/main_cttrl.vhd
+++ b/main_cttrl.vhd
@@ -279,7 +279,7 @@ architecture arc_main_processor of main_processor is
     -- cmp
 	signal s_cmp_zero :  		std_logic;
 
-    -- forward detection
+    -- forward
     signal s_sela_frwrd :   std_logic_vector(1 downto 0);	
     signal s_selb_frwrd :   std_logic_vector(1 downto 0);	
     signal s_rs_ex  :       std_logic_vector(4 downto 0);
@@ -288,7 +288,9 @@ architecture arc_main_processor of main_processor is
     signal s_rd_wb  :       std_logic_vector(4 downto 0);
     signal s_wrtMm  :       std_logic;
     signal s_wrtWb  :       std_logic;
+    signal s_ex_aluSrc:     std_logic;
     signal s_frwrd_b:       std_logic_vector(31 downto 0);
+    signal s_mm_frwrd:      std_logic_vector(31 downto 0);
 
 	--inst
 	signal s_inst_out_a :		std_logic_vector(31 downto 0);
@@ -408,17 +410,19 @@ begin
     s_rd_wb           <= s_mm_wb_out(4 downto 0);
     s_wrtMm           <= s_ex_mm_out(72);
     s_wrtWb           <= s_mm_wb_out(70);
+    s_mm_frwrd        <= s_ex_mm_out(68 downto 37);
+    s_ex_aluSrc       <= s_id_ex_out(114);
     c_forward:        forward port map(reset, s_rs_ex, s_rt_ex, s_wrtMm, s_rd_mm,
-                         s_wrtWb, s_rd_wb, s_sela_frwrd, s_selb_frwrd);
+                          s_wrtWb, s_rd_wb, s_sela_frwrd, s_selb_frwrd);
 
     --                                  reg_out_a                   ula_out_ant
-    c_mux_fwrd_a:     mux port map(s_id_ex_out(113 downto 82), s_ex_mm_out(68 downto 37),
-                            s_mx_5_out_a, s_sela_frwrd, s_alu_inp_a);
+    c_mux_fwrd_a:     mux port map(s_id_ex_out(113 downto 82), s_mm_frwrd, s_mx_5_out_a,
+                          s_sela_frwrd, s_alu_inp_a);
     --                                 reg_out_b                   ula_out_ant
-    c_mux_fwrd_b:     mux port map(s_id_ex_out(81 downto 50), s_ex_mm_out(68 downto 37),
-                            s_mx_5_out_a, s_selb_frwrd, s_frwrd_b);
+    c_mux_fwrd_b:     mux port map(s_id_ex_out(81 downto 50), s_mm_frwrd, s_mx_5_out_a,
+                          s_selb_frwrd, s_frwrd_b);
 
-	c_mx_2 :		  mx_2 port map(s_id_ex_out(114), s_frwrd_b, s_id_ex_out(49 downto 18),
+	c_mx_2 :		  mx_2 port map(s_ex_aluSrc, s_frwrd_b, s_id_ex_out(49 downto 18),
                         s_mx_2_out_a);
 	c_ula :			  ula port map(s_alu_inp_a, s_mx_2_out_a, s_id_ex_out(2 downto 0), s_ula_out_a, open);
 	c_mx_1 :		  mx_1 port map(s_id_ex_out(115), s_id_ex_out(12 downto 8), s_id_ex_out(7 downto 3),