diff --git a/Makefile b/Makefile
index 58b02c7fd069198ef386a5a9db1925239ed6a763..8315e3b1dce89b7997615744f2e27d052a6d5cbe 100644
--- a/Makefile
+++ b/Makefile
@@ -1,8 +1,8 @@
all:
ghdl -a --ieee=synopsys -fexplicit *.vhd
ghdl -e --ieee=synopsys -fexplicit tb_main_processor
- ./tb_main_processor --stop-time=600ns --vcd=tb.vcd
-
+ ./tb_main_processor --stop-time=1000ns --vcd=tb.vcd
+
gtk: all
gtkwave tb.vcd
diff --git a/ctrl.vhd b/ctrl.vhd
index 41d0b5ceea809ff0d5ca17b133b7d43d5ce72ab6..bcc15efb008eb53192795f2a1c1810ca972fb3fd 100644
--- a/ctrl.vhd
+++ b/ctrl.vhd
@@ -17,7 +17,7 @@
-- engineer: darci luiz tomasi junior
-- e-mail: dltj007@gmail.com
-- date : 25/06/2015 - 19:35
--- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library ieee;
use ieee.std_logic_1164.all;
@@ -37,69 +37,68 @@ entity ctrl is
end ctrl;
architecture arc_ctrl of ctrl is
-
+
begin
process(opcode)
begin
case opcode is
--type r
- when "000000" => regdst <= '1';
- jump <= '0';
- alusrc <= '0';
- memtoreg <= '0';
- regwrite <= '1';
- memread <= '0';
- memwrite <= '0';
- branch <= '0';
- aluop(1) <= '1';
- aluop(0) <= '0';
- --type lw
- when "100011" => regdst <= '0';
- jump <= '0';
- alusrc <= '1';
- memtoreg <= '1';
- regwrite <= '1';
- memread <= '1';
- memwrite <= '0';
- branch <= '0';
- aluop(1) <= '0';
- aluop(0) <= '0';
- --type sw
- when "101011" => regdst <= '0'; --x
- jump <= '0';
- alusrc <= '1';
- memtoreg <= '0'; --x
- regwrite <= '0';
- memread <= '0';
- memwrite <= '1';
- branch <= '0';
- aluop(1) <= '0';
- aluop(0) <= '0';
+ when "000000" => regdst <= '1';
+ jump <= '0';
+ alusrc <= '0';
+ memtoreg <= '0';
+ regwrite <= '1';
+ memread <= '0';
+ memwrite <= '0';
+ branch <= '0';
+ aluop(1) <= '1';
+ aluop(0) <= '0';
+ --type lw
+ when "100011" => regdst <= '0';
+ jump <= '0';
+ alusrc <= '1';
+ memtoreg <= '1';
+ regwrite <= '1';
+ memread <= '1';
+ memwrite <= '0';
+ branch <= '0';
+ aluop(1) <= '0';
+ aluop(0) <= '0';
+ --type sw
+ when "101011" => regdst <= '0'; --x
+ jump <= '0';
+ alusrc <= '1';
+ memtoreg <= '0'; --x
+ regwrite <= '0';
+ memread <= '0';
+ memwrite <= '1';
+ branch <= '0';
+ aluop(1) <= '0';
+ aluop(0) <= '0';
--type jump
- when "000010" => regdst <= '0'; --x
- jump <= '1';
- alusrc <= '0';
- memtoreg <= '0'; --x
- regwrite <= '0';
- memread <= '0';
- memwrite <= '0';
- branch <= '0';
- aluop(1) <= '1';
- aluop(0) <= '0';
+ when "000010" => regdst <= '0'; --x
+ jump <= '1';
+ alusrc <= '0';
+ memtoreg <= '0'; --x
+ regwrite <= '0';
+ memread <= '0';
+ memwrite <= '0';
+ branch <= '0';
+ aluop(1) <= '1';
+ aluop(0) <= '0';
--type beq
- when others => regdst <= '0'; --x
- jump <= '0';
- alusrc <= '0';
- memtoreg <= '0'; --x
- regwrite <= '0';
- memread <= '0';
- memwrite <= '0';
- branch <= '1';
- aluop(1) <= '0';
- aluop(0) <= '1';
-
+ when others => regdst <= '0'; --x
+ jump <= '0';
+ alusrc <= '0';
+ memtoreg <= '0'; --x
+ regwrite <= '0';
+ memread <= '0';
+ memwrite <= '0';
+ branch <= '1';
+ aluop(1) <= '0';
+ aluop(0) <= '1';
+
end case;
end process;
end arc_ctrl;
-
diff --git a/hazard.vhd b/hazard.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8703ec9471c57d398c82601ba8785473e94960c6
--- /dev/null
+++ b/hazard.vhd
@@ -0,0 +1,31 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity hazard is
+ port(
+ id_opcode : in std_logic_vector(5 downto 0);
+ if_rs : in std_logic_vector(4 downto 0);
+ if_rt : in std_logic_vector(4 downto 0);
+ id_rt : in std_logic_vector(4 downto 0);
+ flush : out std_logic
+ );
+end hazard;
+
+architecture arc_hazard of hazard is
+begin
+ process(id_opcode, if_rt, if_rs, id_rt)
+ begin
+ -- id instruction is lw
+ if (id_opcode = "100011") then
+ -- id instruction changes if_rs or if_rt
+ if (if_rs = id_rt) or (if_rt = id_rt) then
+ flush <= '1';
+ else
+ flush <= '0';
+ end if;
+ else
+ flush <= '0';
+ end if;
+ end process;
+end architecture arc_hazard;
diff --git a/inst.vhd b/inst.vhd
index c001b4d85bdd598d04da3dedcdc26c763a1ab1f4..0d65edab55b16b48761626b71b2f78765ac42562 100644
--- a/inst.vhd
+++ b/inst.vhd
@@ -17,7 +17,7 @@
-- engineer: darci luiz tomasi junior
-- e-mail: dltj007@gmail.com
-- date : 01/07/2015 - 19:14
--- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
@@ -33,8 +33,8 @@ end inst;
architecture arc_inst of inst is
--deve ser 0 to 255 o array para facilitar a leitura do programa em ordem crescente
type memory is array (0 to 255) of std_logic_vector(31 downto 0);
- signal program : memory := ( x"118d0004", x"ac890000" ,x"012c4820",x"01886020",
- x"08100000",x"ac890000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
+ signal program : memory := ( x"118d0005", x"012c4820" ,x"ac890000",x"01886020",
+ x"08100000",x"ac880000",x"ac890000",x"8c890000",x"ac890000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
@@ -73,6 +73,5 @@ architecture arc_inst of inst is
begin
--o fator - x"00400000" devido ao incio das instrues no software mars
out_a <= program(to_integer((unsigned(in_a) - x"00400000") srl 2));
-
-end arc_inst;
+end arc_inst;
diff --git a/main_cttrl.vhd b/main_cttrl.vhd
index 670119e7a86e86761df171259220ef1064f32423..75fbda2fd14f1c945048feca2faad59aa2cd85f7 100644
--- a/main_cttrl.vhd
+++ b/main_cttrl.vhd
@@ -16,269 +16,280 @@
--
-- engineer: darci luiz tomasi junior
-- e-mail: dltj007@gmail.com
--- date : 01/07/2015 - 22:08
+-- date : 01/07/2015 - 22:08
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity main_processor is
- port(
- clk : in std_logic;
- reset : in std_logic
- );
+port(
+ clk : in std_logic;
+ reset : in std_logic
+);
end main_processor;
architecture arc_main_processor of main_processor is
- component add_pc is
- port(
- in_a : in std_logic_vector(31 downto 0);
- out_a : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component add is
- port(
- in_a : in std_logic_vector(31 downto 0);
- in_b : in std_logic_vector(31 downto 0);
- out_a : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component and_1 is
- port(
- branch : in std_logic;
- in_a : in std_logic;
- out_a : out std_logic
- );
- end component;
-
- component concat is
- port(
- in_a : in std_logic_vector(31 downto 0);
- in_b : in std_logic_vector(31 downto 0);
- out_a : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component compare is
- port(
- inp_a: in std_logic_vector(31 downto 0);
- inp_b: in std_logic_vector(31 downto 0);
- outp: out std_logic
- );
- end component;
-
- component ctrl is
- port(
- opcode : in std_logic_vector(5 downto 0);
- regdst : out std_logic;
- jump : out std_logic;
- branch : out std_logic;
- memread : out std_logic;
- memtoreg : out std_logic;
- aluop : out std_logic_vector(1 downto 0);
- memwrite : out std_logic;
- alusrc : out std_logic;
- regwrite : out std_logic
- );
- end component;
-
- component extend_signal is
- port(
- in_a : in std_logic_vector (15 downto 0);
- out_a : out std_logic_vector (31 downto 0)
- );
- end component;
-
- component inst is
- port(
- in_a : in std_logic_vector(31 downto 0);
- out_a : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component forward is
- port(
- reset : in std_logic;
- rs : in std_logic_vector(4 downto 0);
- rt : in std_logic_vector(4 downto 0);
- writeMm: in std_logic;
- rd_mm : in std_logic_vector(4 downto 0);
- writeWb: in std_logic;
- rd_wb : in std_logic_vector(4 downto 0);
- sela : out std_logic_vector(1 downto 0);
- selb : out std_logic_vector(1 downto 0)
- );
- end component;
-
- component mem is
- port(
- clk : in std_logic;
- reset : in std_logic;
- memwrite : in std_logic;
- memread : in std_logic;
- in_a : in std_logic_vector(31 downto 0);
- in_b : in std_logic_vector(31 downto 0);
- out_a : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component mux is
- port(
- in_a : in std_logic_vector(31 downto 0);
- in_b : in std_logic_vector(31 downto 0);
- in_c : in std_logic_vector(31 downto 0);
- sel : in std_logic_vector(1 downto 0);
- out_a : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component mux2 is
- port(
- in_a : in std_logic_vector(31 downto 0);
- in_b : in std_logic_vector(31 downto 0);
- sel : in std_logic;
- out_a : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component mx_1 is
- port(
- regdst : in std_logic;
- in_a : in std_logic_vector(4 downto 0);
- in_b : in std_logic_vector(4 downto 0);
- out_a : out std_logic_vector(4 downto 0)
- );
- end component;
-
- component mx_2 is
- port(
- alusrc : in std_logic;
- in_a : in std_logic_vector(31 downto 0);
- in_b : in std_logic_vector(31 downto 0);
- out_a : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component mx_3 is
- port(
- in_a : in std_logic_vector(31 downto 0);
- in_b : in std_logic_vector(31 downto 0);
- in_c : in std_logic;
- out_a : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component mx_4 is
- port(
- jump : in std_logic;
- in_a : in std_logic_vector(31 downto 0);
- in_b : in std_logic_vector(31 downto 0);
- out_a : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component mx_5 is
- port(
- memtoreg : in std_logic;
- in_a : in std_logic_vector(31 downto 0);
- in_b : in std_logic_vector(31 downto 0);
- out_a : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component pc is
- port(
- clk : in std_logic;
- reset : in std_logic;
- in_a : in std_logic_vector(31 downto 0);
- out_a : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component reg is
- port(
- clk : in std_logic;
- reset : in std_logic;
- regwrite : in std_logic;
- in_a : in std_logic_vector(4 downto 0);
- in_b : in std_logic_vector(4 downto 0);
- in_c : in std_logic_vector(4 downto 0);
- in_d : in std_logic_vector(31 downto 0);
- out_a : out std_logic_vector(31 downto 0);
- out_b : out std_logic_vector(31 downto 0)
- );
- end component;
-
- component reg128 is
- port(
- clk: in std_logic;
- rst: in std_logic;
- inp: in std_logic_vector(127 downto 0);
- outp: out std_logic_vector(127 downto 0)
- );
- end component;
-
- component reg64 is
- port(
- clk: in std_logic;
- rst: in std_logic;
- inp: in std_logic_vector(63 downto 0);
- outp: out std_logic_vector(63 downto 0)
- );
- end component;
-
- component sl_1 is
- port(
- in_a : in std_logic_vector (31 downto 0);
- out_a : out std_logic_vector (31 downto 0)
- );
- end component;
-
- component sl_2 is
- port(
- in_a : in std_logic_vector (31 downto 0);
- out_a : out std_logic_vector (31 downto 0)
- );
- end component;
-
- component ula_ctrl is
- port (
- aluop : in std_logic_vector (1 downto 0);
- in_a : in std_logic_vector (5 downto 0);
- out_a : out std_logic_vector (2 downto 0)
- );
- end component;
-
- component ula is
- port(
- in_a : in std_logic_vector (31 downto 0); --rs
- in_b : in std_logic_vector (31 downto 0); --rt
- in_c : in std_logic_vector (2 downto 0);
- out_a : out std_logic_vector (31 downto 0);
- zero : out std_logic
- );
- end component;
-
+component add_pc is
+ port(
+ in_a : in std_logic_vector(31 downto 0);
+ out_a : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+component add is
+ port(
+ in_a : in std_logic_vector(31 downto 0);
+ in_b : in std_logic_vector(31 downto 0);
+ out_a : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+component and_1 is
+ port(
+ branch : in std_logic;
+ in_a : in std_logic;
+ out_a : out std_logic
+ );
+end component;
+
+component concat is
+ port(
+ in_a : in std_logic_vector(31 downto 0);
+ in_b : in std_logic_vector(31 downto 0);
+ out_a : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+ component compare is
+ port(
+ inp_a: in std_logic_vector(31 downto 0);
+ inp_b: in std_logic_vector(31 downto 0);
+ outp: out std_logic
+ );
+ end component;
+
+component ctrl is
+ port(
+ opcode : in std_logic_vector(5 downto 0);
+ regdst : out std_logic;
+ jump : out std_logic;
+ branch : out std_logic;
+ memread : out std_logic;
+ memtoreg : out std_logic;
+ aluop : out std_logic_vector(1 downto 0);
+ memwrite : out std_logic;
+ alusrc : out std_logic;
+ regwrite : out std_logic
+ );
+end component;
+
+component extend_signal is
+ port(
+ in_a : in std_logic_vector (15 downto 0);
+ out_a : out std_logic_vector (31 downto 0)
+ );
+end component;
+
+component inst is
+ port(
+ in_a : in std_logic_vector(31 downto 0);
+ out_a : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+component forward is
+ port(
+ reset : in std_logic;
+ rs : in std_logic_vector(4 downto 0);
+ rt : in std_logic_vector(4 downto 0);
+ writeMm: in std_logic;
+ rd_mm : in std_logic_vector(4 downto 0);
+ writeWb: in std_logic;
+ rd_wb : in std_logic_vector(4 downto 0);
+ sela : out std_logic_vector(1 downto 0);
+ selb : out std_logic_vector(1 downto 0)
+ );
+end component;
+
+component hazard is
+ port(
+ id_opcode : in std_logic_vector(5 downto 0);
+ if_rs : in std_logic_vector(4 downto 0);
+ if_rt : in std_logic_vector(4 downto 0);
+ id_rt : in std_logic_vector(4 downto 0);
+ flush : out std_logic
+ );
+end component;
+
+component mem is
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ memwrite : in std_logic;
+ memread : in std_logic;
+ in_a : in std_logic_vector(31 downto 0);
+ in_b : in std_logic_vector(31 downto 0);
+ out_a : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+component mux3 is
+ port(
+ in_a : in std_logic_vector(31 downto 0);
+ in_b : in std_logic_vector(31 downto 0);
+ in_c : in std_logic_vector(31 downto 0);
+ sel : in std_logic_vector(1 downto 0);
+ out_a : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+component mux2 is
+ port(
+ in_a : in std_logic_vector(31 downto 0);
+ in_b : in std_logic_vector(31 downto 0);
+ sel : in std_logic;
+ out_a : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+component mx_1 is
+ port(
+ regdst : in std_logic;
+ in_a : in std_logic_vector(4 downto 0);
+ in_b : in std_logic_vector(4 downto 0);
+ out_a : out std_logic_vector(4 downto 0)
+ );
+end component;
+
+component mx_2 is
+ port(
+ alusrc : in std_logic;
+ in_a : in std_logic_vector(31 downto 0);
+ in_b : in std_logic_vector(31 downto 0);
+ out_a : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+component mx_3 is
+ port(
+ in_a : in std_logic_vector(31 downto 0);
+ in_b : in std_logic_vector(31 downto 0);
+ in_c : in std_logic;
+ out_a : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+component mx_4 is
+ port(
+ jump : in std_logic;
+ in_a : in std_logic_vector(31 downto 0);
+ in_b : in std_logic_vector(31 downto 0);
+ out_a : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+component mx_5 is
+ port(
+ memtoreg : in std_logic;
+ in_a : in std_logic_vector(31 downto 0);
+ in_b : in std_logic_vector(31 downto 0);
+ out_a : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+component pc is
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ pc_write : in std_logic;
+ in_a : in std_logic_vector(31 downto 0);
+ out_a : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+component reg is
+ port(
+ clk : in std_logic;
+ reset : in std_logic;
+ regwrite : in std_logic;
+ in_a : in std_logic_vector(4 downto 0);
+ in_b : in std_logic_vector(4 downto 0);
+ in_c : in std_logic_vector(4 downto 0);
+ in_d : in std_logic_vector(31 downto 0);
+ out_a : out std_logic_vector(31 downto 0);
+ out_b : out std_logic_vector(31 downto 0)
+ );
+end component;
+
+component reg128 is
+ port(
+ clk: in std_logic;
+ rst: in std_logic;
+ inp: in std_logic_vector(127 downto 0);
+ outp: out std_logic_vector(127 downto 0)
+ );
+end component;
+
+component reg64 is
+ port(
+ clk: in std_logic;
+ rst: in std_logic;
+ inp: in std_logic_vector(63 downto 0);
+ outp: out std_logic_vector(63 downto 0)
+ );
+end component;
+
+component sl_1 is
+ port(
+ in_a : in std_logic_vector (31 downto 0);
+ out_a : out std_logic_vector (31 downto 0)
+ );
+end component;
+
+component sl_2 is
+ port(
+ in_a : in std_logic_vector (31 downto 0);
+ out_a : out std_logic_vector (31 downto 0)
+ );
+end component;
+
+component ula_ctrl is
+ port (
+ aluop : in std_logic_vector (1 downto 0);
+ in_a : in std_logic_vector (5 downto 0);
+ out_a : out std_logic_vector (2 downto 0)
+ );
+end component;
+
+component ula is
+ port(
+ in_a : in std_logic_vector (31 downto 0); --rs
+ in_b : in std_logic_vector (31 downto 0); --rt
+ in_c : in std_logic_vector (2 downto 0);
+ out_a : out std_logic_vector (31 downto 0);
+ zero : out std_logic
+ );
+end component;
+
--add_pc
signal s_add_pc_out_a : std_logic_vector(31 downto 0);
signal s_mx_pc_out_a : std_logic_vector(31 downto 0);
signal s_sel_mux_pc : std_logic;
-
+
--add
signal s_add_out_a : std_logic_vector(31 downto 0);
-
+
--and_1
signal s_and_1_out_a : std_logic;
-
+
--concat
signal s_concat_out_a : std_logic_vector(31 downto 0);
-
+
--ctrl
- signal s_ctrl_regdst : std_logic;
- signal s_ctrl_jump : std_logic;
+ signal s_ctrl_regdst : std_logic;
+ signal s_ctrl_jump : std_logic;
signal s_ctrl_branch : std_logic;
signal s_ctrl_memread : std_logic;
signal s_ctrl_memtoreg : std_logic;
@@ -287,81 +298,85 @@ architecture arc_main_processor of main_processor is
signal s_ctrl_alusrc : std_logic;
signal s_ctrl_regwrite : std_logic;
- -- cmp
+ -- cmp
signal s_cmp_zero : std_logic;
- -- forward
- signal s_sela_frwrd : std_logic_vector(1 downto 0);
- signal s_selb_frwrd : std_logic_vector(1 downto 0);
- signal s_rs_ex : std_logic_vector(4 downto 0);
- signal s_rt_ex : std_logic_vector(4 downto 0);
- signal s_rd_mm : std_logic_vector(4 downto 0);
- signal s_rd_wb : std_logic_vector(4 downto 0);
- signal s_wrtMm : std_logic;
- signal s_wrtWb : std_logic;
- signal s_ex_aluSrc: std_logic;
- signal s_frwrd_b: std_logic_vector(31 downto 0);
- signal s_mm_frwrd: std_logic_vector(31 downto 0);
+ -- forward
+ signal s_sela_frwrd : std_logic_vector(1 downto 0);
+ signal s_selb_frwrd : std_logic_vector(1 downto 0);
+ signal s_rs_ex : std_logic_vector(4 downto 0);
+ signal s_rt_ex : std_logic_vector(4 downto 0);
+ signal s_rd_mm : std_logic_vector(4 downto 0);
+ signal s_rd_wb : std_logic_vector(4 downto 0);
+ signal s_wrtMm : std_logic;
+ signal s_wrtWb : std_logic;
+ signal s_ex_aluSrc: std_logic;
+ signal s_frwrd_b: std_logic_vector(31 downto 0);
+ signal s_mm_frwrd: std_logic_vector(31 downto 0);
--inst
signal s_inst_out_a : std_logic_vector(31 downto 0);
-
+ signal s_mux_flush_in_b : std_logic_vector(31 downto 0);
+ signal s_mux_flush_sel : std_logic;
+ signal s_mux_flush_out : std_logic_vector(31 downto 0);
+
--extend_signal
signal s_extend_signal_out_a :std_logic_vector (31 downto 0);
-
+
--mem
signal s_mem_out_a : std_logic_vector(31 downto 0);
-
+
--mx_1
signal s_mx_1_out_a : std_logic_vector(4 downto 0);
-
+
--mx_2
signal s_mx_2_out_a : std_logic_vector(31 downto 0);
-
+
--mx_3
signal s_mx_3_out_a : std_logic_vector(31 downto 0);
-
+
--mx_4
signal s_mx_4_out_a : std_logic_vector(31 downto 0);
-
+
--mx_5
signal s_mx_5_out_a : std_logic_vector(31 downto 0);
-
+
--pc
signal s_pc_out_a : std_logic_vector(31 downto 0);
-
+ signal s_pc_write : std_logic;
+
--reg
signal s_reg_out_a : std_logic_vector(31 downto 0);
signal s_reg_out_b : std_logic_vector(31 downto 0);
-
- -- pipeline registers
- signal s_if_id_in : std_logic_vector(63 downto 0);
- signal s_if_id_out : std_logic_vector(63 downto 0);
- signal s_id_ex_in : std_logic_vector(127 downto 0);
- signal s_id_ex_out : std_logic_vector(127 downto 0);
- signal s_ex_mm_in : std_logic_vector(127 downto 0);
- signal s_ex_mm_out : std_logic_vector(127 downto 0);
- signal s_mm_wb_in : std_logic_vector(127 downto 0);
- signal s_mm_wb_out : std_logic_vector(127 downto 0);
+
+ -- pipeline registers
+ signal s_if_id_in : std_logic_vector(63 downto 0);
+ signal s_if_id_out : std_logic_vector(63 downto 0);
+ signal s_id_ex_in : std_logic_vector(127 downto 0);
+ signal s_id_ex_out : std_logic_vector(127 downto 0);
+ signal s_ex_mm_in : std_logic_vector(127 downto 0);
+ signal s_ex_mm_out : std_logic_vector(127 downto 0);
+ signal s_mm_wb_in : std_logic_vector(127 downto 0);
+ signal s_mm_wb_out : std_logic_vector(127 downto 0);
--sl_1
signal s_sl_1_out_a : std_logic_vector (31 downto 0);
-
+
--sl_2
signal s_sl_2_out_a : std_logic_vector (31 downto 0);
-
+
--ula_ctrl
signal s_ula_ctrl_out_a : std_logic_vector (2 downto 0);
-
+
--ula
signal s_alu_inp_a : std_logic_vector (31 downto 0);
signal s_ula_out_a : std_logic_vector (31 downto 0);
--demais sinais
signal s_geral_opcode : std_logic_vector(5 downto 0);
- signal s_geral_rs : std_logic_vector(4 downto 0);
- signal s_geral_rt : std_logic_vector(4 downto 0);
- signal s_geral_rd : std_logic_vector(4 downto 0);
+ signal s_geral_rs : std_logic_vector(4 downto 0);
+ signal s_geral_rt : std_logic_vector(4 downto 0);
+ signal s_geral_rd : std_logic_vector(4 downto 0);
signal s_geral_i_type : std_logic_vector(15 downto 0);
signal s_geral_funct : std_logic_vector(5 downto 0);
signal s_geral_jump : std_logic_vector(31 downto 0);
@@ -369,20 +384,26 @@ architecture arc_main_processor of main_processor is
begin
- s_sel_mux_pc <= s_ctrl_jump or s_and_1_out_a;
- c_mux2 : mux2 port map(s_add_pc_out_a, s_mx_4_out_a, s_sel_mux_pc,
- s_mx_pc_out_a);
- c_pc : pc port map(clk, reset, s_mx_pc_out_a, s_pc_out_a);
+ s_sel_mux_pc <= s_ctrl_jump or s_and_1_out_a;
+ -- intruction in next stage is lw and rd is rs or rt in this one
+ c_data_hazard: hazard port map(s_geral_opcode,s_inst_out_a(25 downto 21),
+ s_inst_out_a(20 downto 16), s_geral_rt, s_mux_flush_sel);
+ s_pc_write <= not s_mux_flush_sel;
+ c_mux2 : mux2 port map(s_add_pc_out_a, s_mx_4_out_a, s_sel_mux_pc,
+ s_mx_pc_out_a);
+ c_pc : pc port map(clk, reset, s_pc_write, s_mx_pc_out_a, s_pc_out_a);
c_add_pc : add_pc port map(s_pc_out_a, s_add_pc_out_a);
c_inst : inst port map(s_pc_out_a, s_inst_out_a);
-
- -- IF/ID
- -- |63 32 | 31 0|
- s_if_id_in <= s_add_pc_out_a(31 downto 0) & s_inst_out_a(31 downto 0);
- c_if_id : reg64 port map(clk, reset, s_if_id_in, s_if_id_out);
- -- s_add_pc_out é a parte mais significativa do registrador
+ c_mux_flush : mux2 port map(s_inst_out_a, x"00000000", s_mux_flush_sel,
+ s_mux_flush_out);
+
+ -- IF/ID
+ -- |63 32 | 31 0|
+ s_if_id_in <= s_add_pc_out_a(31 downto 0) & s_mux_flush_out(31 downto 0);
+ c_if_id : reg64 port map(clk, reset, s_if_id_in, s_if_id_out);
+ -- s_add_pc_out é a parte mais significativa do registrador
s_geral_pc_4 <= s_if_id_out(63 downto 32);
- -- s_inst_out_a é a menos significativa deste registrador
+ -- s_inst_out_a é a menos significativa deste registrador
s_geral_opcode <= s_if_id_out(31 downto 26);
s_geral_rs <= s_if_id_out(25 downto 21);
s_geral_rt <= s_if_id_out(20 downto 16);
@@ -391,75 +412,74 @@ begin
s_geral_funct <= s_if_id_out(5 downto 0);
s_geral_jump <= s_if_id_out(31 downto 0);
- c_sl_1 : sl_1 port map(s_geral_jump, s_sl_1_out_a);
- c_ctrl : ctrl port map(s_geral_opcode, s_ctrl_regdst, s_ctrl_jump, s_ctrl_branch,
- s_ctrl_memread, s_ctrl_memtoreg, s_ctrl_aluop, s_ctrl_memwrite,
- s_ctrl_alusrc, s_ctrl_regwrite);
- c_concat : concat port map(s_sl_1_out_a, s_geral_pc_4, s_concat_out_a);
- c_sl_2 : sl_2 port map(s_extend_signal_out_a, s_sl_2_out_a);
- c_reg : reg port map(clk, reset, s_mm_wb_out(70), s_geral_rs, s_geral_rt,
- s_mm_wb_out(4 downto 0), s_mx_5_out_a, s_reg_out_a, s_reg_out_b);
- c_extend_signal : extend_signal port map(s_geral_i_type, s_extend_signal_out_a);
- c_add : add port map(s_geral_pc_4, s_sl_2_out_a, s_add_out_a);
- c_cmp: compare port map (s_reg_out_a, s_reg_out_b, s_cmp_zero);
- c_ula_ctrl : ula_ctrl port map(s_ctrl_aluop, s_geral_funct, s_ula_ctrl_out_a);
- c_mx_3 : mx_3 port map(s_geral_pc_4, s_add_out_a, s_and_1_out_a, s_mx_3_out_a);
- c_and_1 : and_1 port map(s_ctrl_branch, s_cmp_zero, s_and_1_out_a);
- c_mx_4 : mx_4 port map(s_ctrl_jump, s_concat_out_a, s_mx_3_out_a, s_mx_4_out_a);
-
- -- ID/EX 41 zeros to put the input in the least sign & control & reg_out_a & reg_out_b &
- -- inp_alu_b & rs & rt & rd & alu_control
- -- |127-0| 119 | 118 | 117 | 116
- s_id_ex_in <= x"00" & s_ctrl_regwrite & s_ctrl_memtoreg & s_ctrl_memwrite & s_ctrl_memread
- -- | 115 | 114 | 113 82 | 81 50 | 49 18
- & s_ctrl_regdst & s_ctrl_alusrc & s_reg_out_a & s_reg_out_b & s_extend_signal_out_a
- -- | 17 13 | 12 8 | 7 3 | 2 0|
- & s_geral_rs & s_geral_rt & s_geral_rd & s_ula_ctrl_out_a;
- c_id_ex : reg128 port map(clk, reset, s_id_ex_in, s_id_ex_out);
-
- -- forwarding unity
- s_rs_ex <= s_id_ex_out(17 downto 13);
- s_rt_ex <= s_id_ex_out(12 downto 8);
- s_rd_mm <= s_ex_mm_out(4 downto 0);
- s_rd_wb <= s_mm_wb_out(4 downto 0);
- s_wrtMm <= s_ex_mm_out(72);
- s_wrtWb <= s_mm_wb_out(70);
- s_mm_frwrd <= s_ex_mm_out(68 downto 37);
- s_ex_aluSrc <= s_id_ex_out(114);
- c_forward: forward port map(reset, s_rs_ex, s_rt_ex, s_wrtMm, s_rd_mm,
- s_wrtWb, s_rd_wb, s_sela_frwrd, s_selb_frwrd);
-
- -- reg_out_a ula_out_ant
- c_mux_fwrd_a: mux port map(s_id_ex_out(113 downto 82), s_mm_frwrd, s_mx_5_out_a,
- s_sela_frwrd, s_alu_inp_a);
- -- reg_out_b ula_out_ant
- c_mux_fwrd_b: mux port map(s_id_ex_out(81 downto 50), s_mm_frwrd, s_mx_5_out_a,
- s_selb_frwrd, s_frwrd_b);
-
- c_mx_2 : mx_2 port map(s_ex_aluSrc, s_frwrd_b, s_id_ex_out(49 downto 18),
- s_mx_2_out_a);
- c_ula : ula port map(s_alu_inp_a, s_mx_2_out_a, s_id_ex_out(2 downto 0), s_ula_out_a, open);
- c_mx_1 : mx_1 port map(s_id_ex_out(115), s_id_ex_out(12 downto 8), s_id_ex_out(7 downto 3),
- s_mx_1_out_a);
-
- -- EX/MM 56 zeros & control & alu_out & inp_alu_b & reg_dst
- -- |127 73 | 72 69 | 68 37 | 36 5
- s_ex_mm_in <= x"0000000000000"& "000" & s_id_ex_out(119 downto 116) & s_ula_out_a & s_id_ex_out(81 downto 50)
- -- | 4 0|
- & s_mx_1_out_a;
- c_ex_mm : reg128 port map(clk, reset, s_ex_mm_in, s_ex_mm_out);
-
- c_mem : mem port map(clk, reset, s_ex_mm_out(70), s_ex_mm_out(69), s_ex_mm_out(68 downto 37),
- s_ex_mm_out(36 downto 5), s_mem_out_a);
-
- -- MM/WB
- -- |127 71 | 70 69 | 68 37 | 36 5
- s_mm_wb_in <= x"00000000000000" & '0' & s_ex_mm_out(72 downto 71) & s_mem_out_a & s_ex_mm_out(68 downto 37)
- -- | 4 0|
- & s_ex_mm_out(4 downto 0);
- c_mm_wb : reg128 port map(clk, reset, s_mm_wb_in, s_mm_wb_out);
-
- c_mx_5 : mx_5 port map(s_mm_wb_out(69), s_mm_wb_out(68 downto 37), s_mm_wb_out(36 downto 5), s_mx_5_out_a);
-
-end arc_main_processor;
+ c_sl_1 : sl_1 port map(s_geral_jump, s_sl_1_out_a);
+ c_ctrl : ctrl port map(s_geral_opcode, s_ctrl_regdst, s_ctrl_jump, s_ctrl_branch,
+ s_ctrl_memread, s_ctrl_memtoreg, s_ctrl_aluop, s_ctrl_memwrite,
+ s_ctrl_alusrc, s_ctrl_regwrite);
+ c_concat : concat port map(s_sl_1_out_a, s_geral_pc_4, s_concat_out_a);
+ c_sl_2 : sl_2 port map(s_extend_signal_out_a, s_sl_2_out_a);
+ c_reg : reg port map(clk, reset, s_mm_wb_out(70), s_geral_rs, s_geral_rt,
+ s_mm_wb_out(4 downto 0), s_mx_5_out_a, s_reg_out_a, s_reg_out_b);
+ c_extend_signal : extend_signal port map(s_geral_i_type, s_extend_signal_out_a);
+ c_add : add port map(s_geral_pc_4, s_sl_2_out_a, s_add_out_a);
+ c_cmp: compare port map (s_reg_out_a, s_reg_out_b, s_cmp_zero);
+ c_ula_ctrl : ula_ctrl port map(s_ctrl_aluop, s_geral_funct, s_ula_ctrl_out_a);
+ c_mx_3 : mx_3 port map(s_geral_pc_4, s_add_out_a, s_and_1_out_a, s_mx_3_out_a);
+ c_and_1 : and_1 port map(s_ctrl_branch, s_cmp_zero, s_and_1_out_a);
+ c_mx_4 : mx_4 port map(s_ctrl_jump, s_concat_out_a, s_mx_3_out_a, s_mx_4_out_a);
+
+ -- ID/EX 41 zeros to put the input in the least sign & control & reg_out_a & reg_out_b &
+ -- inp_alu_b & rs & rt & rd & alu_control
+ -- |127-0| 119 | 118 | 117 | 116
+ s_id_ex_in <= x"00" & s_ctrl_regwrite & s_ctrl_memtoreg & s_ctrl_memwrite & s_ctrl_memread
+ -- | 115 | 114 | 113 82 | 81 50 | 49 18
+ & s_ctrl_regdst & s_ctrl_alusrc & s_reg_out_a & s_reg_out_b & s_extend_signal_out_a
+ -- | 17 13 | 12 8 | 7 3 | 2 0|
+ & s_geral_rs & s_geral_rt & s_geral_rd & s_ula_ctrl_out_a;
+ c_id_ex : reg128 port map(clk, reset, s_id_ex_in, s_id_ex_out);
+
+ -- forwarding unity
+ s_rs_ex <= s_id_ex_out(17 downto 13);
+ s_rt_ex <= s_id_ex_out(12 downto 8);
+ s_rd_mm <= s_ex_mm_out(4 downto 0);
+ s_rd_wb <= s_mm_wb_out(4 downto 0);
+ s_wrtMm <= s_ex_mm_out(72);
+ s_wrtWb <= s_mm_wb_out(70);
+ s_mm_frwrd <= s_ex_mm_out(68 downto 37);
+ s_ex_aluSrc <= s_id_ex_out(114);
+ c_forward: forward port map(reset, s_rs_ex, s_rt_ex, s_wrtMm, s_rd_mm,
+ s_wrtWb, s_rd_wb, s_sela_frwrd, s_selb_frwrd);
+
+ -- reg_out_a ula_out_ant
+ c_mux_fwrd_a: mux3 port map(s_id_ex_out(113 downto 82), s_mm_frwrd, s_mx_5_out_a,
+ s_sela_frwrd, s_alu_inp_a);
+ -- reg_out_b ula_out_ant
+ c_mux_fwrd_b: mux3 port map(s_id_ex_out(81 downto 50), s_mm_frwrd, s_mx_5_out_a,
+ s_selb_frwrd, s_frwrd_b);
+ c_mx_2 : mx_2 port map(s_ex_aluSrc, s_frwrd_b, s_id_ex_out(49 downto 18),
+ s_mx_2_out_a);
+ c_ula : ula port map(s_alu_inp_a, s_mx_2_out_a, s_id_ex_out(2 downto 0), s_ula_out_a, open);
+ c_mx_1 : mx_1 port map(s_id_ex_out(115), s_id_ex_out(12 downto 8), s_id_ex_out(7 downto 3),
+ s_mx_1_out_a);
+
+ -- EX/MM 56 zeros & control & alu_out & inp_alu_b & reg_dst
+ -- |127 73 | 72 69 | 68 37 | 36 5
+ s_ex_mm_in <= x"0000000000000"& "000" & s_id_ex_out(119 downto 116) & s_ula_out_a & s_id_ex_out(81 downto 50)
+ -- | 4 0|
+ & s_mx_1_out_a;
+ c_ex_mm : reg128 port map(clk, reset, s_ex_mm_in, s_ex_mm_out);
+
+ c_mem : mem port map(clk, reset, s_ex_mm_out(70), s_ex_mm_out(69), s_ex_mm_out(68 downto 37),
+ s_ex_mm_out(36 downto 5), s_mem_out_a);
+
+ -- MM/WB
+ -- |127 71 | 70 69 | 68 37 | 36 5
+ s_mm_wb_in <= x"00000000000000" & '0' & s_ex_mm_out(72 downto 71) & s_mem_out_a & s_ex_mm_out(68 downto 37)
+ -- | 4 0|
+ & s_ex_mm_out(4 downto 0);
+ c_mm_wb : reg128 port map(clk, reset, s_mm_wb_in, s_mm_wb_out);
+
+ c_mx_5 : mx_5 port map(s_mm_wb_out(69), s_mm_wb_out(68 downto 37), s_mm_wb_out(36 downto 5), s_mx_5_out_a);
+
+end arc_main_processor;
diff --git a/mux.vhd b/mux3.vhd
similarity index 92%
rename from mux.vhd
rename to mux3.vhd
index dc9499ea52054558282f467cffabdd18820593ea..b36ce307869a8432c4725802668489eaa7a3a323 100644
--- a/mux.vhd
+++ b/mux3.vhd
@@ -17,11 +17,11 @@
-- engineer: darci luiz tomasi junior
-- e-mail: dltj007@gmail.com
-- date : 08/07/2015 - 19:11
--- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library ieee;
use ieee.std_logic_1164.all;
-entity mux is
+entity mux3 is
port(
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0);
@@ -29,14 +29,14 @@ entity mux is
sel : in std_logic_vector(1 downto 0);
out_a : out std_logic_vector(31 downto 0)
);
-end mux;
+end mux3;
-architecture arc_mux of mux is
+architecture arc_mux3 of mux3 is
begin
process(sel, in_a, in_b, in_c)
begin
- if sel = "00" then
+ if sel = "00" then
out_a <= in_a;
elsif sel = "01" then
out_a <= in_b;
@@ -44,5 +44,4 @@ begin
out_a <= in_c;
end if;
end process;
-end arc_mux;
-
+end arc_mux3;
diff --git a/pc.vhd b/pc.vhd
index d7f8b4ce8608fede80aa2456f3924e299528ddf8..27b4643d4f127d3db14153f4940c4efb137ee208 100644
--- a/pc.vhd
+++ b/pc.vhd
@@ -16,30 +16,32 @@
--
-- engineer: darci luiz tomasi junior
-- e-mail: dltj007@gmail.com
--- date : 01/07/2015 - 19:53
--- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+-- date : 01/07/2015 - 19:53
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library ieee;
use ieee.std_logic_1164.all;
entity pc is
port(
- clk : in std_logic;
- reset : in std_logic;
- in_a : in std_logic_vector(31 downto 0);
- out_a : out std_logic_vector(31 downto 0)
+ clk : in std_logic;
+ reset : in std_logic;
+ pc_write: in std_logic;
+ in_a : in std_logic_vector(31 downto 0);
+ out_a : out std_logic_vector(31 downto 0)
);
end pc;
architecture arc_pc of pc is
-
+
begin
process(clk, reset)
begin
if reset = '1' then
out_a <= x"00400000"; --para utilizar com o mars
elsif clk'event and clk = '1' then
- out_a <= in_a;
+ if pc_write = '1' then
+ out_a <= in_a;
+ end if;
end if;
end process;
end arc_pc;
-
diff --git a/sum.asm b/sum.asm
index 60b1377932f744d1b05ee30a17b347eca8c9af94..f2209a731ec7730f3c3425cc751b64301e8ff225 100644
--- a/sum.asm
+++ b/sum.asm
@@ -9,12 +9,16 @@
# li $t5, 6
# la $a0, xffff0000
for: beq $t4,$t5,fimfor
- sw $t1, 0($a0)
# j = j*i;
add $t1, $t1, $t4
+
+ sw $t1, 0($a0)
add $t4, $t4, $t0
j for
+ sw $t0, 0($a0)
-fimfor: sw $t1, 0($a0)
\ No newline at end of file
+fimfor: sw $t1, 0($a0)
+ lw $t1 0($a0)
+ sw $t1 0($a0)
\ No newline at end of file
diff --git a/sum.hex b/sum.hex
index dd8926d769429703f05c839307096b7bb6346ae1..d19e24d854139acc6bc8089c4f04a393891e5a71 100644
--- a/sum.hex
+++ b/sum.hex
@@ -1,6 +1,9 @@
-118d0004
-ac890000
+118d0005
012c4820
+ac890000
01886020
08100000
+ac880000
+ac890000
+8c890000
ac890000