diff --git a/main_cttrl.vhd b/main_cttrl.vhd
index 8864af6d2eb503cbff53331b0bec58788e1fdc36..c5e6a953465cdbf44564388cd34de0b485c602ae 100644
--- a/main_cttrl.vhd
+++ b/main_cttrl.vhd
@@ -24,8 +24,8 @@ use ieee.numeric_std.all;
entity main_processor is
port(
- clk : in std_logic;
- reset : in std_logic
+ clk : in std_logic;
+ reset : in std_logic
);
end main_processor;
@@ -33,32 +33,32 @@ architecture arc_main_processor of main_processor is
component add_pc is
port(
- in_a : in std_logic_vector(31 downto 0);
- out_a : out std_logic_vector(31 downto 0)
+ in_a : in std_logic_vector(31 downto 0);
+ out_a : out std_logic_vector(31 downto 0)
);
end component;
component add is
port(
- in_a : in std_logic_vector(31 downto 0);
- in_b : in std_logic_vector(31 downto 0);
- out_a : out std_logic_vector(31 downto 0)
+ in_a : in std_logic_vector(31 downto 0);
+ in_b : in std_logic_vector(31 downto 0);
+ out_a : out std_logic_vector(31 downto 0)
);
end component;
component and_1 is
port(
- branch : in std_logic;
- in_a : in std_logic;
- out_a : out std_logic
+ branch : in std_logic;
+ in_a : in std_logic;
+ out_a : out std_logic
);
end component;
component concat is
port(
- in_a : in std_logic_vector(31 downto 0);
- in_b : in std_logic_vector(31 downto 0);
- out_a : out std_logic_vector(31 downto 0)
+ in_a : in std_logic_vector(31 downto 0);
+ in_b : in std_logic_vector(31 downto 0);
+ out_a : out std_logic_vector(31 downto 0)
);
end component;
@@ -72,69 +72,69 @@ architecture arc_main_processor of main_processor is
component ctrl is
port(
- opcode : in std_logic_vector(5 downto 0);
- regdst : out std_logic;
- jump : out std_logic;
- branch : out std_logic;
- memread : out std_logic;
- memtoreg : out std_logic;
- aluop : out std_logic_vector(1 downto 0);
- memwrite : out std_logic;
- alusrc : out std_logic;
- regwrite : out std_logic
+ opcode : in std_logic_vector(5 downto 0);
+ regdst : out std_logic;
+ jump : out std_logic;
+ branch : out std_logic;
+ memread : out std_logic;
+ memtoreg : out std_logic;
+ aluop : out std_logic_vector(1 downto 0);
+ memwrite : out std_logic;
+ alusrc : out std_logic;
+ regwrite : out std_logic
);
end component;
component extend_signal is
port(
- in_a : in std_logic_vector (15 downto 0);
- out_a : out std_logic_vector (31 downto 0)
+ in_a : in std_logic_vector (15 downto 0);
+ out_a : out std_logic_vector (31 downto 0)
);
end component;
component inst is
port(
- in_a : in std_logic_vector(31 downto 0);
- out_a : out std_logic_vector(31 downto 0)
+ in_a : in std_logic_vector(31 downto 0);
+ out_a : out std_logic_vector(31 downto 0)
);
end component;
component mem is
port(
- clk : in std_logic;
- reset : in std_logic;
- memwrite : in std_logic;
- memread : in std_logic;
- in_a : in std_logic_vector(31 downto 0);
- in_b : in std_logic_vector(31 downto 0);
- out_a : out std_logic_vector(31 downto 0)
+ clk : in std_logic;
+ reset : in std_logic;
+ memwrite : in std_logic;
+ memread : in std_logic;
+ in_a : in std_logic_vector(31 downto 0);
+ in_b : in std_logic_vector(31 downto 0);
+ out_a : out std_logic_vector(31 downto 0)
);
end component;
component mx_1 is
port(
- regdst : in std_logic;
- in_a : in std_logic_vector(4 downto 0);
- in_b : in std_logic_vector(4 downto 0);
- out_a : out std_logic_vector(4 downto 0)
+ regdst : in std_logic;
+ in_a : in std_logic_vector(4 downto 0);
+ in_b : in std_logic_vector(4 downto 0);
+ out_a : out std_logic_vector(4 downto 0)
);
end component;
component mx_2 is
port(
- alusrc : in std_logic;
- in_a : in std_logic_vector(31 downto 0);
- in_b : in std_logic_vector(31 downto 0);
- out_a : out std_logic_vector(31 downto 0)
+ alusrc : in std_logic;
+ in_a : in std_logic_vector(31 downto 0);
+ in_b : in std_logic_vector(31 downto 0);
+ out_a : out std_logic_vector(31 downto 0)
);
end component;
component mx_3 is
port(
- in_a : in std_logic_vector(31 downto 0);
- in_b : in std_logic_vector(31 downto 0);
- in_c : in std_logic;
- out_a : out std_logic_vector(31 downto 0)
+ in_a : in std_logic_vector(31 downto 0);
+ in_b : in std_logic_vector(31 downto 0);
+ in_c : in std_logic;
+ out_a : out std_logic_vector(31 downto 0)
);
end component;
@@ -178,6 +178,24 @@ architecture arc_main_processor of main_processor is
out_b : out std_logic_vector(31 downto 0)
);
end component;
+
+ component reg128 is
+ port(
+ clk: in std_logic;
+ rst: in std_logic;
+ inp: in std_logic_vector(127 downto 0);
+ outp: out std_logic_vector(127 downto 0)
+ );
+ end component;
+
+ component reg64 is
+ port(
+ clk: in std_logic;
+ rst: in std_logic;
+ inp: in std_logic_vector(63 downto 0);
+ outp: out std_logic_vector(63 downto 0)
+ );
+ end component;
component sl_1 is
port(
@@ -225,7 +243,7 @@ architecture arc_main_processor of main_processor is
--ctrl
signal s_ctrl_regdst : std_logic;
- signal s_ctrl_jump : std_logic;
+ signal s_ctrl_jump : std_logic;
signal s_ctrl_branch : std_logic;
signal s_ctrl_memread : std_logic;
signal s_ctrl_memtoreg : std_logic;
@@ -233,6 +251,9 @@ architecture arc_main_processor of main_processor is
signal s_ctrl_memwrite : std_logic;
signal s_ctrl_alusrc : std_logic;
signal s_ctrl_regwrite : std_logic;
+
+ -- cmp
+ signal s_cmp_zero : std_logic;
--inst
signal s_inst_out_a : std_logic_vector(31 downto 0);
@@ -265,6 +286,16 @@ architecture arc_main_processor of main_processor is
signal s_reg_out_a : std_logic_vector(31 downto 0);
signal s_reg_out_b : std_logic_vector(31 downto 0);
+ -- pipeline registers
+ signal s_if_id_in : std_logic_vector(63 downto 0);
+ signal s_if_id_out : std_logic_vector(63 downto 0);
+ signal s_id_ex_in : std_logic_vector(127 downto 0);
+ signal s_id_ex_out : std_logic_vector(127 downto 0);
+ signal s_ex_mm_in : std_logic_vector(127 downto 0);
+ signal s_ex_mm_out : std_logic_vector(127 downto 0);
+ signal s_mm_wb_in : std_logic_vector(127 downto 0);
+ signal s_mm_wb_out : std_logic_vector(127 downto 0);
+
--sl_1
signal s_sl_1_out_a : std_logic_vector (31 downto 0);
@@ -276,8 +307,7 @@ architecture arc_main_processor of main_processor is
--ula
signal s_ula_out_a : std_logic_vector (31 downto 0);
- signal s_ula_zero : std_logic;
-
+
--demais sinais
signal s_geral_opcode : std_logic_vector(5 downto 0);
signal s_geral_rs : std_logic_vector(4 downto 0);
@@ -289,35 +319,65 @@ architecture arc_main_processor of main_processor is
signal s_geral_pc_4 : std_logic_vector(31 downto 0);
begin
- s_geral_opcode <= s_inst_out_a(31 downto 26);
- s_geral_rs <= s_inst_out_a(25 downto 21);
- s_geral_rt <= s_inst_out_a(20 downto 16);
- s_geral_rd <= s_inst_out_a(15 downto 11);
- s_geral_i_type <= s_inst_out_a(15 downto 0);
- s_geral_funct <= s_inst_out_a(5 downto 0);
- s_geral_jump <= s_inst_out_a(31 downto 0);
- s_geral_pc_4 <= s_add_pc_out_a(31 downto 0);
c_pc : pc port map(clk, reset, s_mx_4_out_a, s_pc_out_a);
c_add_pc : add_pc port map(s_pc_out_a, s_add_pc_out_a);
- c_inst : inst port map(s_pc_out_a, s_inst_out_a);
- c_sl_1 : sl_1 port map(s_geral_jump, s_sl_1_out_a);
- c_ctrl : ctrl port map(s_geral_opcode, s_ctrl_regdst, s_ctrl_jump, s_ctrl_branch, s_ctrl_memread, s_ctrl_memtoreg, s_ctrl_aluop, s_ctrl_memwrite, s_ctrl_alusrc, s_ctrl_regwrite);
+ c_inst : inst port map(s_pc_out_a, s_inst_out_a);
+
+ -- IF/ID
+ s_if_id_in <= s_add_pc_out_a(31 downto 0) & s_inst_out_a(31 downto 0);
+ c_if_id : reg64 port map(clk, reset, s_if_id_in, s_if_id_out);
+ -- s_add_pc_out é a parte mais significativa do registrador
+ s_geral_pc_4 <= s_if_id_out(63 downto 32);
+ -- s_inst_out_a é a menos significativa deste registrador
+ s_geral_opcode <= s_if_id_out(31 downto 26);
+ s_geral_rs <= s_if_id_out(25 downto 21);
+ s_geral_rt <= s_if_id_out(20 downto 16);
+ s_geral_rd <= s_if_id_out(15 downto 11);
+ s_geral_i_type <= s_if_id_out(15 downto 0);
+ s_geral_funct <= s_if_id_out(5 downto 0);
+ s_geral_jump <= s_if_id_out(31 downto 0);
+
+ c_sl_1 : sl_1 port map(s_geral_jump, s_sl_1_out_a);
+ c_ctrl : ctrl port map(s_geral_opcode, s_ctrl_regdst, s_ctrl_jump, s_ctrl_branch, s_ctrl_memread, s_ctrl_memtoreg, s_ctrl_aluop,
+ s_ctrl_memwrite, s_ctrl_alusrc, s_ctrl_regwrite);
c_concat : concat port map(s_sl_1_out_a, s_geral_pc_4, s_concat_out_a);
- c_mx_1 : mx_1 port map(s_ctrl_regdst, s_geral_rt, s_geral_rd, s_mx_1_out_a);
- c_sl_2 : sl_2 port map(s_extend_signal_out_a, s_sl_2_out_a);
- c_reg : reg port map(clk, reset, s_ctrl_regwrite, s_geral_rs, s_geral_rt, s_mx_1_out_a, s_mx_5_out_a, s_reg_out_a, s_reg_out_b);
+ c_sl_2 : sl_2 port map(s_extend_signal_out_a, s_sl_2_out_a);
+ c_reg : reg port map(clk, reset, s_mm_wb_out(70), s_geral_rs, s_geral_rt, s_mm_wb_out(4 downto 0), s_mx_5_out_a, s_reg_out_a,
+ s_reg_out_b);
c_extend_signal : extend_signal port map(s_geral_i_type, s_extend_signal_out_a);
- c_add : add port map(s_add_pc_out_a, s_sl_2_out_a, s_add_out_a);
- c_cmp: compare port map (s_reg_out_a, s_reg_out_b, s_ula_zero);
- c_ula : ula port map(s_reg_out_a, s_mx_2_out_a, s_ula_ctrl_out_a, s_ula_out_a, open);
- c_mx_2 : mx_2 port map(s_ctrl_alusrc, s_reg_out_b, s_extend_signal_out_a, s_mx_2_out_a);
+ c_add : add port map(s_geral_pc_4, s_sl_2_out_a, s_add_out_a);
+ c_cmp: compare port map (s_reg_out_a, s_reg_out_b, s_cmp_zero);
+ c_mx_2 : mx_2 port map(s_ctrl_alusrc, s_reg_out_b, s_extend_signal_out_a, s_mx_2_out_a);
c_ula_ctrl : ula_ctrl port map(s_ctrl_aluop, s_geral_funct, s_ula_ctrl_out_a);
- c_mx_3 : mx_3 port map(s_add_pc_out_a, s_add_out_a, s_and_1_out_a, s_mx_3_out_a);
- c_and_1 : and_1 port map(s_ctrl_branch, s_ula_zero, s_and_1_out_a);
- c_mem : mem port map(clk, reset, s_ctrl_memwrite, s_ctrl_memread, s_ula_out_a, s_reg_out_b, s_mem_out_a);
- c_mx_4 : mx_4 port map(s_ctrl_jump, s_concat_out_a, s_mx_3_out_a, s_mx_4_out_a);
- c_mx_5 : mx_5 port map(s_ctrl_memtoreg, s_mem_out_a, s_ula_out_a, s_mx_5_out_a);
+ c_mx_3 : mx_3 port map(s_geral_pc_4, s_add_out_a, s_and_1_out_a, s_mx_3_out_a);
+ c_and_1 : and_1 port map(s_ctrl_branch, s_cmp_zero, s_and_1_out_a);
+ c_mx_4 : mx_4 port map(s_ctrl_jump, s_concat_out_a, s_mx_3_out_a, s_mx_4_out_a);
+
+ -- ID/EX 41 zeros to put the input in the least sign & control & reg_out_a & reg_out_b & inp_alu_b & rs & rt & rd & alu_control
+ -- |127 119 | 118 | 117 | 116 | 115 | 114 | 113 82
+ s_id_ex_in <= x"00" & '0' & s_ctrl_regwrite & s_ctrl_memtoreg & s_ctrl_memwrite & s_ctrl_memread & s_ctrl_regdst & s_reg_out_a
+ -- | 81 50 | 49 18 | 17 13 | 12 8 | 7 3 | 2 0|
+ & s_reg_out_b & s_mx_2_out_a & s_geral_rs & s_geral_rt & s_geral_rd & s_ula_ctrl_out_a;
+ c_id_ex : reg128 port map(clk, reset, s_id_ex_in, s_id_ex_out);
+
+ c_ula : ula port map(s_id_ex_out(113 downto 82), s_id_ex_out(49 downto 18), s_id_ex_out(2 downto 0), s_ula_out_a, open);
+ c_mx_1 : mx_1 port map(s_id_ex_out(114), s_id_ex_out(12 downto 8), s_id_ex_out(7 downto 3), s_mx_1_out_a);
+
+ -- EX/MM 56 zeros & control & alu_out & inp_alu_b & reg_dst
+ -- |127 73 | 72 69 | 68 37 | 36 5 | 4 0|
+ s_ex_mm_in <= x"0000000000000"& "000" & s_id_ex_out(118 downto 115) & s_ula_out_a & s_id_ex_out(81 downto 50) & s_mx_1_out_a;
+ c_ex_mm : reg128 port map(clk, reset, s_ex_mm_in, s_ex_mm_out);
+
+ c_mem : mem port map(clk, reset, s_ex_mm_out(70), s_ex_mm_out(69), s_ex_mm_out(68 downto 37), s_ex_mm_out(36 downto 5),
+ s_mem_out_a);
+
+ -- MM/WB
+ -- |127 71 | 70 69 | 68 37 | 36 5 | 4 0|
+ s_mm_wb_in <= x"00000000000000" & '0' & s_ex_mm_out(72 downto 71) & s_mem_out_a & s_ex_mm_out(68 downto 37) & s_ex_mm_out(4 downto 0);
+ c_mm_wb : reg128 port map(clk, reset, s_mm_wb_in, s_mm_wb_out);
+
+ c_mx_5 : mx_5 port map(s_mm_wb_out(69), s_mm_wb_out(68 downto 37), s_mm_wb_out(36 downto 5), s_mx_5_out_a);
end arc_main_processor;
diff --git a/reg128.vhd b/reg128.vhd
index 04e7c25bd3ec061b9dc466d6b4665ffbd37a0dc5..eb8f5b383eeb908a82288d9daafe47356f2f8f7a 100644
--- a/reg128.vhd
+++ b/reg128.vhd
@@ -1,17 +1,17 @@
-library ieee;
-use ieee.std_logic_1164.all;
+library ieee;
+use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-entity reg64 is
+entity reg128 is
port(
clk: in std_logic;
rst: in std_logic;
inp: in std_logic_vector(127 downto 0);
outp: out std_logic_vector(127 downto 0)
);
-end reg64;
+end reg128;
-architecture arc_reg64 of reg64 is
+architecture arc_reg128 of reg128 is
begin
process(clk, rst)
begin
@@ -21,4 +21,4 @@ begin
outp <= inp;
end if;
end process;
-end architecture arc_reg64;
+end architecture arc_reg128;
diff --git a/reg64.vhd b/reg64.vhd
index a8602ff3f0ada64ad987cedd84311eec75732617..d0a19200404c03638641121569afdb1721f316a4 100644
--- a/reg64.vhd
+++ b/reg64.vhd
@@ -1,5 +1,5 @@
-library ieee;
-use ieee.std_logic_1164.all;
+library ieee;
+use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reg64 is
@@ -16,7 +16,7 @@ begin
process(clk, rst)
begin
if rst = '1' then
- outp <= x"0000000000000000";
+ outp <= x"0040000000000000";
elsif clk'event and clk = '1' then
outp <= inp;
end if;
diff --git a/tb_main_processor.vhd b/tb_main_processor.vhd
index 16e7832f87d36e9710792ef13d3b33a833efefd0..2df87700522540a20fcb084bca972e143de42917 100644
--- a/tb_main_processor.vhd
+++ b/tb_main_processor.vhd
@@ -52,7 +52,7 @@ architecture behavior of tb_main_processor is
signal reset : std_logic := '0';
-- clock period definitions
- constant clk_period : time := 10 ns;
+ constant clk_period : time := 5 ns;
begin
@@ -76,7 +76,7 @@ begin
stim_proc: process
begin
reset <= '1';
- wait for 10 ns;
+ wait for 5 ns;
reset <= '0';
wait;
end process;