From fd4df6021dc7eb564b9acbc1567b684bb3692b4c Mon Sep 17 00:00:00 2001 From: Strozzi <laps15@inf.ufpr.br> Date: Tue, 21 Jun 2016 17:51:41 -0300 Subject: [PATCH] Finishes Pipelinem --- inst.vhd | 4 ++-- main_cttrl.vhd | 20 +++++++++++++++++--- mux2.vhd | 38 ++++++++++++++++++++++++++++++++++++++ pc.vhd | 2 +- reg.vhd | 30 +++++++++++++++++------------- sum.asm | 20 ++++++++++++++++++++ sum.hex | 6 ++++++ 7 files changed, 101 insertions(+), 19 deletions(-) create mode 100644 mux2.vhd create mode 100644 sum.asm create mode 100644 sum.hex diff --git a/inst.vhd b/inst.vhd index a2c9442..c001b4d 100644 --- a/inst.vhd +++ b/inst.vhd @@ -33,8 +33,8 @@ end inst; architecture arc_inst of inst is --deve ser 0 to 255 o array para facilitar a leitura do programa em ordem crescente type memory is array (0 to 255) of std_logic_vector(31 downto 0); - signal program : memory := ( x"01095024", x"01485025" ,x"014a5020",x"01285022", - x"0149582a",x"00004820",x"11490002",x"01284820",x"08100006",x"ae2a0000",x"8e300000", + signal program : memory := ( x"118d0004", x"ac890000" ,x"012c4820",x"01886020", + x"08100000",x"ac890000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000", x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000", x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000", x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000", diff --git a/main_cttrl.vhd b/main_cttrl.vhd index 23a9db1..670119e 100644 --- a/main_cttrl.vhd +++ b/main_cttrl.vhd @@ -134,6 +134,15 @@ architecture arc_main_processor of main_processor is out_a : out std_logic_vector(31 downto 0) ); end component; + + component mux2 is + port( + in_a : in std_logic_vector(31 downto 0); + in_b : in std_logic_vector(31 downto 0); + sel : in std_logic; + out_a : out std_logic_vector(31 downto 0) + ); + end component; component mx_1 is port( @@ -255,6 +264,8 @@ architecture arc_main_processor of main_processor is --add_pc signal s_add_pc_out_a : std_logic_vector(31 downto 0); + signal s_mx_pc_out_a : std_logic_vector(31 downto 0); + signal s_sel_mux_pc : std_logic; --add signal s_add_out_a : std_logic_vector(31 downto 0); @@ -358,9 +369,12 @@ architecture arc_main_processor of main_processor is begin - c_pc : pc port map(clk, reset, s_mx_4_out_a, s_pc_out_a); - c_add_pc : add_pc port map(s_pc_out_a, s_add_pc_out_a); - c_inst : inst port map(s_pc_out_a, s_inst_out_a); + s_sel_mux_pc <= s_ctrl_jump or s_and_1_out_a; + c_mux2 : mux2 port map(s_add_pc_out_a, s_mx_4_out_a, s_sel_mux_pc, + s_mx_pc_out_a); + c_pc : pc port map(clk, reset, s_mx_pc_out_a, s_pc_out_a); + c_add_pc : add_pc port map(s_pc_out_a, s_add_pc_out_a); + c_inst : inst port map(s_pc_out_a, s_inst_out_a); -- IF/ID -- |63 32 | 31 0| diff --git a/mux2.vhd b/mux2.vhd new file mode 100644 index 0000000..bfc2070 --- /dev/null +++ b/mux2.vhd @@ -0,0 +1,38 @@ +-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +-- complete implementation of patterson and hennessy single cycle mips processor +-- copyright (c) 2015 darci luiz tomasi junior +-- +-- this program is free software: you can redistribute it and/or modify +-- it under the terms of the gnu general public license as published by +-- the free software foundation, version 3. +-- +-- this program is distributed in the hope that it will be useful, +-- but without any warranty; without even the implied warranty of +-- merchantability or fitness for a particular purpose. see the +-- gnu general public license for more details. +-- +-- you should have received a copy of the gnu general public license +-- along with this program. if not, see <http://www.gnu.org/licenses/>. +-- +-- engineer: darci luiz tomasi junior +-- e-mail: dltj007@gmail.com +-- date : 08/07/2015 - 19:11 +-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ +library ieee; +use ieee.std_logic_1164.all; + +entity mux2 is + port( + in_a : in std_logic_vector(31 downto 0); + in_b : in std_logic_vector(31 downto 0); + sel : in std_logic; + out_a : out std_logic_vector(31 downto 0) + ); +end mux2; + +architecture arc_mux2 of mux2 is + +begin + out_a <= in_a when sel = '0' else in_b; +end arc_mux2; + diff --git a/pc.vhd b/pc.vhd index 796842f..d7f8b4c 100644 --- a/pc.vhd +++ b/pc.vhd @@ -37,7 +37,7 @@ begin begin if reset = '1' then out_a <= x"00400000"; --para utilizar com o mars - elsif clk'event and clk = '0' then + elsif clk'event and clk = '1' then out_a <= in_a; end if; end process; diff --git a/reg.vhd b/reg.vhd index 427404a..5098eec 100644 --- a/reg.vhd +++ b/reg.vhd @@ -59,28 +59,31 @@ begin reg_2(2) <= (others => '0'); reg_1(3) <= (others => '0'); reg_2(3) <= (others => '0'); - reg_1(4) <= (others => '0'); - reg_2(4) <= (others => '0'); + -- la $a0, xffff0000 + reg_1(4) <= x"ffff0000"; + reg_2(4) <= x"ffff0000"; reg_1(5) <= (others => '0'); reg_2(5) <= (others => '0'); reg_1(6) <= (others => '0'); reg_2(6) <= (others => '0'); reg_1(7) <= (others => '0'); reg_2(7) <= (others => '0'); - --t0 + -- li $t0, 1 reg_1(8) <= (0 => '1', others => '0'); --no temos a funo addi, ento reg_2(8) <= (0 => '1', others => '0'); --tem que ser na fora bruta - --t1 - reg_1(9) <= (0 => '1', 1 => '1', others => '0'); - reg_2(9) <= (0 => '1', 1 => '1', others => '0'); + -- li $t1, 1 + reg_1(9) <= (0 => '1', others => '0'); + reg_2(9) <= (0 => '1', others => '0'); reg_1(10) <= (others => '0'); reg_2(10) <= (others => '0'); reg_1(11) <= (others => '0'); reg_2(11) <= (others => '0'); - reg_1(12) <= (others => '0'); - reg_2(12) <= (others => '0'); - reg_1(13) <= (others => '0'); - reg_2(13) <= (others => '0'); + -- li $t4, 2 + reg_1(12) <= (1 => '1', others => '0'); + reg_2(12) <= (1 => '1', others => '0'); + -- li $t5, 6 + reg_1(13) <= (1 => '1', 2 => '1', others => '0'); + reg_2(13) <= (1 => '1', 2 => '1', others => '0'); reg_1(14) <= (others => '0'); reg_2(14) <= (others => '0'); reg_1(15) <= (others => '0'); @@ -120,9 +123,10 @@ begin reg_2(31) <= (others => '0'); elsif clk'event and clk = '0' and regwrite = '1' then - reg_1(to_integer(unsigned(in_c))) <= in_d; - reg_2(to_integer(unsigned(in_c))) <= in_d; - + if to_integer(unsigned(in_c)) /= 0 then + reg_1(to_integer(unsigned(in_c))) <= in_d; + reg_2(to_integer(unsigned(in_c))) <= in_d; + end if; end if; end process; diff --git a/sum.asm b/sum.asm new file mode 100644 index 0000000..60b1377 --- /dev/null +++ b/sum.asm @@ -0,0 +1,20 @@ +# j=1; +# addi $t1, $zero, 1 +# la $a0, 0x10010000 + +# for(i=1; i <= n; i++) +# addi $t4, $zero, 2 +# li $t0, 1 + +# li $t5, 6 +# la $a0, xffff0000 +for: beq $t4,$t5,fimfor + sw $t1, 0($a0) +# j = j*i; + add $t1, $t1, $t4 + + add $t4, $t4, $t0 + + j for + +fimfor: sw $t1, 0($a0) \ No newline at end of file diff --git a/sum.hex b/sum.hex new file mode 100644 index 0000000..dd8926d --- /dev/null +++ b/sum.hex @@ -0,0 +1,6 @@ +118d0004 +ac890000 +012c4820 +01886020 +08100000 +ac890000 -- GitLab