From 1031af5a2299e2600fbab75c658e6553351f87ea Mon Sep 17 00:00:00 2001
From: Roberto Hexsel <roberto@inf.ufpr.br>
Date: Tue, 30 Jun 2015 12:30:35 -0300
Subject: [PATCH] update on resource usage

---
 README | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/README b/README
index 421df2c..f8c93eb 100644
--- a/README
+++ b/README
@@ -7,8 +7,8 @@ book (Computer Organisation and Design) and is a complete implementation
 of the MIPS32r2 instruction set.
 
 The model was synthesized for an Altera EP4CE30F23.  The model runs at 50 MHz
-(top board speed) and uses up 15% of the combinational blocks and 5% of the
-logic registers on the FPGA.
+(top board speed) and uses up 22% of the combinational blocks, 9% of the
+logic registers, and 33% of the memory bits on the FPGA.
 
 Processor model runs C code, compiled with GCC;  there are scripts to
 compile and assemble code to run on the simulator or the FPGA.
-- 
GitLab