diff --git a/cMIPS/include/cMIPS.h b/cMIPS/include/cMIPS.h
index 4a60af9678a0b82a2392f8c2a6241e75697f93a7..05346dd57dea5d10b6e3c0ed9fcea5efe6555272 100644
--- a/cMIPS/include/cMIPS.h
+++ b/cMIPS/include/cMIPS.h
@@ -10,18 +10,19 @@
#define x_IO_ADDR_MASK (0 - x_IO_ADDR_RANGE)
-#define IO_PRINT_ADDR x_IO_BASE_ADDR;
-#define IO_STDOUT_ADDR (x_IO_BASE_ADDR + 1 * x_IO_ADDR_RANGE);
-#define IO_STDIN_ADDR (x_IO_BASE_ADDR + 2 * x_IO_ADDR_RANGE);
-#define IO_READ_ADDR (x_IO_BASE_ADDR + 3 * x_IO_ADDR_RANGE);
-#define IO_WRITE_ADDR (x_IO_BASE_ADDR + 4 * x_IO_ADDR_RANGE);
-#define IO_COUNT_ADDR (x_IO_BASE_ADDR + 5 * x_IO_ADDR_RANGE);
-#define IO_FPU_ADDR (x_IO_BASE_ADDR + 6 * x_IO_ADDR_RANGE);
-#define IO_UART_ADDR (x_IO_BASE_ADDR + 7 * x_IO_ADDR_RANGE);
-#define IO_STATS_ADDR (x_IO_BASE_ADDR + 8 * x_IO_ADDR_RANGE);
-#define IO_DSP7SEG_ADDR (x_IO_BASE_ADDR + 9 * x_IO_ADDR_RANGE);
-#define IO_KEYBD_ADDR (x_IO_BASE_ADDR +10 * x_IO_ADDR_RANGE);
-#define IO_LCD_ADDR (x_IO_BASE_ADDR +11 * x_IO_ADDR_RANGE);
+#define IO_PRINT_ADDR x_IO_BASE_ADDR
+#define IO_STDOUT_ADDR (x_IO_BASE_ADDR + 1 * x_IO_ADDR_RANGE)
+#define IO_STDIN_ADDR (x_IO_BASE_ADDR + 2 * x_IO_ADDR_RANGE)
+#define IO_READ_ADDR (x_IO_BASE_ADDR + 3 * x_IO_ADDR_RANGE)
+#define IO_WRITE_ADDR (x_IO_BASE_ADDR + 4 * x_IO_ADDR_RANGE)
+#define IO_COUNT_ADDR (x_IO_BASE_ADDR + 5 * x_IO_ADDR_RANGE)
+#define IO_FPU_ADDR (x_IO_BASE_ADDR + 6 * x_IO_ADDR_RANGE)
+#define IO_UART_ADDR (x_IO_BASE_ADDR + 7 * x_IO_ADDR_RANGE)
+#define IO_STATS_ADDR (x_IO_BASE_ADDR + 8 * x_IO_ADDR_RANGE)
+#define IO_DSP7SEG_ADDR (x_IO_BASE_ADDR + 9 * x_IO_ADDR_RANGE)
+#define IO_KEYBD_ADDR (x_IO_BASE_ADDR +10 * x_IO_ADDR_RANGE)
+#define IO_LCD_ADDR (x_IO_BASE_ADDR +11 * x_IO_ADDR_RANGE)
+#define IO_SDCARD_ADDR (x_IO_BASE_ADDR +12 * x_IO_ADDR_RANGE)
extern void exit(int);
@@ -42,6 +43,8 @@ extern void writeClose(void);
extern int readInt(int*);
extern void dumpRAM(void);
extern int print_sp(void);
+extern int print_status(void);
+extern int print_cause(void);
extern char *memcpy(char*, const char*, int);
extern char *memset(char*, const int, int);
diff --git a/cMIPS/include/cMIPS.s b/cMIPS/include/cMIPS.s
index 67514d9c36994145484ce1f4e95602bb3450015a..c343e165af49f15c27617ea7cb160920aa480904 100644
--- a/cMIPS/include/cMIPS.s
+++ b/cMIPS/include/cMIPS.s
@@ -19,6 +19,7 @@
.set HW_dsp7seg_addr,(x_IO_BASE_ADDR + 9 * x_IO_ADDR_RANGE)
.set HW_keybd_addr, (x_IO_BASE_ADDR + 10 * x_IO_ADDR_RANGE)
.set HW_lcd_addr, (x_IO_BASE_ADDR + 11 * x_IO_ADDR_RANGE)
+ .set HW_SDcard_addr, (x_IO_BASE_ADDR + 12 * x_IO_ADDR_RANGE)
# see vhdl/packageMemory.vhd for addresses
.set x_EXCEPTION_0000,0x00000130
@@ -28,25 +29,6 @@
.set x_EXCEPTION_BFC0,0x000004E0
.set x_ENTRY_POINT, 0x00000500
- .set cop0_Index, $0
- .set cop0_Random, $1
- .set cop0_EntryLo0,$2
- .set cop0_EntryLo1,$3
- .set cop0_Context ,$4
- .set cop0_PageMask,$5
- .set cop0_Wired, $6
- .set cop0_BadVAddr,$8
- .set cop0_COUNT ,$9
- .set cop0_EntryHi ,$10
- .set cop0_COMPARE ,$11
- .set cop0_STATUS ,$12
- .set cop0_CAUSE ,$13
- .set cop0_EPC, $14
- .set cop0_CONFIG, $16
- .set cop0_CONFIG_f0,0
- .set cop0_CONFIG_f1,1
- .set cop0_LLAddr, $17
- .set cop0_ErrorPC, $30
.set c0_index, $0
.set c0_random, $1
@@ -70,10 +52,17 @@
# reset: COP0 present, at exception level, all else disabled
- .set cop0_STATUS_reset,0x10000002
+ .set c0_status_reset,0x10000002
# normal state: COP0 present, user mode, all IRQs enabled
- .set cop0_STATUS_normal,0x1000ff11
+ .set c0_status_normal,0x1000ff11
# reset: COUNTER stopped, use special interrVector, no interrupts
- .set cop0_CAUSE_reset, 0x0880007c
+ .set c0_cause_reset, 0x0880007c
+
+
+ .equ led_RED, 0x4000
+ .equ led_GRE, 0x2000
+ .equ led_BLU, 0x1000
+ .equ led_OFF, 0x0FFF
+
diff --git a/cMIPS/include/cMIPSio.c b/cMIPS/include/cMIPSio.c
index e6b3feb5dc8e74e99990f41f62a301c7c217ad58..777d04273ee22d028a4d06a5426b8bbb03e1662c 100644
--- a/cMIPS/include/cMIPSio.c
+++ b/cMIPS/include/cMIPSio.c
@@ -406,8 +406,8 @@ void LCDbyte(unsigned char n) {
//=======================================================================
-// 7 segment display
-// rgb values are in [0,7]
+// 7 segment display and RGB leds
+// rgb values are in [0,7], stored in bits R=bit14, G=bit13, B=bit12
// MSdigit bits bit7..4, lsDigit bit3..0, MSD dot bit9, lsD dot bit8
//=======================================================================
void DSP7SEGput(int MSD, int MSdot, int lsd, int lsdot, int rgb) {
@@ -420,7 +420,7 @@ void DSP7SEGput(int MSD, int MSdot, int lsd, int lsdot, int rgb) {
dig1 = (MSD & 0xf) << 4;
dig0 = (lsd & 0xf);
- leds = (rgb & 0x07) <<10;
+ leds = (rgb & 0x07) <<12;
*IO = leds | dot1 | dot0 | dig1 | dig0;
}
diff --git a/cMIPS/include/handlers.s b/cMIPS/include/handlers.s
index 30cb85a0c49083e915f390aa4d7b48c595e68439..2d5c425f7bfb8169ca7c0841fa0ac7d44b15ed6a 100644
--- a/cMIPS/include/handlers.s
+++ b/cMIPS/include/handlers.s
@@ -534,6 +534,34 @@ _d_ms: addiu $a0, $a0, -1
nop
.end delay_ms
#----------------------------------------------------------------
+
+ ##
+ ## read contents of control registers (for debugging)
+ ##
+ .global print_sp, print_status, print_cause
+ .ent print_sp
+print_sp:
+ jr $ra
+ move $v0, $sp
+ .end print_sp
+
+ .ent print_status
+print_status:
+ mfc0 $v0, c0_status
+ nop
+ jr $ra
+ nop
+ .end print_status
+
+ .ent print_cause
+print_cause:
+ mfc0 $v0, c0_cause
+ nop
+ jr $ra
+ nop
+ .end print_cause
+ #----------------------------------------------------------------
+
#================================================================
diff --git a/cMIPS/include/start.s b/cMIPS/include/start.s
index 661b0233c54e3265b0804c911a29f46dc26d4f6b..b8ba5df34668ebc05165a6d3c718ff683346a686 100644
--- a/cMIPS/include/start.s
+++ b/cMIPS/include/start.s
@@ -131,8 +131,8 @@ _start:
la $sp, (MIDDLE_RAM - 16)
- # set STATUS, cop0, hw interrupts IRQ7,IRQ6,IRQ5 enabled, user mode
- li $k0, cop0_STATUS_normal
+ # set STATUS, c0, hw interrupts IRQ7,IRQ6,IRQ5 enabled, user mode
+ li $k0, c0_status_normal
mtc0 $k0, c0_status
@@ -410,8 +410,6 @@ PT_update:
-
-
##===============================================================
## Page Table
##
diff --git a/cMIPS/include/syn_start.s b/cMIPS/include/syn_start.s
index e147b9552b9742642531bb53af90dc80d1821ade..1c7fd0843f718c8d2c8b4ba96dc6e0e528f82358 100644
--- a/cMIPS/include/syn_start.s
+++ b/cMIPS/include/syn_start.s
@@ -25,11 +25,11 @@ _start: nop
# needed so systems without a page table will not break
# read TLB[4] and write it to TLB[2]
li $k0, 4
- mtc0 $k0, cop0_Index
+ mtc0 $k0, c0_index
ehb
tlbr
li $k1, 2
- mtc0 $k1, cop0_Index
+ mtc0 $k1, c0_index
ehb
tlbwi
@@ -37,28 +37,28 @@ _start: nop
# then set another mapping onto TLB[4], to avoid replicated entries
li $a0, ( (x_DATA_BASE_ADDR + 8*4096) >>12 )
sll $a2, $a0, 12 # tag for RAM[8,9] double-page
- mtc0 $a2, cop0_EntryHi
+ mtc0 $a2, c0_entryhi
li $a0, ((x_DATA_BASE_ADDR + 8*4096) >>12 )
sll $a1, $a0, 6 # RAM[8] (even)
ori $a1, $a1, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
- mtc0 $a1, cop0_EntryLo0
+ mtc0 $a1, c0_entrylo0
li $a0, ( (x_DATA_BASE_ADDR + 9*4096) >>12 )
sll $a1, $a0, 6 # RAM[9] (odd)
ori $a1, $a1, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
- mtc0 $a1, cop0_EntryLo1
+ mtc0 $a1, c0_entrylo1
# and write it to TLB[4]
li $k0, 4
- mtc0 $k0, cop0_Index
+ mtc0 $k0, c0_index
tlbwi
# pin down first four TLB entries: ROM[0], RAM[0], stack and I/O
li $k0, 4
- mtc0 $k0, cop0_Wired
+ mtc0 $k0, c0_wired
# initialize SP at top of RAM: RAM[1] - 16
@@ -66,7 +66,7 @@ _start: nop
# set STATUS, cop0, hw interrupt IRQ7,IRQ6,IRQ5 enabled, user mode
li $k0, 0x1000e011
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
j main
nop
@@ -78,21 +78,41 @@ exit:
_exit: la $k0, HW_dsp7seg_addr # 7 segment display
li $k1, 0x1300 # display .0.0, RED led
sw $k1, 0($k0) # write to 7 segment display
-
+ li $k0, 0x10000010
+ mtc0 $k0, c0_status # disable interrupts
+ nop
+
hexit: j hexit # wait forever
nop
.end _start
##
- ## read contants of the stack-pointer (for debugging)
+ ## read contents of control registers (for debugging)
##
- .global print_sp
+ .global print_sp, print_status, print_cause
.ent print_sp
print_sp:
jr $ra
move $v0, $sp
.end print_sp
+
+ .ent print_status
+print_status:
+ mfc0 $v0, c0_status
+ nop
+ jr $ra
+ nop
+ .end print_status
+
+ .ent print_cause
+print_cause:
+ mfc0 $v0, c0_cause
+ nop
+ jr $ra
+ nop
+ .end print_cause
+
##
##================================================================
diff --git a/cMIPS/tests/badVAddr.s b/cMIPS/tests/badVAddr.s
index 74b6d95bf7134a62b43c5f08a3fa13d25f663c64..85902d921185be1ab21267b4bbcce60ee39d2699 100644
--- a/cMIPS/tests/badVAddr.s
+++ b/cMIPS/tests/badVAddr.s
@@ -10,7 +10,7 @@ _start: nop
## set STATUS, cop0, no interrupts enabled, user mode
li $k0, 0x10000010
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
j main
nop
@@ -32,7 +32,7 @@ _exit: nop # flush pipeline
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -42,7 +42,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -80,7 +80,7 @@ excp_180:
.org x_EXCEPTION_0200,0
_excp_0200:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
diff --git a/cMIPS/tests/badVAddrMM.s b/cMIPS/tests/badVAddrMM.s
index 157f65d71f30718ffce57c66c1fe2dc18aaf04f3..c805efddc58e500044fba33ba686322604e0f191 100644
--- a/cMIPS/tests/badVAddrMM.s
+++ b/cMIPS/tests/badVAddrMM.s
@@ -9,7 +9,7 @@ _start: nop
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: ramTop-8
## set STATUS, cop0, no interrupts enabled, user mode
- li $k0, cop0_STATUS_normal
+ li $k0, c0_status_normal
mtc0 $k0, c0_status
j main
@@ -33,7 +33,7 @@ _exit: nop # flush pipeline
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -43,7 +43,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -97,7 +97,7 @@ _excp_0200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
diff --git a/cMIPS/tests/break.s b/cMIPS/tests/break.s
index e6645c7013825550381b504dc8e44a2581f5a5f4..922d02f2ce5bee82ff4af5e258c96e650eb718ea 100644
--- a/cMIPS/tests/break.s
+++ b/cMIPS/tests/break.s
@@ -15,7 +15,7 @@ _start: nop
## set STATUS, cop0, no interrupts enabled, user mode
li $k0, 0x10000010
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
j main
nop
@@ -35,7 +35,7 @@ _exit: nop # flush pipeline
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -45,7 +45,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -60,13 +60,13 @@ _excp_0100:
.ent _excp_180
excp_180:
_excp_180:
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
sw $k0, 0($15) # print CAUSE
li $k0, '\n'
sw $k0, x_IO_ADDR_RANGE($15) # print new-line
- mfc0 $k1, cop0_EPC # advance EPC to next instruction
+ mfc0 $k1, c0_epc # advance EPC to next instruction
addi $k1, $k1, 4
- mtc0 $k1, cop0_EPC
+ mtc0 $k1, c0_epc
addiu $7, $7, -1
eret
.end _excp_180
@@ -79,7 +79,7 @@ _excp_200:
##
## this exception should not happen
##
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
sw $k0,0($15) # print CAUSE
li $k1, 'e'
sw $k1, x_IO_ADDR_RANGE($15)
@@ -95,7 +95,7 @@ _excp_200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
diff --git a/cMIPS/tests/busError_d.s b/cMIPS/tests/busError_d.s
index 0bfcfaa45b55a92e320a0b7e38ca0297baf1f01b..2e84cc64e506a2481e77aaca70c324f936e7c46e 100644
--- a/cMIPS/tests/busError_d.s
+++ b/cMIPS/tests/busError_d.s
@@ -13,7 +13,7 @@ _start: nop
## set STATUS, cop0, no interrupts enabled, user mode
li $k0, 0x10000010
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
j main
nop
@@ -37,7 +37,7 @@ _exit: nop # flush pipeline
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -47,7 +47,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -64,14 +64,14 @@ _excp_0100:
excp_180:
li $k0, '\n'
sw $k0, x_IO_ADDR_RANGE($14)
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
# andi $k0, $k0, 0x003f # mask off cause of exception
sw $k0, 0($14) # print CAUSE
li $k0, '\n'
sw $k0, x_IO_ADDR_RANGE($14)
li $k0, 0x10000010 # clear status of exception
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
j apocalipse # and print a message
nop
@@ -83,7 +83,7 @@ excp_180:
.org x_EXCEPTION_0200,0
_excp_0200:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -94,7 +94,7 @@ _excp_0200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -119,19 +119,19 @@ main: la $14, x_IO_BASE_ADDR # used by handler
# sw $2, 0($14)
li $8, (ram_displ & 0xfffff000) # keep VPN2
- mtc0 $8, cop0_EntryHi
+ mtc0 $8, c0_entryhi
# sw $8, 0($14)
li $6, ( ((ram_displ >>12) <<6) | 0b000111 ) # PPN0
- mtc0 $6, cop0_EntryLo0
+ mtc0 $6, c0_entrylo0
# sw $6, 0($14)
li $7, ( (((ram_displ+4096) >>12) <<6) | 0b000111 ) # PPN1
- mtc0 $7, cop0_EntryLo1
+ mtc0 $7, c0_entrylo1
# sw $7, 0($14)
li $5, 7 # read TLB(7)
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
ehb
tlbwi
diff --git a/cMIPS/tests/busError_i.s b/cMIPS/tests/busError_i.s
index b1f69575a7c6931f9c98c7d028d4b719520b0f25..c2ecfb66b68fc92bfe406ab7da94032acebdd53d 100644
--- a/cMIPS/tests/busError_i.s
+++ b/cMIPS/tests/busError_i.s
@@ -18,7 +18,7 @@ _start: nop
## set STATUS, cop0, no interrupts enabled, user mode
li $k0, 0x10000010
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
.set bad_address, (x_INST_BASE_ADDR + x_INST_MEM_SZ + 4096)
@@ -27,21 +27,21 @@ _start: nop
li $a0, ( bad_address >>12 )
sll $a2, $a0, 12 # tag for RAM[8,9] double-page
- mtc0 $a2, cop0_EntryHi
+ mtc0 $a2, c0_entryhi
li $a0, ((bad_address + 0*4096) >>12 )
sll $a1, $a0, 6 # ROM_top+4096 (even)
ori $a1, $a1, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
- mtc0 $a1, cop0_EntryLo0
+ mtc0 $a1, c0_entrylo0
li $a0, ((bad_address + 1*4096) >>12 )
sll $a1, $a0, 6 # ROM_top+8192 (odd)
ori $a1, $a1, 0b00000000000000000000000000000111 # ccc=0, d,v,g1
- mtc0 $a1, cop0_EntryLo1
+ mtc0 $a1, c0_entrylo1
# and write it to TLB[3]
li $k0, 3
- mtc0 $k0, cop0_Index
+ mtc0 $k0, c0_index
tlbwi
j main
@@ -66,7 +66,7 @@ _exit: nop # flush pipeline
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -76,7 +76,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -93,13 +93,13 @@ _excp_0100:
excp_180:
li $k0, '\n'
sw $k0, x_IO_ADDR_RANGE($14)
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
sw $k0, 0($14) # print CAUSE
li $k0, '\n'
sw $k0, x_IO_ADDR_RANGE($14)
li $k0, 0x10000010 # clear status of exception
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
j apocalipse # and print a message
nop
@@ -110,7 +110,7 @@ excp_180:
.org x_EXCEPTION_0200,0
_excp_0200:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -121,7 +121,7 @@ _excp_0200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
diff --git a/cMIPS/tests/counter.s b/cMIPS/tests/counter.s
index 09a069b64d804165fd95c838655bad39f7f06f72..cfc9123de3271ec6ecc993b32d384b27048cf0ee 100644
--- a/cMIPS/tests/counter.s
+++ b/cMIPS/tests/counter.s
@@ -17,12 +17,12 @@
.global _exit
_start: nop
- li $k0, cop0_STATUS_reset # RESET, kernel mode, all else disabled
+ li $k0, c0_status_reset # RESET, kernel mode, all else disabled
mtc0 $k0, c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: ramTop-8
li $k0, 0x1800ff01 # RESET_STATUS, kernel mode, interr enabled
mtc0 $k0, c0_status
- li $k0, cop0_CAUSE_reset # RESET, disable counter
+ li $k0, c0_cause_reset # RESET, disable counter
mtc0 $k0, c0_cause
la $15,x_IO_BASE_ADDR
diff --git a/cMIPS/tests/extract.s b/cMIPS/tests/extract.s
index ac9de4ae2b3af6ac2b5a4b28c96bebeb3b8dc356..9d7ea0c6efc5b8549b279f379cbd3914330ae666 100644
--- a/cMIPS/tests/extract.s
+++ b/cMIPS/tests/extract.s
@@ -8,12 +8,12 @@
.ent _start
_start: nop
li $k0,0x10000002 # RESET_STATUS, kernel mode, all else disabled
- mtc0 $k0,cop0_STATUS
+ mtc0 $k0,c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: memTop-8
li $k0,0x00000000 # nothing happens
- mtc0 $k0,cop0_CAUSE
+ mtc0 $k0,c0_cause
li $k0, 0x1000ff01 # enable interrupts
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
nop
jal main
exit:
@@ -32,12 +32,12 @@ _exit: nop # flush pipeline
.global excp_180
.ent excp_180
excp_180:
- mfc0 $k0, cop0_CAUSE # show cause
+ mfc0 $k0, c0_cause # show cause
sw $k0, 0($15)
li $k1, 0x00000000 # disable SW interrupt
- mtc0 $k1, cop0_CAUSE
+ mtc0 $k1, c0_cause
li $k0, 0x1000ff00 # disable interrupts
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
eret
.end excp_180
diff --git a/cMIPS/tests/fib.c b/cMIPS/tests/fib.c
index 21772e6165ded6f30dc9a10369ed26ba6a57b3d0..7220bcaf9f10490245e3019fbc31c174e67bb4f8 100644
--- a/cMIPS/tests/fib.c
+++ b/cMIPS/tests/fib.c
@@ -15,6 +15,7 @@
#define SEQ_SZ 10
+
/*---------------------------------------------------------------------------*/
void fib(unsigned int* buf, unsigned int n) {
@@ -45,7 +46,7 @@ void myprint(unsigned int* buf, unsigned int n) {
/*---------------------------------------------------------------------------*/
int main() {
- unsigned int buf[10];
+ unsigned int buf[SEQ_SZ];
fib(buf, SEQ_SZ);
myprint(buf, SEQ_SZ);
diff --git a/cMIPS/tests/infiniteLoop.s b/cMIPS/tests/infiniteLoop.s
index e5446911b4dbf236f8c79d3ac112532f0e1cf44b..7f0bde5b7e38e85089cc32c186399b7b58de4b88 100644
--- a/cMIPS/tests/infiniteLoop.s
+++ b/cMIPS/tests/infiniteLoop.s
@@ -8,10 +8,10 @@
.ent _start
_start: nop
li $k0, 0x18000002 # RESET_STATUS, kernel mode, all else disabled
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: ramTop-8
li $k0, 0x0000007c # CAUSE, no exceptions
- mtc0 $k0, cop0_CAUSE # clear CAUSE
+ mtc0 $k0, c0_cause # clear CAUSE
nop
jal main
@@ -33,19 +33,19 @@ _exit: nop # flush pipeline
.ent _excp_180
excp_180:
_excp_180:
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
sw $k0,0($14) # print CAUSE
- mfc0 $k0, cop0_EPC #
+ mfc0 $k0, c0_epc #
sw $k0,0($14) # print EPC
addiu $7,$7,-1
addiu $15,$15,-1 # fix the invalid address
li $k0, 0x18000300 # disable interrupts
- mtc0 $k0, cop0_STATUS
- mfc0 $k0, cop0_EPC # fix the return address
+ mtc0 $k0, c0_status
+ mfc0 $k0, c0_epc # fix the return address
srl $k0,$k0,2
sll $k0,$k0,2
- mtc0 $k0, cop0_EPC
- mtc0 $zero, cop0_CAUSE # clear CAUSE
+ mtc0 $k0, c0_epc
+ mtc0 $zero, c0_cause # clear CAUSE
eret
.end _excp_180
diff --git a/cMIPS/tests/insert.s b/cMIPS/tests/insert.s
index 5dc1ef397030cab290057eace32e6ccb639722fe..03d259409eb84a219bc72a87ec04ea03ed04ca70 100644
--- a/cMIPS/tests/insert.s
+++ b/cMIPS/tests/insert.s
@@ -8,12 +8,12 @@
.ent _start
_start: nop
li $k0,0x10000002 # RESET_STATUS, kernel mode, all else disabled
- mtc0 $k0,cop0_STATUS
+ mtc0 $k0,c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: memTop-8
li $k0,0x00000000 # nothing happens
- mtc0 $k0,cop0_CAUSE
+ mtc0 $k0,c0_cause
li $k0, 0x1000ff01 # enable interrupts
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
nop
jal main
exit:
@@ -32,12 +32,12 @@ _exit: nop # flush pipeline
.global excp_180
.ent excp_180
excp_180:
- mfc0 $k0, cop0_CAUSE # show cause
+ mfc0 $k0, c0_cause # show cause
sw $k0, 0($15)
li $k1, 0x00000000 # disable SW interrupt
- mtc0 $k1, cop0_CAUSE
+ mtc0 $k1, c0_cause
li $k0, 0x1000ff00 # disable interrupts
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
eret
.end excp_180
diff --git a/cMIPS/tests/interrJR_dlySlot.s b/cMIPS/tests/interrJR_dlySlot.s
index 2a1d96a4fddc25862d6660563ced3c32243cb848..df1625c7ce06b10ff3c467b2a60330a270cb99e0 100644
--- a/cMIPS/tests/interrJR_dlySlot.s
+++ b/cMIPS/tests/interrJR_dlySlot.s
@@ -12,12 +12,12 @@
.global _exit
_start: nop
- li $k0, cop0_STATUS_reset # RESET, kernel mode, all else disabled
+ li $k0, c0_status_reset # RESET, kernel mode, all else disabled
mtc0 $k0, c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: ramTop-8
li $k0, 0x1000ff01 # RESET_STATUS, kernel mode, interr enabled
mtc0 $k0, c0_status
- li $k0, cop0_CAUSE_reset # RESET, disable counter
+ li $k0, c0_cause_reset # RESET, disable counter
mtc0 $k0, c0_cause
la $15,x_IO_BASE_ADDR
diff --git a/cMIPS/tests/interr_x2.s b/cMIPS/tests/interr_x2.s
index 72bdfe1cb69eb43ea5bf49773b5984f5ac05a79a..ccc785533eccecee02160a7efd2d0bf7dc018c5e 100644
--- a/cMIPS/tests/interr_x2.s
+++ b/cMIPS/tests/interr_x2.s
@@ -23,12 +23,12 @@
.set ext_restart, 0xc0000000 # start ext_counter, intrr enable
_start: nop
- li $k0, cop0_STATUS_reset # RESET, kernel mode, all else disabled
+ li $k0, c0_status_reset # RESET, kernel mode, all else disabled
mtc0 $k0, c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: ramTop-8
li $k0, 0x1000ff01 # RESET_STATUS, kernel mode, interr enabled
mtc0 $k0, c0_status
- li $k0, cop0_CAUSE_reset # RESET, disable counter
+ li $k0, c0_cause_reset # RESET, disable counter
mtc0 $k0, c0_cause
la $15,x_IO_BASE_ADDR
diff --git a/cMIPS/tests/lwl_lwr.s b/cMIPS/tests/lwl_lwr.s
index 8eba85dc9f998eda5ada6aebbe193dc653dd3f5e..cd81e70b2a5559dbf70abfa8a02cc4ae9dabd501 100644
--- a/cMIPS/tests/lwl_lwr.s
+++ b/cMIPS/tests/lwl_lwr.s
@@ -8,10 +8,10 @@
.ent _start
_start: nop
li $k0, 0x18000002 # RESET_STATUS, kernel mode, all else disabled
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: ramTop-8
li $k0, 0x0000007c # CAUSE, no exceptions
- mtc0 $k0, cop0_CAUSE # clear CAUSE
+ mtc0 $k0, c0_cause # clear CAUSE
nop
jal main
@@ -33,19 +33,19 @@ _exit: nop # flush pipeline
.ent _excp_180
excp_180:
_excp_180:
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
sw $k0,0($14) # print CAUSE
- mfc0 $k0, cop0_EPC #
+ mfc0 $k0, c0_epc #
sw $k0,0($14) # print EPC
addiu $7,$7,-1
addiu $15,$15,-1 # fix the invalid address
li $k0, 0x18000300 # disable interrupts
- mtc0 $k0, cop0_STATUS
- mfc0 $k0, cop0_EPC # fix the return address
+ mtc0 $k0, c0_status
+ mfc0 $k0, c0_epc # fix the return address
srl $k0,$k0,2
sll $k0,$k0,2
- mtc0 $k0, cop0_EPC
- mtc0 $zero, cop0_CAUSE # clear CAUSE
+ mtc0 $k0, c0_epc
+ mtc0 $zero, c0_cause # clear CAUSE
eret
.end _excp_180
diff --git a/cMIPS/tests/mac_7seg.s b/cMIPS/tests/mac_7seg.s
index 090e8634b1acd3987e0632a228fd0a42b1880362..4bd0418fe2d2f5d5b7b0ffbdfeca0ba9584778e7 100644
--- a/cMIPS/tests/mac_7seg.s
+++ b/cMIPS/tests/mac_7seg.s
@@ -15,10 +15,10 @@
_start: nop
li $k0, 0x10000000
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
li $k0, MMU_WIRED
- mtc0 $k0, cop0_Wired
+ mtc0 $k0, c0_wired
j main
nop
@@ -67,42 +67,47 @@ hBFC0: j hBFC0 # wait forever
#
# main -----------------------------------------------------
#
-main: la $25, HW_dsp7seg_addr # 7 segment display
+ .equ DELAY,1000
+ .equ RED, 0x4000
+ .equ GRE, 0x2000
+ .equ BLU, 0x1000
+ .equ OFF, 0x0000
+main: la $25, HW_dsp7seg_addr # 7 segment display
#
- # light up leds RED, GREEN, BLUE
+ # light up leds RED (b14), GREEN (b13), BLUE (b12)
# turn {R.G,B} led on for 1 sec, turn it off for 1 sec,
# repeat for next color
#
- li $9, 0x1000 # light up led RED
+ li $9, RED # light up led RED
sw $9, 0($25) # write to 7 segment display
jal delay_ms
- la $a0, 1000
+ la $a0, DELAY
- li $9, 0x0000 # turn off leds
+ li $9, OFF # turn off leds
sw $9, 0($25) # write to 7 segment display
jal delay_ms
- la $a0, 1000
+ la $a0, DELAY
- li $9, 0x0800 # light up led GREEN
+ li $9, GRE # light up led GREEN
sw $9, 0($25) # write to 7 segment display
jal delay_ms
- la $a0, 1000
+ la $a0, DELAY
- li $9, 0x0000 # turn off leds
+ li $9, OFF # turn off leds
sw $9, 0($25) # write to 7 segment display
jal delay_ms
- la $a0, 1000
+ la $a0, DELAY
- li $9, 0x0400 # light up led BLUE
+ li $9, BLU # light up led BLUE
sw $9, 0($25) # write to 7 segment display
jal delay_ms
- la $a0, 1000
+ la $a0, DELAY
- li $9, 0x0000 # turn off leds
+ li $9, OFF # turn off leds
sw $9, 0($25) # write to 7 segment display
jal delay_ms
- la $a0, 1000
+ la $a0, DELAY
#
@@ -114,20 +119,20 @@ main: la $25, HW_dsp7seg_addr # 7 segment display
li $3,0
new: addiu $3, $3, 1 # change digit
- andi $3, $3, 0x03ff # keep it into 2 digits plus dots
+ andi $3, $3, 0x73ff # keep it into 2 digits plus dots
andi $4, $3, 0x0007 # keep only 3 bits for RGB
- sll $4, $4, 10 # light up the leds
+ sll $4, $4, 12 # light up the leds (RED on bit 14)
or $3, $3, $4
sw $3, 0($25) # write to 7 segment display
jal delay_ms
- li $a0, 750 # wait 3/4 second
+ li $a0, (DELAY*3/4) # wait 3/4 second
- andi $3, $3, 0x003ff # turn off leds
+ andi $3, $3, 0x03ff # turn off leds
sw $3, 0($25) # write to 7 segment display
jal delay_ms
- li $a0, 250 # wait 1/4 second
+ li $a0, (DELAY*1/4) # wait 1/4 second
b new # and repeat forever
nop
diff --git a/cMIPS/tests/mac_intRam.s b/cMIPS/tests/mac_intRam.s
index 33b5a0f44467be90d651ac902c7a5bba07610fab..6ae8843bcfa252cd6548567d9f540c1ce792f7e7 100644
--- a/cMIPS/tests/mac_intRam.s
+++ b/cMIPS/tests/mac_intRam.s
@@ -29,7 +29,7 @@
_start: nop
li $k0, 0x10000000
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
li $k0, MMU_WIRED
mtc0 $k0, cop0_Wired
diff --git a/cMIPS/tests/mac_lcd.s b/cMIPS/tests/mac_lcd.s
index 3dd3f50dd1e3dde789424b8ce7679c899af32b71..88d864ea4e78ff3099c275e7162413dbef3ed2a2 100644
--- a/cMIPS/tests/mac_lcd.s
+++ b/cMIPS/tests/mac_lcd.s
@@ -30,7 +30,7 @@
_start: nop
li $k0, 0x10000000
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
li $k0, MMU_WIRED
mtc0 $k0, cop0_Wired
@@ -41,7 +41,7 @@ _start: nop
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, HW_dsp7seg_addr # 7 segment display
- li $k1, 0x0399 # display .9.9
+ li $k1, 0x4399 # display .9.9, RED led on
sw $k1, 0($k0) # write to 7 segment display
h0000: j h0000 # wait forever
nop
@@ -49,7 +49,7 @@ h0000: j h0000 # wait forever
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, HW_dsp7seg_addr # 7 segment display
- li $k1, 0x0388 # display .8.8
+ li $k1, 0x4388 # display .8.8
sw $k1, 0($k0) # write to 7 segment display
h0100: j h0100 # wait forever
nop
@@ -57,7 +57,7 @@ h0100: j h0100 # wait forever
.org x_EXCEPTION_0180,0
_excp_0180:
la $k0, HW_dsp7seg_addr # 7 segment display
- li $k1, 0x0377 # display .7.7
+ li $k1, 0x4377 # display .7.7
sw $k1, 0($k0) # write to 7 segment display
h0180: j h0180 # wait forever
nop
@@ -65,7 +65,7 @@ h0180: j h0180 # wait forever
.org x_EXCEPTION_0200,0
_excp_0200:
la $k0, HW_dsp7seg_addr # 7 segment display
- li $k1, 0x0366 # display .6.6
+ li $k1, 0x4366 # display .6.6
sw $k1, 0($k0) # write to 7 segment display
h0200: j h0200 # wait forever
nop
@@ -73,7 +73,7 @@ h0200: j h0200 # wait forever
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, HW_dsp7seg_addr # 7 segment display
- li $k1, 0x0355 # display .5.5
+ li $k1, 0x4355 # display .5.5
sw $k1, 0($k0) # write to 7 segment display
hBFC0: j hBFC0 # wait forever
nop
@@ -86,7 +86,7 @@ main: nop
### tell the world we are alive
la $15, HW_dsp7seg_addr # 7 segment display
li $16, 01
- sw $16, 0($15) # write to 7 segment display
+ sw $16, 0($15) # write 01 to 7 segment display
la $4, LCD_reset_cycles # wait for 50ms, so LCDctrl resets
diff --git a/cMIPS/tests/mfc0CONFIG.s b/cMIPS/tests/mfc0CONFIG.s
index d1e0fa41e45aaadd215491b985467d46da30c04e..fa4140415f429906a1896b006e690673702cda08 100644
--- a/cMIPS/tests/mfc0CONFIG.s
+++ b/cMIPS/tests/mfc0CONFIG.s
@@ -25,11 +25,11 @@ _exit: nop # flush pipeline
.org x_EXCEPTION_0180,0 # exception vector_180
.ent _excp_180
_excp_180:
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
sw $k0, 0($15) # print CAUSE
addiu $7, $7, -1
li $k0, 0x10000300 # disable interrupts
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
eret
.end _excp_180
@@ -37,16 +37,16 @@ _excp_180:
.org x_ENTRY_POINT,0 # normal code start
main: la $15, x_IO_BASE_ADDR
nop
- mfc0 $6, cop0_STATUS
+ mfc0 $6, c0_status
sw $6, 0($15)
nop
- mfc0 $6, cop0_CAUSE
+ mfc0 $6, c0_cause
sw $6, 0($15)
nop
- mfc0 $6, cop0_CONFIG,0
+ mfc0 $6, c0_config,0
sw $6, 0($15)
nop
- mfc0 $6, cop0_CONFIG,1
+ mfc0 $6, c0_config,1
li $7, 0x8000007f # mask off TLB/cache configuration
and $6, $6, $7 # so changes in TLB/caches won't break this
sw $6, 0($15)
diff --git a/cMIPS/tests/mmu_context.s b/cMIPS/tests/mmu_context.s
index 542686d80fe7f18e44780db341d8843c5ee20db5..180e4699dca82c2677f9ff11598a5a0cfdc09c5d 100644
--- a/cMIPS/tests/mmu_context.s
+++ b/cMIPS/tests/mmu_context.s
@@ -32,12 +32,12 @@
.ent _start
_start:
- li $2, cop0_STATUS_reset
+ li $2, c0_status_reset
addi $2, $2, -2
- mtc0 $2, cop0_STATUS ### make sure CPU is not at exception level
+ mtc0 $2, c0_status ### make sure CPU is not at exception level
li $2, MMU_WIRED
- mtc0 $2, cop0_Wired ### make sure all but 0'th TLB entries are usable
+ mtc0 $2, c0_wired ### make sure all but 0'th TLB entries are usable
j main
nop
@@ -56,9 +56,9 @@ _start:
excp: tlbp # probe for the guilty entry
tlbr # it will surely hit, use Index to point at it
- mfc0 $k1, cop0_EntryLo0
+ mfc0 $k1, c0_entrylo0
ori $k1, $k1, 0x0002 # make V=1
- mtc0 $k1, cop0_EntryLo0
+ mtc0 $k1, c0_entrylo0
tlbwi # write entry back
li $30, 'e'
@@ -87,12 +87,12 @@ main: la $31, x_IO_BASE_ADDR
##
la $29, 0xaaaf0000 # 16 MS bits
- mtc0 $29, cop0_Context
+ mtc0 $29, c0_context
ehb # clear hazards
ehb # clear hazards
- mfc0 $28, cop0_Context
+ mfc0 $28, c0_context
#sw $28, 0($31)
#sw $29, 0($31)
bne $28, $29, error1
@@ -123,12 +123,12 @@ next1: li $30, '\n'
move $28, $zero
la $29, 0x555f0000 # can write only 16 MS bits
- mtc0 $29, cop0_Context # must read back 0x555f0000
+ mtc0 $29, c0_context # must read back 0x555f0000
ehb # clear hazards
ehb # clear hazards
- mfc0 $28, cop0_Context
+ mfc0 $28, c0_context
#sw $28, 0($31)
srl $28, $28, 16 # keep only 16 MS bits
li $27, 0x555f # check 16MS bits = 0x555f---- = 0x555f
@@ -161,21 +161,21 @@ next2: li $30, '\n'
##
li $5, 4 # tlb[4] maps first RAM entry
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
tlbr
ehb
- mfc0 $6, cop0_EntryLo0
+ mfc0 $6, c0_entrylo0
li $7, -3 # clear valid bit: -3 =0xffff.fffd
and $5, $6, $7
- mtc0 $5, cop0_EntryLo0
+ mtc0 $5, c0_entrylo0
ehb
tlbwi # change mapping
la $29, 0xffff0000 # can write only 16 MS bits
- mtc0 $29, cop0_Context
+ mtc0 $29, c0_context
ehb # clear hazards
nop
@@ -192,7 +192,7 @@ next2: li $30, '\n'
nop
nop
- mfc0 $28, cop0_Context
+ mfc0 $28, c0_context
#sw $28, 0($31)
la $27, 0xffff0000 | (x_DATA_BASE_ADDR >>9)
@@ -222,7 +222,7 @@ next3: li $30, '\n'
## make sure BadVAddr was loaded correctly with offending address
##
- mfc0 $28, cop0_BadVAddr
+ mfc0 $28, c0_badvaddr
#sw $28, 0($31)
#sw $8, 0($31)
bne $28, $8, error4
diff --git a/cMIPS/tests/mmu_double.s b/cMIPS/tests/mmu_double.s
index b4db6f17f448a90974278ad7f1fa542a2e461e19..171cb5414d5d09bbff6f15772b4d60a46a0b4d9f 100644
--- a/cMIPS/tests/mmu_double.s
+++ b/cMIPS/tests/mmu_double.s
@@ -42,9 +42,9 @@
## set STATUS, cop0, no interrupts enabled
_start: li $k0, 0x10000000
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
li $k0, MMU_WIRED
- mtc0 $k0, cop0_Wired
+ mtc0 $k0, c0_wired
j main
nop
@@ -59,11 +59,11 @@ _start: li $k0, 0x10000000
.set noreorder
.set noat
-_excp_000: mfc0 $k1, cop0_Context
+_excp_000: mfc0 $k1, c0_context
lw $k0, 0($k1) # k0 <- TP[Context.lo]
lw $k1, 8($k1) # k1 <- TP[Context.hi]
- mtc0 $k0, cop0_EntryLo0 # EntryLo0 <- k0 = even element
- mtc0 $k1, cop0_EntryLo1 # EntryLo1 <- k1 = odd element
+ mtc0 $k0, c0_entrylo0 # EntryLo0 <- k0 = even element
+ mtc0 $k1, c0_entrylo1 # EntryLo1 <- k1 = odd element
ehb
tlbwi # write indexed for not overwriting PTable
li $30, 't'
@@ -84,7 +84,7 @@ _excp_000: mfc0 $k1, cop0_Context
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -105,11 +105,11 @@ _excp_0100:
## EntryHi holds VPN2(31..13), probe the TLB for the offending entry
## VPN2 g ASID : PPN0 ccc0 d0 v0 g0 : PPN1 ccc1 d1 v1 g1
_excp_180: tlbp # probe for the guilty entry
- mfc0 $k1, cop0_CAUSE # clear CAUSE
+ mfc0 $k1, c0_cause # clear CAUSE
tlbr # it will surely hit, just use Index to point at it
- mfc0 $k1, cop0_EntryLo0
+ mfc0 $k1, c0_entrylo0
ori $k1, $k1, 0x0002 # make V=1
- mtc0 $k1, cop0_EntryLo0
+ mtc0 $k1, c0_entrylo0
tlbwi # write entry back
li $30, 'h'
@@ -129,7 +129,7 @@ _excp_180: tlbp # probe for the guilty entry
_excp_0200:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -139,7 +139,7 @@ _excp_0200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -174,12 +174,12 @@ main: la $20, x_IO_BASE_ADDR
la $4, PTbase
li $5, 0 # 1st ROM mapping
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
nop
tlbr
- mfc0 $6, cop0_EntryLo0
- mfc0 $7, cop0_EntryLo1
+ mfc0 $6, c0_entrylo0
+ mfc0 $7, c0_entrylo1
# 1st entry: PPN0 & PPN1 ROM
sw $6, 0($4)
@@ -188,12 +188,12 @@ main: la $20, x_IO_BASE_ADDR
sw $0, 0xc($4)
li $5, 2 # 2nd ROM mapping
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
nop
tlbr
- mfc0 $6, cop0_EntryLo0
- mfc0 $7, cop0_EntryLo1
+ mfc0 $6, c0_entrylo0
+ mfc0 $7, c0_entrylo1
# 2nd entry: PPN2 & PPN3 ROM
sw $6, 0x10($4)
@@ -202,16 +202,16 @@ main: la $20, x_IO_BASE_ADDR
sw $0, 0x1c($4)
# load Context with PTbase
- mtc0 $4, cop0_Context
+ mtc0 $4, c0_context
## change mapping for 2nd ROM TLB entry, thus causing a miss
li $9, 0x2000
sll $9, $9, 8
- mfc0 $8, cop0_EntryHi
+ mfc0 $8, c0_entryhi
add $8, $9, $8 # change tag
- mtc0 $8, cop0_EntryHi
+ mtc0 $8, c0_entryhi
tlbwi # and write it back to TLB
@@ -221,16 +221,16 @@ main: la $20, x_IO_BASE_ADDR
##
## read tlb[4] (1st RAM mapping) and clear the V bit
fix5: li $5, 4
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
tlbr
- mfc0 $6, cop0_EntryLo0
+ mfc0 $6, c0_entrylo0
addi $7, $zero, -3 # 0xffff.fffd = 1111.1111.1111.1101
and $8, $7, $6 # clear V bit
- mtc0 $8, cop0_EntryLo0
+ mtc0 $8, c0_entrylo0
tlbwi # write entry back to TLB
diff --git a/cMIPS/tests/mmu_double2.s b/cMIPS/tests/mmu_double2.s
index d4292775e5c47b8682c8611c639eaace84f3d70d..9f7bed2972dc2096a71c0e7ae261b065cd8b0aa5 100644
--- a/cMIPS/tests/mmu_double2.s
+++ b/cMIPS/tests/mmu_double2.s
@@ -42,9 +42,9 @@
## set STATUS, cop0, no interrupts enabled
_start: li $k0, 0x10000000
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
li $k0, MMU_WIRED
- mtc0 $k0, cop0_Wired
+ mtc0 $k0, c0_wired
j main
nop
@@ -59,11 +59,11 @@ _start: li $k0, 0x10000000
.set noreorder
.set noat
-_excp_000: mfc0 $k1, cop0_Context
+_excp_000: mfc0 $k1, c0_context
lw $k0, 0($k1) # k0 <- TP[Context.lo]
lw $k1, 8($k1) # k1 <- TP[Context.hi]
- mtc0 $k0, cop0_EntryLo0 # EntryLo0 <- k0 = even element
- mtc0 $k1, cop0_EntryLo1 # EntryLo1 <- k1 = odd element
+ mtc0 $k0, c0_entrylo0 # EntryLo0 <- k0 = even element
+ mtc0 $k1, c0_entrylo1 # EntryLo1 <- k1 = odd element
ehb
tlbwi # write indexed for not overwriting PTable
li $30, 't'
@@ -84,7 +84,7 @@ _excp_000: mfc0 $k1, cop0_Context
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -107,11 +107,11 @@ _excp_0100:
## EntryHi holds VPN2(31..13), probe the TLB for the offending entry
## VPN2 g ASID : PPN0 ccc0 d0 v0 g0 : PPN1 ccc1 d1 v1 g1
_excp_180: tlbp # probe for the guilty entry
- mfc0 $k1, cop0_CAUSE # clear CAUSE
+ mfc0 $k1, c0_cause # clear CAUSE
tlbr # it will surely hit, just use Index to point at it
- mfc0 $k1, cop0_EntryLo0
+ mfc0 $k1, c0_entrylo0
ori $k1, $k1, 0x0002 # make V=1
- mtc0 $k1, cop0_EntryLo0
+ mtc0 $k1, c0_entrylo0
tlbwi # write entry back
li $30, 'h'
@@ -131,7 +131,7 @@ _excp_180: tlbp # probe for the guilty entry
_excp_0200:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -141,7 +141,7 @@ _excp_0200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -177,12 +177,12 @@ main: la $20, x_IO_BASE_ADDR
la $4, PTbase
li $5, 0 # 1st ROM mapping
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
nop
tlbr
- mfc0 $6, cop0_EntryLo0
- mfc0 $7, cop0_EntryLo1
+ mfc0 $6, c0_entrylo0
+ mfc0 $7, c0_entrylo1
# 1st entry: PPN0 & PPN1 ROM
sw $6, 0($4)
@@ -191,12 +191,12 @@ main: la $20, x_IO_BASE_ADDR
sw $0, 0xc($4)
li $5, 2 # 2nd ROM mapping
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
nop
tlbr
- mfc0 $6, cop0_EntryLo0
- mfc0 $7, cop0_EntryLo1
+ mfc0 $6, c0_entrylo0
+ mfc0 $7, c0_entrylo1
# 2nd entry: PPN2 & PPN3 ROM
sw $6, 0x10($4)
@@ -205,16 +205,16 @@ main: la $20, x_IO_BASE_ADDR
sw $0, 0x1c($4)
# load Context with PTbase
- mtc0 $4, cop0_Context
+ mtc0 $4, c0_context
## change mapping for 2nd ROM TLB entry, thus causing a miss
li $9, 0x2000
sll $9, $9, 8
- mfc0 $8, cop0_EntryHi
+ mfc0 $8, c0_entryhi
add $8, $9, $8 # change tag
- mtc0 $8, cop0_EntryHi
+ mtc0 $8, c0_entryhi
tlbwi # and write it back to TLB
@@ -224,16 +224,16 @@ main: la $20, x_IO_BASE_ADDR
##
## read tlb[4] (1st RAM mapping) and clear the V bit
fix5: li $5, 4
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
tlbr
- mfc0 $6, cop0_EntryLo0
+ mfc0 $6, c0_entrylo0
addi $7, $zero, -3 # 0xffff.fffd = 1111.1111.1111.1101
and $8, $7, $6 # clear V bit
- mtc0 $8, cop0_EntryLo0
+ mtc0 $8, c0_entrylo0
tlbwi # write entry back to TLB
diff --git a/cMIPS/tests/mmu_index.s b/cMIPS/tests/mmu_index.s
index c8df76c2102a3f108264de1f6e212ac8a7f954df..7d63fc37ea1296144ee8e0a13592375100e88b55 100644
--- a/cMIPS/tests/mmu_index.s
+++ b/cMIPS/tests/mmu_index.s
@@ -15,9 +15,9 @@
.ent _start
_start: li $5, MMU_WIRED
- mtc0 $5, cop0_Wired ### make sure all but 0'th TLB entries are usable
+ mtc0 $5, c0_wired ### make sure all but 0'th TLB entries are usable
li $6, MMU_CAPACITY - 1
- mtc0 $6, cop0_Index
+ mtc0 $6, c0_index
la $15, x_IO_BASE_ADDR
@@ -35,13 +35,13 @@ _start: li $5, MMU_WIRED
##
li $7, MMU_CAPACITY - 2 # one entry wired -> TLB(0)
- mfc0 $25, cop0_Random # read one value
+ mfc0 $25, c0_random # read one value
#sw $25, 0($15)
nop # there must be more than 6 instructions
nop # in between two comparisons
L1: addiu $7, $7, -1
- mfc0 $26, cop0_Random # read new value
+ mfc0 $26, c0_random # read new value
nop
nop
#sw $26, 0($15)
@@ -67,16 +67,16 @@ L1: addiu $7, $7, -1
li $7, MMU_CAPACITY - 2
li $5, MMU_WIRED + 2 # 3 entries are wired (0..2)
- mtc0 $5, cop0_Wired
+ mtc0 $5, c0_wired
- mfc0 $25, cop0_Random # read one value
+ mfc0 $25, c0_random # read one value
#sw $25, 0($15)
nop # there must be more than 6 instructions
nop # in between two comparisons
L2: addiu $7, $7,-1
- mfc0 $26, cop0_Random
+ mfc0 $26, c0_random
nop
nop
#sw $26, 0($15)
@@ -102,13 +102,13 @@ L2: addiu $7, $7,-1
li $7, MMU_CAPACITY - 2
li $5, MMU_CAPACITY - 1 # 7 entries are wired (0..6)
- mtc0 $5, cop0_Wired
+ mtc0 $5, c0_wired
- mfc0 $25, cop0_Random # read one value
+ mfc0 $25, c0_random # read one value
#sw $25, 0($15)
L3: addiu $7, $7,-1
- mfc0 $26, cop0_Random
+ mfc0 $26, c0_random
nop
nop
#sw $26, 0($15)
@@ -134,14 +134,14 @@ L3: addiu $7, $7,-1
li $7, 10
li $5, 0 # no entries are wired
- mtc0 $5, cop0_Wired
+ mtc0 $5, c0_wired
- mfc0 $25, cop0_Random # read one value
+ mfc0 $25, c0_random # read one value
#sw $25, 0($15)
nop
L4: addiu $7, $7,-1
- mfc0 $26, cop0_Random
+ mfc0 $26, c0_random
nop
#sw $26, 0($15)
beq $26, $25, error # stop if last two values read are equal
diff --git a/cMIPS/tests/mmu_inval.s b/cMIPS/tests/mmu_inval.s
index 5c43a7c53011eb80605904ed9283d72cf30bc48a..f6eae39cbccbfd09eccfb28cd3b1d2101389b123 100644
--- a/cMIPS/tests/mmu_inval.s
+++ b/cMIPS/tests/mmu_inval.s
@@ -38,7 +38,7 @@
## set STATUS, cop0, no interrupts enabled, EXL=0
_start: li $k0, 0x10000000
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
j main
nop
@@ -48,7 +48,7 @@ _start: li $k0, 0x10000000
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -58,7 +58,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -80,9 +80,9 @@ excp: # EntryHi holds VPN2(31..13)
_excp: tlbp # probe for the guilty entry
nop
tlbr # it will surely hit, just use Index to point at it
- mfc0 $k1, cop0_EntryLo0
+ mfc0 $k1, c0_entrylo0
ori $k1, $k1, 0x0002 # make V=1
- mtc0 $k1, cop0_EntryLo0
+ mtc0 $k1, c0_entrylo0
ehb
tlbwi # write entry back
@@ -105,7 +105,7 @@ _excp: tlbp # probe for the guilty entry
_excp_0200:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -115,7 +115,7 @@ _excp_0200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -137,22 +137,22 @@ _excp_BFC0:
main: la $20, x_IO_BASE_ADDR
li $k0, MMU_WIRED
- mtc0 $k0, cop0_Wired # Wire to the TLB entries 0 (ROM) and 1 (IO)
+ mtc0 $k0, c0_wired # Wire to the TLB entries 0 (ROM) and 1 (IO)
## read tlb[5] (2nd RAM mapping) and clear the V bit
li $5, 5
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
tlbr
- mfc0 $6, cop0_EntryLo0
+ mfc0 $6, c0_entrylo0
addi $7, $zero, -3 # 0xffff.fffd = 1111.1111.1111.1101
and $8, $7, $6 # clear V bit
- mtc0 $8, cop0_EntryLo0
+ mtc0 $8, c0_entrylo0
- mfc0 $9, cop0_EntryHi
+ mfc0 $9, c0_entryhi
tlbwi # write entry back to TLB
diff --git a/cMIPS/tests/mmu_inval2.s b/cMIPS/tests/mmu_inval2.s
index 51873837ed4e78c6b814853751c9f175b32285a1..d97912205196f9bb54084e57cef4a2d6c5bc54b5 100644
--- a/cMIPS/tests/mmu_inval2.s
+++ b/cMIPS/tests/mmu_inval2.s
@@ -38,7 +38,7 @@
## set STATUS, cop0, no interrupts enabled, UM=0, EXL=0
_start: li $k0, 0x10000000
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
j main
nop
@@ -49,7 +49,7 @@ _start: li $k0, 0x10000000
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -59,7 +59,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -81,9 +81,9 @@ excp: # EntryHi holds VPN2(31..13)
_excp: tlbp # probe for the guilty entry
nop
tlbr # it will surely hit, just use Index to point at it
- mfc0 $k1, cop0_EntryLo0
+ mfc0 $k1, c0_entrylo0
ori $k1, $k1, 0x0002 # make V=1
- mtc0 $k1, cop0_EntryLo0
+ mtc0 $k1, c0_entrylo0
tlbwi # write entry back
li $30, 't'
@@ -106,7 +106,7 @@ _excp: tlbp # probe for the guilty entry
_excp_0200:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -116,7 +116,7 @@ _excp_0200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -135,22 +135,22 @@ _excp_BFC0:
main: la $20, x_IO_BASE_ADDR
li $k0, MMU_WIRED
- mtc0 $k0, cop0_Wired # Wire to the TLB entries 0 (ROM) and 1 (IO)
+ mtc0 $k0, c0_wired # Wire to the TLB entries 0 (ROM) and 1 (IO)
## read tlb[5] (2nd RAM mapping) and clear the V bit
li $5, 5
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
tlbr
- mfc0 $6, cop0_EntryLo0
+ mfc0 $6, c0_entrylo0
addi $7, $zero, -3 # 0xffff.fffd = 1111.1111.1111.1101
and $8, $7, $6 # clear D bit
- mtc0 $8, cop0_EntryLo0
+ mtc0 $8, c0_entrylo0
- mfc0 $9, cop0_EntryHi
+ mfc0 $9, c0_entryhi
tlbwi # write entry back to TLB
diff --git a/cMIPS/tests/mmu_mod.s b/cMIPS/tests/mmu_mod.s
index 0eb529b9f52114219b9304ccda3e9d5a062b24ab..e4a4d90498a813052d5f2bba733fbc3e41c8fd9a 100644
--- a/cMIPS/tests/mmu_mod.s
+++ b/cMIPS/tests/mmu_mod.s
@@ -39,7 +39,7 @@
## set STATUS, cop0, no interrupts enabled
_start: li $k0, 0x10000000
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
j main
nop
@@ -50,7 +50,7 @@ _start: li $k0, 0x10000000
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -60,7 +60,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -85,11 +85,11 @@ _excp: tlbp # probe for the guilty entry
nop
tlbr # it will surely hit, just use Index to point at it
- mfc0 $k1, cop0_EntryLo0
+ mfc0 $k1, c0_entrylo0
ori $k1, $k1, 0x0004 # make D=1
- mtc0 $k1, cop0_EntryLo0
+ mtc0 $k1, c0_entrylo0
tlbwi # write entry back
@@ -112,7 +112,7 @@ _excp: tlbp # probe for the guilty entry
_excp_0200:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -122,7 +122,7 @@ _excp_0200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -142,22 +142,22 @@ _excp_BFC0:
main: la $20, x_IO_BASE_ADDR
li $k0, MMU_WIRED
- mtc0 $k0, cop0_Wired # Wire TLB entries 0 (ROM) and 1 (IO)
+ mtc0 $k0, c0_wired # Wire TLB entries 0 (ROM) and 1 (IO)
## read tlb[5] (2nd RAM mapping) and clear the D bit
li $5, 5
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
tlbr
- mfc0 $6, cop0_EntryLo0
+ mfc0 $6, c0_entrylo0
addi $7, $zero, -5 # 0xffff.fffb = 1111.1111.1111.1011
and $8, $7, $6 # clear D bit
- mtc0 $8, cop0_EntryLo0
+ mtc0 $8, c0_entrylo0
- mfc0 $9, cop0_EntryHi
+ mfc0 $9, c0_entryhi
ehb
tlbwi # write entry back to TLB
diff --git a/cMIPS/tests/mmu_mod2.s b/cMIPS/tests/mmu_mod2.s
index 1da91060debba0ccafc9f7e697950b3c5ade8744..e3ae0cee5ac7373b882e47a83e52f5f1a0d4ae9a 100644
--- a/cMIPS/tests/mmu_mod2.s
+++ b/cMIPS/tests/mmu_mod2.s
@@ -39,7 +39,7 @@
## set STATUS, cop0, no interrupts enabled
_start: li $k0, 0x10000000
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
j main
nop
@@ -49,7 +49,7 @@ _start: li $k0, 0x10000000
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -59,7 +59,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -84,15 +84,15 @@ _excp: tlbp # probe for the guilty entry
nop
tlbr # it will surely hit, just use Index to point at it
- mfc0 $k1, cop0_EntryLo0
+ mfc0 $k1, c0_entrylo0
ori $k1, $k1, 0x0004 # make D=1
- mtc0 $k1, cop0_EntryLo0
+ mtc0 $k1, c0_entrylo0
tlbwi # write entry back
- mfc0 $k1, cop0_CAUSE # clear CAUSE
+ mfc0 $k1, c0_cause # clear CAUSE
li $30, 'h'
sw $30, x_IO_ADDR_RANGE($20)
@@ -112,7 +112,7 @@ _excp: tlbp # probe for the guilty entry
_excp_0200:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -122,7 +122,7 @@ _excp_0200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -144,22 +144,22 @@ _excp_BFC0:
main: la $20, x_IO_BASE_ADDR
li $k0, MMU_WIRED
- mtc0 $k0, cop0_Wired # Wire TLB entries 0 (ROM) and 1 (IO)
+ mtc0 $k0, c0_wired # Wire TLB entries 0 (ROM) and 1 (IO)
## read tlb[5] (2nd RAM mapping) and clear the D bit
li $5, 5
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
tlbr
- mfc0 $6, cop0_EntryLo0
+ mfc0 $6, c0_entrylo0
addi $7, $zero, -5 # 0xffff.fffb = 1111.1111.1111.1011
and $8, $7, $6 # clear D bit
- mtc0 $8, cop0_EntryLo0
+ mtc0 $8, c0_entrylo0
- mfc0 $9, cop0_EntryHi
+ mfc0 $9, c0_entryhi
ehb
tlbwi # write entry back to TLB
diff --git a/cMIPS/tests/mmu_pc_hit.s b/cMIPS/tests/mmu_pc_hit.s
index 4ca722c2e7c559f8e88243668340fbb7550a0320..53217682361ebca7b7dd117ca178fe02255c2b9a 100644
--- a/cMIPS/tests/mmu_pc_hit.s
+++ b/cMIPS/tests/mmu_pc_hit.s
@@ -50,69 +50,69 @@
.ent _start
_start: la $31, x_IO_BASE_ADDR
- mtc0 $zero, cop0_Wired # make sure all TLB entries are usable
+ mtc0 $zero, c0_wired # make sure all TLB entries are usable
## initialize TLB with entries that will not match in tests below
## NOTE: this is strictly forbidden as all entries are equal
## we only do this while testing the TLB
la $2, entryHi_0
- mtc0 $2, cop0_EntryHi
+ mtc0 $2, c0_entryhi
la $3, entryLo0_0
- mtc0 $3, cop0_EntryLo0
+ mtc0 $3, c0_entrylo0
#la $4, entryLo1_0
- #mtc0 $4, cop0_EntryLo1
+ #mtc0 $4, c0_entrylo1
li $5, 0
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
tlbwi
la $2, entryHi_1
- mtc0 $2, cop0_EntryHi
+ mtc0 $2, c0_entryhi
la $3, entryLo0_1
- mtc0 $3, cop0_EntryLo0
+ mtc0 $3, c0_entrylo0
#la $4, entryLo1_1
- #mtc0 $4, cop0_EntryLo1
+ #mtc0 $4, c0_entrylo1
li $5, 1
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
tlbwi
la $2, entryHi_2
- mtc0 $2, cop0_EntryHi
+ mtc0 $2, c0_entryhi
la $3, entryLo0_2
- mtc0 $3, cop0_EntryLo0
+ mtc0 $3, c0_entrylo0
#la $4, entryLo1_2
- #mtc0 $4, cop0_EntryLo1
+ #mtc0 $4, c0_entrylo1
li $5, 2
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
tlbwi
la $2, entryHi_3
- mtc0 $2, cop0_EntryHi
+ mtc0 $2, c0_entryhi
la $3, entryLo0_3
- mtc0 $3, cop0_EntryLo0
+ mtc0 $3, c0_entrylo0
#la $4, entryLo1_3
- #mtc0 $4, cop0_EntryLo1
+ #mtc0 $4, c0_entrylo1
li $5, 3
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
tlbwi
li $5,2
- mtc0 $5, cop0_Wired # pin down entries with startup code
+ mtc0 $5, c0_wired # pin down entries with startup code
- mfc0 $19, cop0_Random # check for randomness
+ mfc0 $19, c0_random # check for randomness
sw $19, 0($31)
- mfc0 $19, cop0_Random # check for randomness
+ mfc0 $19, c0_random # check for randomness
sw $19, 0($31)
nop
- mfc0 $19, cop0_Random # check for randomness
+ mfc0 $19, c0_random # check for randomness
sw $19, 0($31)
- mfc0 $19, cop0_Random # check for randomness
+ mfc0 $19, c0_random # check for randomness
sw $19, 0($31)
li $30, '\n'
sw $30, x_IO_ADDR_RANGE($31)
@@ -120,11 +120,11 @@ _start: la $31, x_IO_BASE_ADDR
## write to a random location
la $2, entryHi_3
- mtc0 $2, cop0_EntryHi
+ mtc0 $2, c0_entryhi
la $3, entryLo0_3
- mtc0 $3, cop0_EntryLo0
+ mtc0 $3, c0_entrylo0
#la $4, entryLo1_3
- #mtc0 $4, cop0_EntryLo1
+ #mtc0 $4, c0_entrylo1
tlbwr # write 0x00006001, 0x0000185f, 0x00001c7f to TLB, ranndom loc
@@ -136,16 +136,16 @@ _start: la $31, x_IO_BASE_ADDR
## check first record was written
## make sure it will miss by probing for 0,0,0
##
- mtc0 $zero, cop0_EntryHi
- mtc0 $zero, cop0_EntryLo0
- #mtc0 $zero, cop0_EntryLo1
+ mtc0 $zero, c0_entryhi
+ mtc0 $zero, c0_entrylo0
+ #mtc0 $zero, c0_entrylo1
nop
nop
tlbp
- mfc0 $19, cop0_Index # check for bit31=1
+ mfc0 $19, c0_index # check for bit31=1
sw $19, 0($31)
slt $20, $19, $zero # $20 <- (bit31 = 1)
@@ -179,11 +179,11 @@ next2: li $30, '\n'
# write into another randomly selected entry
la $5, entryHi_2
- mtc0 $5, cop0_EntryHi
+ mtc0 $5, c0_entryhi
la $6, entryLo0_2
- mtc0 $6, cop0_EntryLo0
+ mtc0 $6, c0_entrylo0
#la $7, entryLo1_2
- #mtc0 $7, cop0_EntryLo1
+ #mtc0 $7, c0_entrylo1
nop
tlbwr
@@ -194,9 +194,9 @@ next2: li $30, '\n'
## check second record was written
## make sure it will miss by probing for 0,0,0
##
- mtc0 $zero, cop0_EntryHi
- mtc0 $zero, cop0_EntryLo0
- #mtc0 $zero, cop0_EntryLo1
+ mtc0 $zero, c0_entryhi
+ mtc0 $zero, c0_entrylo0
+ #mtc0 $zero, c0_entrylo1
nop
nop
@@ -205,7 +205,7 @@ next2: li $30, '\n'
ehb
- mfc0 $19, cop0_Index # check for bit31=1
+ mfc0 $19, c0_index # check for bit31=1
sw $19, 0($31)
slt $20, $19, $zero # $20 <- (bit31 = 1)
@@ -240,7 +240,7 @@ next1: li $30, '\n'
## now check for last entry written -- must be a hit
la $5, entryHi_2
- mtc0 $5, cop0_EntryHi
+ mtc0 $5, c0_entryhi
nop
nop
@@ -248,7 +248,7 @@ next1: li $30, '\n'
tlbp
- mfc0 $19, cop0_Index # check for bit31=1
+ mfc0 $19, c0_index # check for bit31=1
sw $19, 0($31)
slt $20, $19, $zero # $20 <- (bit31 = 1)
@@ -277,7 +277,7 @@ next0: li $30, '\n'
## now check for one of the initialization values -- must be a hit
la $5, entryHi_i
- mtc0 $5, cop0_EntryHi
+ mtc0 $5, c0_entryhi
nop
nop
@@ -285,7 +285,7 @@ next0: li $30, '\n'
tlbp
- mfc0 $19, cop0_Index # check for bit31=1
+ mfc0 $19, c0_index # check for bit31=1
sw $19, 0($31)
slt $20, $19, $zero # $20 <- (bit31 = 1)
diff --git a/cMIPS/tests/mmu_refill.s b/cMIPS/tests/mmu_refill.s
index 207a594aefd468d2d43d1740666eafbf71258671..49ba7fecb045ee4b8e78eb9ea1c0a433f816559d 100644
--- a/cMIPS/tests/mmu_refill.s
+++ b/cMIPS/tests/mmu_refill.s
@@ -3,7 +3,7 @@
##
##
## This test breaks if the base of RAM is below 0x0001.0000 since
- ## cop0_Context maps only addresses ABOVE 0x0000.ffff
+ ## c0_context maps only addresses ABOVE 0x0000.ffff
##
##
## EntryHi : EntryLo0 : EntryLo1
@@ -42,7 +42,7 @@
## set STATUS, cop0, no interrupts enabled, EXL=0
_start: li $k0, 0x10000000
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
j main
nop
@@ -58,11 +58,11 @@ _start: li $k0, 0x10000000
.set noat
excp:
-_excp: mfc0 $k1, cop0_Context
+_excp: mfc0 $k1, c0_context
lw $k0, 0($k1) # k0 <- TP[Context.lo]
lw $k1, 8($k1) # k1 <- TP[Context.hi]
- mtc0 $k0, cop0_EntryLo0 # EntryLo0 <- k0 = even element
- mtc0 $k1, cop0_EntryLo1 # EntryLo1 <- k1 = odd element
+ mtc0 $k0, c0_entrylo0 # EntryLo0 <- k0 = even element
+ mtc0 $k1, c0_entrylo1 # EntryLo1 <- k1 = odd element
ehb
tlbwr # update TLB
li $30, 'e'
@@ -82,7 +82,7 @@ _excp: mfc0 $k1, cop0_Context
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -92,7 +92,7 @@ _excp_0100:
.org x_EXCEPTION_0180,0
_excp_0180:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -101,7 +101,7 @@ _excp_0180:
nop
_excp_0200:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -111,7 +111,7 @@ _excp_0200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -138,7 +138,7 @@ _excp_BFC0:
main: la $20, x_IO_BASE_ADDR
li $k0, MMU_WIRED
- mtc0 $k0, cop0_Wired # Wire to the TLB entries 0 (ROM) and 1 (IO)
+ mtc0 $k0, c0_wired # Wire to the TLB entries 0 (ROM) and 1 (IO)
##
@@ -152,13 +152,13 @@ main: la $20, x_IO_BASE_ADDR
la $4, PTbase
li $5, 0 # 1st ROM mapping
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
nop
tlbr
- mfc0 $6, cop0_EntryLo0
+ mfc0 $6, c0_entrylo0
# sw $6, 0($20)
- mfc0 $7, cop0_EntryLo1
+ mfc0 $7, c0_entrylo1
# sw $7, 0($20)
# 1st entry: PPN0 & PPN1 ROM
@@ -169,13 +169,13 @@ main: la $20, x_IO_BASE_ADDR
li $5, 2 # 2nd ROM mapping on 2nd PT element
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
nop
tlbr
- mfc0 $6, cop0_EntryLo0
+ mfc0 $6, c0_entrylo0
# sw $6, 0($20)
- mfc0 $7, cop0_EntryLo1
+ mfc0 $7, c0_entrylo1
# sw $7, 0($20)
@@ -187,13 +187,13 @@ main: la $20, x_IO_BASE_ADDR
li $5, 3 # 3rd ROM mapping on 3rd PT element
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
nop
tlbr
- mfc0 $6, cop0_EntryLo0
+ mfc0 $6, c0_entrylo0
# sw $6, 0($20)
- mfc0 $7, cop0_EntryLo1
+ mfc0 $7, c0_entrylo1
# sw $7, 0($20)
# 2nd entry: PPN4 & PPN5 ROM
@@ -203,22 +203,22 @@ main: la $20, x_IO_BASE_ADDR
sw $0, 44($4)
# load Context with PTbase
- mtc0 $4, cop0_Context
+ mtc0 $4, c0_context
## change mapping for 2nd ROM TLB entry, thus causing a miss
li $5, 2 # 2nd ROM mapping
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
li $9, 0x2000
sll $9, $9, 8
- mfc0 $8, cop0_EntryHi
+ mfc0 $8, c0_entryhi
add $8, $9, $8 # change tag
- mtc0 $8, cop0_EntryHi
+ mtc0 $8, c0_entryhi
tlbwi # and write it back to TLB
diff --git a/cMIPS/tests/mmu_refill2.s b/cMIPS/tests/mmu_refill2.s
index 225978db541275217f6f40785d94c1b385d28560..5f0828982b12a0187853903d883a53d79b602030 100644
--- a/cMIPS/tests/mmu_refill2.s
+++ b/cMIPS/tests/mmu_refill2.s
@@ -23,10 +23,10 @@
## set STATUS, cop0, no interrupts enabled, UM=0, EXL=0
_start: li $k0, 0x10000000
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
li $k0, MMU_WIRED
- mtc0 $k0, cop0_Wired
+ mtc0 $k0, c0_wired
j main
nop
@@ -41,16 +41,16 @@ _start: li $k0, 0x10000000
.set noreorder
.set noat
-_excp: mfc0 $k1, cop0_Context
+_excp: mfc0 $k1, c0_context
lw $k0, 0($k1) # k0 <- TP[Context.lo]
lw $k1, 8($k1) # k1 <- TP[Context.hi]
- mtc0 $k0, cop0_EntryLo0 # EntryLo0 <- k0 = even element
- mtc0 $k1, cop0_EntryLo1 # EntryLo1 <- k1 = odd element
+ mtc0 $k0, c0_entrylo0 # EntryLo0 <- k0 = even element
+ mtc0 $k1, c0_entrylo1 # EntryLo1 <- k1 = odd element
##
## cause, on purpose, another miss on 2nd ROM mapping
##
li $k0, 2
- mtc0 $k0, cop0_Index
+ mtc0 $k0, c0_index
ehb
tlbwi # update TLB
@@ -64,7 +64,7 @@ _excp: mfc0 $k1, cop0_Context
sw $30, x_IO_ADDR_RANGE($20)
li $30, '\n'
sw $30, x_IO_ADDR_RANGE($20)
- mfc0 $k1, cop0_CAUSE # clear CAUSE
+ mfc0 $k1, c0_cause # clear CAUSE
eret
.end _excp
@@ -72,7 +72,7 @@ _excp: mfc0 $k1, cop0_Context
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -84,7 +84,7 @@ _excp_0100:
.org x_EXCEPTION_0180,0
_excp_0180:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
la $a0, not_enough_ram
@@ -99,7 +99,7 @@ _excp_0180:
.org x_EXCEPTION_0200,0
_excp_0200:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -111,7 +111,7 @@ _excp_0200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -151,17 +151,17 @@ main: la $20, x_IO_BASE_ADDR
# load Context with PTbase
la $4, PTbase
- mtc0 $4, cop0_Context
+ mtc0 $4, c0_context
# 1st entry: PPN0 & PPN1 ROM
li $5, 0 # 1st ROM mapping
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
nop
tlbr
- mfc0 $6, cop0_EntryLo0
+ mfc0 $6, c0_entrylo0
# sw $6, 0($20)
- mfc0 $7, cop0_EntryLo1
+ mfc0 $7, c0_entrylo1
# sw $7, 0($20)
sw $6, 0x0($4)
@@ -172,13 +172,13 @@ main: la $20, x_IO_BASE_ADDR
# 2nd entry: PPN2 & PPN3 ROM
li $5, 2 # 2nd ROM mapping
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
nop
tlbr
- mfc0 $6, cop0_EntryLo0
+ mfc0 $6, c0_entrylo0
# sw $6, 0($20)
- mfc0 $7, cop0_EntryLo1
+ mfc0 $7, c0_entrylo1
# sw $7, 0($20)
@@ -190,13 +190,13 @@ main: la $20, x_IO_BASE_ADDR
# 1024th entry: PPN6 & PPN7 RAM
li $5, 7 # 3rd RAM mapping
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
nop
tlbr
- mfc0 $6, cop0_EntryLo0
+ mfc0 $6, c0_entrylo0
# sw $6, 0($20)
- mfc0 $7, cop0_EntryLo1
+ mfc0 $7, c0_entrylo1
# sw $7, 0($20)
.set ram6_displ,((x_DATA_BASE_ADDR + 6*4096)>>(13-4)) # num(VPN2)*16
@@ -212,14 +212,14 @@ main: la $20, x_IO_BASE_ADDR
## change mapping for 3rd RAM TLB entry, thus causing a miss
chnge3: li $5, 7 # 3rd RAM mapping
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
li $9, 0x8000
sll $9, $9, 8
- mfc0 $8, cop0_EntryHi
+ mfc0 $8, c0_entryhi
add $8, $9, $8 # change tag
- mtc0 $8, cop0_EntryHi
+ mtc0 $8, c0_entryhi
ehb
tlbwi # and write it back to TLB (Index = 6)
diff --git a/cMIPS/tests/mmu_refill3.s b/cMIPS/tests/mmu_refill3.s
index d3fbc06ea04da4f6b5566b1c35b354fa69af2e74..5a9a05bad08145a6f1345d4c980dc06083fd8e95 100644
--- a/cMIPS/tests/mmu_refill3.s
+++ b/cMIPS/tests/mmu_refill3.s
@@ -39,10 +39,10 @@
## set STATUS, cop0, no interrupts enabled, UM=0, EXL=0
_start: li $k0, 0x10000000
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
li $k0, MMU_WIRED
- mtc0 $k0, cop0_Wired
+ mtc0 $k0, c0_wired
j main
nop
@@ -57,28 +57,28 @@ _start: li $k0, 0x10000000
.set noreorder
.set noat
-_excp: mfc0 $k1, cop0_Context
+_excp: mfc0 $k1, c0_context
lw $k0, 0($k1) # k0 <- TP[Context.lo]
lw $k1, 8($k1) # k1 <- TP[Context.hi]
- mtc0 $k0, cop0_EntryLo0 # EntryLo0 <- k0 = even element
- mtc0 $k1, cop0_EntryLo1 # EntryLo1 <- k1 = odd element
+ mtc0 $k0, c0_entrylo0 # EntryLo0 <- k0 = even element
+ mtc0 $k1, c0_entrylo1 # EntryLo1 <- k1 = odd element
##
## cause, on purpose, another miss on 2nd ROM mapping
## exchange mappings for TLB[2] and TLB[7]
##
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
li $k0, 0x000c # code for TLBS - 0xc
andi $k1, $k1, 0x000f
bne $k0, $k1, _ex_n
nop
li $k0, 2
- mtc0 $k0, cop0_Index
+ mtc0 $k0, c0_index
ehb
j _ex_w
nop
_ex_n: li $k0, 7
- mtc0 $k0, cop0_Index
+ mtc0 $k0, c0_index
ehb
_ex_w: tlbwi # update TLB
@@ -102,7 +102,7 @@ _ex_w: tlbwi # update TLB
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -112,7 +112,7 @@ _excp_0100:
.org x_EXCEPTION_0180,0
_excp_0180:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -121,7 +121,7 @@ _excp_0180:
nop
_excp_0200:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -131,7 +131,7 @@ _excp_0200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -165,17 +165,17 @@ main: la $20, x_IO_BASE_ADDR
# load Context with PTbase
la $4, PTbase
- mtc0 $4, cop0_Context
+ mtc0 $4, c0_context
# 1st entry: PPN0 & PPN1 ROM
li $5, 0 # 1st ROM mapping
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
nop
tlbr
- mfc0 $6, cop0_EntryLo0
+ mfc0 $6, c0_entrylo0
# sw $6, 0($20)
- mfc0 $7, cop0_EntryLo1
+ mfc0 $7, c0_entrylo1
# sw $7, 0($20)
sw $6, 0x0($4)
@@ -186,13 +186,13 @@ main: la $20, x_IO_BASE_ADDR
# 2nd entry: PPN2 & PPN3 ROM
li $5, 2 # 2nd ROM mapping
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
nop
tlbr
- mfc0 $6, cop0_EntryLo0
+ mfc0 $6, c0_entrylo0
# sw $6, 0($20)
- mfc0 $7, cop0_EntryLo1
+ mfc0 $7, c0_entrylo1
# sw $7, 0($20)
@@ -204,13 +204,13 @@ main: la $20, x_IO_BASE_ADDR
# 1024th entry: PPN6 & PPN7 RAM
li $5, 7 # 3rd RAM mapping
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
nop
tlbr
- mfc0 $6, cop0_EntryLo0
+ mfc0 $6, c0_entrylo0
# sw $6, 0($20)
- mfc0 $7, cop0_EntryLo1
+ mfc0 $7, c0_entrylo1
# sw $7, 0($20)
.set ram6_displ,((x_DATA_BASE_ADDR + 6*4096)>>(13-4)) ## num(VPN2)*16
@@ -226,14 +226,14 @@ main: la $20, x_IO_BASE_ADDR
## change mapping for 4th RAM TLB entry, thus causing a miss
li $5, 7 # 4th RAM mapping
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
li $9, 0x8000
sll $9, $9, 8
- mfc0 $8, cop0_EntryHi
+ mfc0 $8, c0_entryhi
add $8, $9, $8 # change tag
- mtc0 $8, cop0_EntryHi
+ mtc0 $8, c0_entryhi
tlbwi # and write it back to TLB (Index = 6)
diff --git a/cMIPS/tests/mmu_tlbp.s b/cMIPS/tests/mmu_tlbp.s
index 06482be37675090945020becec516acb0be846f0..63f6654367b7dd8c7b8eb1d4486cf2cff5dc565c 100644
--- a/cMIPS/tests/mmu_tlbp.s
+++ b/cMIPS/tests/mmu_tlbp.s
@@ -39,30 +39,30 @@
.ent _start
_start: la $31, x_IO_BASE_ADDR
- li $2, cop0_STATUS_reset
+ li $2, c0_status_reset
addi $2, $2, -2
- mtc0 $2, cop0_STATUS ### make sure CPU is not at exception level
+ mtc0 $2, c0_status ### make sure CPU is not at exception level
## load into MMU(3)
li $1, 3
- mtc0 $1, cop0_Index
+ mtc0 $1, c0_index
la $2, entryHi_3
- mtc0 $2, cop0_EntryHi
+ mtc0 $2, c0_entryhi
la $3, entryLo0_3
- mtc0 $3, cop0_EntryLo0
+ mtc0 $3, c0_entrylo0
la $4, entryLo1_3
- mtc0 $4, cop0_EntryLo1
+ mtc0 $4, c0_entrylo1
tlbwi
## check first record was written
ehb
- mtc0 $zero, cop0_EntryHi
- mtc0 $zero, cop0_EntryLo0
- mtc0 $zero, cop0_EntryLo1
+ mtc0 $zero, c0_entryhi
+ mtc0 $zero, c0_entrylo0
+ mtc0 $zero, c0_entrylo1
tlbr # read TLB from index = 3
- mfc0 $23, cop0_EntryHi
+ mfc0 $23, c0_entryhi
sw $23, 0($31)
li $30, '\n'
sw $30, x_IO_ADDR_RANGE($31)
@@ -70,17 +70,17 @@ _start: la $31, x_IO_BASE_ADDR
## load into MMU(2)
addiu $1, $1, -1
- mtc0 $1, cop0_Index
+ mtc0 $1, c0_index
la $5, entryHi_2
- mtc0 $5, cop0_EntryHi
+ mtc0 $5, c0_entryhi
la $6, entryLo0_2
- mtc0 $6, cop0_EntryLo0
+ mtc0 $6, c0_entrylo0
la $7, entryLo1_2
- mtc0 $7, cop0_EntryLo1
+ mtc0 $7, c0_entrylo1
tlbwi
tlbr # read TLB from index = 2
- mfc0 $23, cop0_EntryHi
+ mfc0 $23, c0_entryhi
sw $23, 0($31)
li $30, '\n'
sw $30, x_IO_ADDR_RANGE($31)
@@ -88,25 +88,25 @@ _start: la $31, x_IO_BASE_ADDR
## load into MMU(5)
li $1, 5
- mtc0 $1, cop0_Index
+ mtc0 $1, c0_index
la $8, entryHi_1
- mtc0 $8, cop0_EntryHi
+ mtc0 $8, c0_entryhi
la $9, entryLo0_1
- mtc0 $9, cop0_EntryLo0
+ mtc0 $9, c0_entrylo0
la $10, entryLo1_1
- mtc0 $10, cop0_EntryLo1
+ mtc0 $10, c0_entrylo1
tlbwi
## load into MMU(4)
li $1, 4
- mtc0 $1, cop0_Index
+ mtc0 $1, c0_index
la $11, entryHi_4
- mtc0 $11, cop0_EntryHi
+ mtc0 $11, c0_entryhi
la $12, entryLo0_4
- mtc0 $12, cop0_EntryLo0
+ mtc0 $12, c0_entrylo0
la $13, entryLo1_4
- mtc0 $13, cop0_EntryLo1
+ mtc0 $13, c0_entrylo1
tlbwi
li $30, '\n'
@@ -119,14 +119,14 @@ _start: la $31, x_IO_BASE_ADDR
## make a copy of entryHi_3 and change VPN to force a miss
vpn: la $14, entryHi_3
ori $14, $14, 0x8000 # change VPN w.r.t tlb(3)
- mtc0 $14, cop0_EntryHi
+ mtc0 $14, c0_entryhi
sw $14, 0($31)
ehb # clear all hazards
tlbp # and probe the tlb
- mfc0 $15, cop0_Index # check for bit31=1
+ mfc0 $15, c0_index # check for bit31=1
sw $15, 0($31)
slt $16, $15, $zero # $16 <- (bit31 = 1)
@@ -150,14 +150,14 @@ vpn: la $14, entryHi_3
asid: la $18, entryHi_2
ori $18, $18, 0x88 # change ASID w.r.t tlb(2)
-# mtc0 $18, cop0_EntryHi
+# mtc0 $18, c0_entryhi
# sw $18, 0($31)
# ehb # clear all hazards
# tlbp # and probe the tlb
-# mfc0 $19, cop0_Index # check for bit31=1
+# mfc0 $19, c0_index # check for bit31=1
# sw $19, 0($31)
# slt $20, $19, $zero # $20 <- (bit31 = 1)
@@ -178,14 +178,14 @@ asid: la $18, entryHi_2
## make a copy of entryHi_1 to force a hit
hits: la $18, entryHi_1
- mtc0 $18, cop0_EntryHi
+ mtc0 $18, c0_entryhi
sw $18, 0($31)
ehb # clear all hazards
tlbp # and probe the tlb
- mfc0 $19, cop0_Index # check for bit31=1
+ mfc0 $19, c0_index # check for bit31=1
#sw $19, 0($31)
slt $20, $19, $zero # $20 <- (bit31 = 1)
@@ -209,14 +209,14 @@ hit1: li $30, 'h'
## make a copy of entryHi_4 to force a hit
la $18, entryHi_4
- mtc0 $18, cop0_EntryHi
+ mtc0 $18, c0_entryhi
sw $18, 0($31)
ehb # clear all hazards
tlbp # and probe the tlb
- mfc0 $19, cop0_Index # check for bit31=1
+ mfc0 $19, c0_index # check for bit31=1
#sw $19, 0($31)
slt $20, $19, $zero # $20 <- (bit31 = 1)
diff --git a/cMIPS/tests/mmu_tlbwi.s b/cMIPS/tests/mmu_tlbwi.s
index 50088fa5de8b519b785290cdc0d88845b0ffe5bb..7f10deed3ee659f567a59087fa3c0cbe0e961191 100644
--- a/cMIPS/tests/mmu_tlbwi.s
+++ b/cMIPS/tests/mmu_tlbwi.s
@@ -41,31 +41,31 @@
.ent _start
_start: la $31, x_IO_BASE_ADDR
- li $2, cop0_STATUS_reset
+ li $2, c0_status_reset
addi $2, $2, -2
- mtc0 $2, cop0_STATUS ### make sure CPU is not at exception level
+ mtc0 $2, c0_status ### make sure CPU is not at exception level
li $2, MMU_WIRED
- mtc0 $2, cop0_Wired ### make sure all but 0,1 TLB entries are usable
+ mtc0 $2, c0_wired ### make sure all but 0,1 TLB entries are usable
# load into MMU(3)
li $1, 3
- mtc0 $1, cop0_Index
+ mtc0 $1, c0_index
la $2, entryHi_3
- mtc0 $2, cop0_EntryHi
+ mtc0 $2, c0_entryhi
la $3, entryLo0_3
- mtc0 $3, cop0_EntryLo0
+ mtc0 $3, c0_entrylo0
la $4, entryLo1_3
- mtc0 $4, cop0_EntryLo1
+ mtc0 $4, c0_entrylo1
tlbwi
## check first record was written
ehb
- mtc0 $zero, cop0_EntryHi
- mtc0 $zero, cop0_EntryLo0
- mtc0 $zero, cop0_EntryLo1
+ mtc0 $zero, c0_entryhi
+ mtc0 $zero, c0_entrylo0
+ mtc0 $zero, c0_entrylo1
ehb
@@ -75,11 +75,11 @@ _start: la $31, x_IO_BASE_ADDR
sw $30, x_IO_ADDR_RANGE($31)
read3: tlbr # read TLB at index = 3
- mfc0 $23, cop0_EntryHi
+ mfc0 $23, c0_entryhi
sw $23, 0($31)
- mfc0 $24, cop0_EntryLo0
+ mfc0 $24, c0_entrylo0
sw $24, 0($31)
- mfc0 $25, cop0_EntryLo1
+ mfc0 $25, c0_entrylo1
sw $25, 0($31)
li $30, '\n'
@@ -88,35 +88,35 @@ read3: tlbr # read TLB at index = 3
# load into MMU(4)
li $1, 4
- mtc0 $1, cop0_Index
+ mtc0 $1, c0_index
la $11, entryHi_4
- mtc0 $11, cop0_EntryHi
+ mtc0 $11, c0_entryhi
la $12, entryLo0_4
- mtc0 $12, cop0_EntryLo0
+ mtc0 $12, c0_entrylo0
la $13, entryLo1_4
- mtc0 $13, cop0_EntryLo1
+ mtc0 $13, c0_entrylo1
tlbwi
# load into MMU(2)
li $1, 2
- mtc0 $1, cop0_Index
+ mtc0 $1, c0_index
la $5, entryHi_2
- mtc0 $5, cop0_EntryHi
+ mtc0 $5, c0_entryhi
la $6, entryLo0_2
- mtc0 $6, cop0_EntryLo0
+ mtc0 $6, c0_entrylo0
la $7, entryLo1_2
- mtc0 $7, cop0_EntryLo1
+ mtc0 $7, c0_entrylo1
tlbwi
# load into MMU(5)
li $1, 5
- mtc0 $1, cop0_Index
+ mtc0 $1, c0_index
la $8, entryHi_1
- mtc0 $8, cop0_EntryHi
+ mtc0 $8, c0_entryhi
la $9, entryLo0_1
- mtc0 $9, cop0_EntryLo0
+ mtc0 $9, c0_entrylo0
la $10, entryLo1_1
- mtc0 $10, cop0_EntryLo1
+ mtc0 $10, c0_entrylo1
tlbwi
@@ -129,13 +129,13 @@ read3: tlbr # read TLB at index = 3
li $30, '\n'
sw $30, x_IO_ADDR_RANGE($31)
- mtc0 $1, cop0_Index
+ mtc0 $1, c0_index
tlbr # index = 0
- mfc0 $23, cop0_EntryHi
+ mfc0 $23, c0_entryhi
sw $23, 0($31)
- mfc0 $24, cop0_EntryLo0
+ mfc0 $24, c0_entrylo0
sw $24, 0($31)
- mfc0 $24, cop0_EntryLo1
+ mfc0 $24, c0_entrylo1
sw $24, 0($31)
@@ -146,13 +146,13 @@ read3: tlbr # read TLB at index = 3
li $30, '\n'
sw $30, x_IO_ADDR_RANGE($31)
- mtc0 $1, cop0_Index
+ mtc0 $1, c0_index
tlbr # index = 1
- mfc0 $14, cop0_EntryHi
+ mfc0 $14, c0_entryhi
sw $14, 0($31)
- mfc0 $15, cop0_EntryLo0
+ mfc0 $15, c0_entrylo0
sw $15, 0($31)
- mfc0 $16, cop0_EntryLo1
+ mfc0 $16, c0_entrylo1
sw $16, 0($31)
@@ -163,13 +163,13 @@ read3: tlbr # read TLB at index = 3
li $30, '\n'
sw $30, x_IO_ADDR_RANGE($31)
- mtc0 $1, cop0_Index
+ mtc0 $1, c0_index
tlbr # index = 2
- mfc0 $17, cop0_EntryHi
+ mfc0 $17, c0_entryhi
sw $17, 0($31)
- mfc0 $18, cop0_EntryLo0
+ mfc0 $18, c0_entrylo0
sw $18, 0($31)
- mfc0 $19, cop0_EntryLo1
+ mfc0 $19, c0_entrylo1
sw $19, 0($31)
@@ -180,13 +180,13 @@ read3: tlbr # read TLB at index = 3
li $30, '\n'
sw $30, x_IO_ADDR_RANGE($31)
- mtc0 $1, cop0_Index
+ mtc0 $1, c0_index
tlbr # index = 3
- mfc0 $20, cop0_EntryHi
+ mfc0 $20, c0_entryhi
sw $20, 0($31)
- mfc0 $21, cop0_EntryLo0
+ mfc0 $21, c0_entrylo0
sw $21, 0($31)
- mfc0 $22, cop0_EntryLo1
+ mfc0 $22, c0_entrylo1
sw $22, 0($31)
@@ -197,13 +197,13 @@ read3: tlbr # read TLB at index = 3
li $30, '\n'
sw $30, x_IO_ADDR_RANGE($31)
- mtc0 $1, cop0_Index
+ mtc0 $1, c0_index
tlbr # index = 4
- mfc0 $23, cop0_EntryHi
+ mfc0 $23, c0_entryhi
sw $23, 0($31)
- mfc0 $24, cop0_EntryLo0
+ mfc0 $24, c0_entrylo0
sw $24, 0($31)
- mfc0 $25, cop0_EntryLo1
+ mfc0 $25, c0_entrylo1
sw $25, 0($31)
@@ -214,13 +214,13 @@ read3: tlbr # read TLB at index = 3
li $30, '\n'
sw $30, x_IO_ADDR_RANGE($31)
- mtc0 $1, cop0_Index
+ mtc0 $1, c0_index
tlbr # index = 5
- mfc0 $23, cop0_EntryHi
+ mfc0 $23, c0_entryhi
sw $23, 0($31)
- mfc0 $24, cop0_EntryLo0
+ mfc0 $24, c0_entrylo0
sw $24, 0($31)
- mfc0 $24, cop0_EntryLo1
+ mfc0 $24, c0_entrylo1
sw $24, 0($31)
@@ -256,21 +256,21 @@ read3: tlbr # read TLB at index = 3
# sw $15, 0($31)
- mtc0 $1, cop0_Index
+ mtc0 $1, c0_index
tlbr # index = 6
- mfc0 $23, cop0_EntryHi
+ mfc0 $23, c0_entryhi
# sw $23, 0($31)
bne $23, $13, error
nop
- mfc0 $24, cop0_EntryLo0
+ mfc0 $24, c0_entrylo0
# sw $24, 0($31)
bne $24, $14, error
nop
- mfc0 $25, cop0_EntryLo1
+ mfc0 $25, c0_entrylo1
# sw $25, 0($31)
bne $25, $15, error
@@ -310,21 +310,21 @@ ok6: li $30, 'o'
la $15, MMU_ini_dat_RAM7
# sw $15, 0($31)
- mtc0 $1, cop0_Index
+ mtc0 $1, c0_index
tlbr # index = 7
- mfc0 $23, cop0_EntryHi
+ mfc0 $23, c0_entryhi
# sw $23, 0($31)
bne $23, $13, error
nop
- mfc0 $24, cop0_EntryLo0
+ mfc0 $24, c0_entrylo0
# sw $24, 0($31)
bne $24, $14, error
nop
- mfc0 $25, cop0_EntryLo1
+ mfc0 $25, c0_entrylo1
# sw $25, 0($31)
bne $25, $15, error
diff --git a/cMIPS/tests/mmu_tlbwr.s b/cMIPS/tests/mmu_tlbwr.s
index 6e3fc0c3fd8f490cd3b561111570cb07416bc648..daa657d0a4e338182c1560080bff961799fdc735 100644
--- a/cMIPS/tests/mmu_tlbwr.s
+++ b/cMIPS/tests/mmu_tlbwr.s
@@ -47,59 +47,59 @@
.ent _start
_start: la $31, x_IO_BASE_ADDR
- li $2, cop0_STATUS_reset
+ li $2, c0_status_reset
addi $2, $2, -2
- mtc0 $2, cop0_STATUS ### make sure CPU is not at exception level
+ mtc0 $2, c0_status ### make sure CPU is not at exception level
li $2, MMU_WIRED
- mtc0 $2, cop0_Wired ### make sure all but 0'th TLB entries are usable
+ mtc0 $2, c0_wired ### make sure all but 0'th TLB entries are usable
##
## Initialize TLB with entries that will not match in tests below
##
la $2, entryHi_i
- mtc0 $2, cop0_EntryHi
+ mtc0 $2, c0_entryhi
la $3, entryLo0_i
- mtc0 $3, cop0_EntryLo0
+ mtc0 $3, c0_entrylo0
la $4, entryLo1_i
- mtc0 $4, cop0_EntryLo1
+ mtc0 $4, c0_entrylo1
### do not change mapping for base of ROM at tlb[0] not tlb[1]
li $5, 2
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
tlbwi
addi $2, $2, 0x4000 # increase VPN2
li $5, 3
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
tlbwi
addi $2, $2, 0x4000 # increase VPN2
li $5, 4
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
tlbwi
addi $2, $2, 0x4000 # increase VPN2
li $5, 5
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
tlbwi
addi $2, $2, 0x4000 # increase VPN2
li $5, 6
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
tlbwi
addi $2, $2, 0x4000 # increase VPN2
li $5, 7
- mtc0 $5, cop0_Index
+ mtc0 $5, c0_index
tlbwi
- mfc0 $19, cop0_Random # check for randomness
- mfc0 $20, cop0_Random # check for randomness
- mfc0 $21, cop0_Random # check for randomness
- mfc0 $22, cop0_Random # check for randomness
+ mfc0 $19, c0_random # check for randomness
+ mfc0 $20, c0_random # check for randomness
+ mfc0 $21, c0_random # check for randomness
+ mfc0 $22, c0_random # check for randomness
beq $19, $20, error4
nop
@@ -132,11 +132,11 @@ next4: li $30, '\n'
## write to a random location
la $2, entryHi_3
- mtc0 $2, cop0_EntryHi
+ mtc0 $2, c0_entryhi
la $3, entryLo0_3
- mtc0 $3, cop0_EntryLo0
+ mtc0 $3, c0_entrylo0
la $4, entryLo1_3
- mtc0 $4, cop0_EntryLo1
+ mtc0 $4, c0_entrylo1
tlbwr # write to TLB, ranndom loc
@@ -150,18 +150,18 @@ next4: li $30, '\n'
## make sure it will miss by probing for Entry_0
##
la $5, entryHi_4
- mtc0 $5, cop0_EntryHi
+ mtc0 $5, c0_entryhi
la $5, entryLo0_4
- mtc0 $5, cop0_EntryLo0
+ mtc0 $5, c0_entrylo0
la $5, entryLo1_4
- mtc0 $5, cop0_EntryLo1
+ mtc0 $5, c0_entrylo1
nop
nop
tlbp
- mfc0 $19, cop0_Index # check for bit31=1
+ mfc0 $19, c0_index # check for bit31=1
sw $19, 0($31)
slt $20, $19, $zero # $20 <- (bit31 = 1)
@@ -191,11 +191,11 @@ next2: li $30, '\n'
# write into another randomly selected entry
la $5, entryHi_2
- mtc0 $5, cop0_EntryHi
+ mtc0 $5, c0_entryhi
la $6, entryLo0_2
- mtc0 $6, cop0_EntryLo0
+ mtc0 $6, c0_entrylo0
la $7, entryLo1_2
- mtc0 $7, cop0_EntryLo1
+ mtc0 $7, c0_entrylo1
nop
tlbwr
@@ -208,9 +208,9 @@ next2: li $30, '\n'
## make sure it will miss by probing for entryHi_1
##
la $5, entryHi_1
- mtc0 $5, cop0_EntryHi
- mtc0 $zero, cop0_EntryLo0
- mtc0 $zero, cop0_EntryLo1
+ mtc0 $5, c0_entryhi
+ mtc0 $zero, c0_entrylo0
+ mtc0 $zero, c0_entrylo1
nop
nop
@@ -219,7 +219,7 @@ next2: li $30, '\n'
ehb
- mfc0 $19, cop0_Index # check for bit31=1
+ mfc0 $19, c0_index # check for bit31=1
sw $19, 0($31)
slt $20, $19, $zero # $20 <- (bit31 = 1)
@@ -249,7 +249,7 @@ next1: li $30, '\n'
## now check for last entry written -- must be a hit
la $5, entryHi_2
- mtc0 $5, cop0_EntryHi
+ mtc0 $5, c0_entryhi
nop
nop
@@ -257,7 +257,7 @@ next1: li $30, '\n'
tlbp
- mfc0 $19, cop0_Index # check for bit31=1
+ mfc0 $19, c0_index # check for bit31=1
# sw $19, 0($31)
slt $20, $19, $zero # $20 <- (bit31 = 1)
@@ -282,11 +282,11 @@ next0: li $30, '\n'
## write to a random location
la $2, entryHi_1
- mtc0 $2, cop0_EntryHi
+ mtc0 $2, c0_entryhi
la $3, entryLo0_1
- mtc0 $3, cop0_EntryLo0
+ mtc0 $3, c0_entrylo0
la $4, entryLo1_1
- mtc0 $4, cop0_EntryLo1
+ mtc0 $4, c0_entrylo1
nop
nop
@@ -300,7 +300,7 @@ next0: li $30, '\n'
tlbp
- mfc0 $19, cop0_Index # check for bit31=1
+ mfc0 $19, c0_index # check for bit31=1
# sw $19, 0($31)
slt $20, $19, $zero # $20 <- (bit31 = 1)
diff --git a/cMIPS/tests/mtc0CAUSE2.s b/cMIPS/tests/mtc0CAUSE2.s
index c91bb51ef4c57c7aede9ee0193c5615aff66947f..e59c431a8e232851c939f51a00266126e02ddb7a 100644
--- a/cMIPS/tests/mtc0CAUSE2.s
+++ b/cMIPS/tests/mtc0CAUSE2.s
@@ -7,10 +7,10 @@
.ent _start
_start: nop
li $k0, 0x10000002 # RESET_STATUS, kernel mode, all else disabled
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: ramTop-8
li $k0, 0x0000007c # CAUSE_STATUS, no exceptions
- mtc0 $k0, cop0_CAUSE # clear CAUSE
+ mtc0 $k0, c0_cause # clear CAUSE
nop
j main
nop
@@ -29,12 +29,12 @@ _exit: nop # flush pipeline
.org x_EXCEPTION_0180,0 # exception vector_180
.ent _excp_180
_excp_180:
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
sw $k0,0($15) # print CAUSE
addiu $7,$7,-1
li $k0, 0x10000310 # disable interrupts except SW0,1, user mode
- mtc0 $k0, cop0_STATUS
- mtc0 $zero, cop0_CAUSE # clear CAUSE
+ mtc0 $k0, c0_status
+ mtc0 $zero, c0_cause # clear CAUSE
eret
.end _excp_180
@@ -46,14 +46,14 @@ main: la $15,x_IO_BASE_ADDR
here: sw $5, 0($15)
li $6, 0x10000302 # kernel mode, disable interrupts
- mtc0 $6,cop0_STATUS
+ mtc0 $6,c0_status
li $6, 0x0000ffff # write garbage to CAUSE, assert sw interr 0,1
- mtc0 $6,cop0_CAUSE
+ mtc0 $6,c0_cause
addiu $5,$5,2
li $6, 0x10000311 # user mode, enable sw interrupts
- mtc0 $6,cop0_STATUS
+ mtc0 $6,c0_status
nop
nop
nop
diff --git a/cMIPS/tests/mtc0EPC.s b/cMIPS/tests/mtc0EPC.s
index 449d5fb7ff6f5ca650b580c01dd3e26f32b04aa5..f742f6568b58d39dd521e4e2e07be509799cc390 100644
--- a/cMIPS/tests/mtc0EPC.s
+++ b/cMIPS/tests/mtc0EPC.s
@@ -7,9 +7,9 @@ _start: li $5, 3
li $6, 0x11001100
la $15, x_IO_BASE_ADDR
nop
-lasso: mtc0 $6,cop0_EPC
+lasso: mtc0 $6,c0_epc
addiu $5,$5,-1
- mfc0 $8,cop0_EPC
+ mfc0 $8,c0_epc
sw $8, 0($15)
sll $6,$6,1
bne $5,$0,lasso
diff --git a/cMIPS/tests/mtc0ERET.s b/cMIPS/tests/mtc0ERET.s
index 7f7ce1b3244df61ddd5bd4b317433192d2322335..6eb6168c7047dadb86348069622b11390d5d524b 100644
--- a/cMIPS/tests/mtc0ERET.s
+++ b/cMIPS/tests/mtc0ERET.s
@@ -10,7 +10,7 @@ _start: li $5, 3
nop
li $4, 255
nop
-lasso: mtc0 $6,cop0_EPC
+lasso: mtc0 $6,c0_epc
move $8,$6
sw $8, 0($15)
addiu $5,$5,-1
diff --git a/cMIPS/tests/mtc0MFC0.s b/cMIPS/tests/mtc0MFC0.s
index 879ea3dcb2a5caf19a43044435bdf4c5903a43fb..12b86bfa74a60e6e5067ce0c2036480672df9c9f 100644
--- a/cMIPS/tests/mtc0MFC0.s
+++ b/cMIPS/tests/mtc0MFC0.s
@@ -7,10 +7,10 @@ _start: li $5, 3
li $6, 0x11001100
la $15, x_IO_BASE_ADDR
nop
-lasso: mtc0 $6,cop0_STATUS
+lasso: mtc0 $6,c0_status
ei $8
sw $8, 0($15)
- mfc0 $6,cop0_STATUS
+ mfc0 $6,c0_status
sll $6,$6,1
addiu $5,$5,-1
bne $5,$0,lasso
@@ -22,7 +22,7 @@ lasso: mtc0 $6,cop0_STATUS
lacco: ori $8,$8,1
mtc0 $8,$12
di
- mfc0 $9,cop0_STATUS
+ mfc0 $9,c0_status
addiu $5,$5,-1
sw $9, 56($15)
sll $8,$9,1
diff --git a/cMIPS/tests/nmi.s b/cMIPS/tests/nmi.s
index da31b2a54e7a6bc533aed48bbc66f04534aad1e7..9e1854a4fe2e4951aa4ed9b61ff7eaa0bbcb2eac 100644
--- a/cMIPS/tests/nmi.s
+++ b/cMIPS/tests/nmi.s
@@ -12,12 +12,12 @@
.ent _start
_start: nop
li $k0,0x10000002 # RESET_STATUS, kernel mode, all else disabled
- mtc0 $k0,cop0_STATUS
+ mtc0 $k0,c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: memTop-8
li $k0,0x00000700
- mtc0 $k0,cop0_CAUSE
+ mtc0 $k0,c0_cause
li $k0, 0x1000ff01 # enable interrupts
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
nop
jal main
exit:
@@ -46,7 +46,7 @@ _excp_180:
li $k1, 0x80000100 # restart counter
sw $k1, 0($k0)
li $k0, 0x1000ff01
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
eret
.end excp_180
@@ -55,13 +55,13 @@ _excp_180:
.ent excp_0000
excp_0000:
_excp_0000:
- mfc0 $k0, cop0_STATUS # read STATUS
+ mfc0 $k0, c0_status # read STATUS
sw $k0,0($15) # and print its contents
j nmi_reset_handler
nop
excp_0000ret:
li $k0, 0x1000ff03 # enable interrupts, still in kernel mode
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
eret
nmi_reset_handler: # handler for NMI or soft-reset
diff --git a/cMIPS/tests/overflow.s b/cMIPS/tests/overflow.s
index 75d22a8187f4f4b8cba22ae77210f561a25cd234..a928a947206572013070d86a6533101fa0c56368 100644
--- a/cMIPS/tests/overflow.s
+++ b/cMIPS/tests/overflow.s
@@ -14,9 +14,9 @@
_start: nop
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: ramTop-8
la $k0, main
- mtc0 $k0, cop0_EPC
+ mtc0 $k0, c0_epc
li $k1, 2
- mtc0 $k1, cop0_Wired
+ mtc0 $k1, c0_wired
nop
eret # go into user mode, all else disabled
nop
@@ -35,7 +35,7 @@ _exit: nop # flush pipeline
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -45,7 +45,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -80,18 +80,18 @@ _excp_180:
li $k1, 0x18000008 # disable interrupts, go into user level
- mfc0 $k0, cop0_CAUSE # ovfl was in a delay slot?
+ mfc0 $k0, c0_cause # ovfl was in a delay slot?
srl $k0, $k0, 31 # YES: add 8 to EPC to skip offending add
- mtc0 $k1, cop0_STATUS
+ mtc0 $k1, c0_status
beq $k0, $zero, plus4
- mfc0 $k1, cop0_EPC
+ mfc0 $k1, c0_epc
plus8: j return
addiu $k1, $k1, 8 # fix EPC to jump over 2 instr: branch & add
plus4: addiu $k1, $k1, 4 # fix EPC to jump over offending instruction
-return: mtc0 $k1, cop0_EPC
+return: mtc0 $k1, c0_epc
eret
.end _excp_180
@@ -100,7 +100,7 @@ return: mtc0 $k1, cop0_EPC
_excp_0200:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -110,7 +110,7 @@ _excp_0200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
diff --git a/cMIPS/tests/slt32.s b/cMIPS/tests/slt32.s
index 5f1a0a408d771fdab501830e34af0cf8687b84e8..e9f3dd02b2373797faccc6ddedb284d196a4123a 100644
--- a/cMIPS/tests/slt32.s
+++ b/cMIPS/tests/slt32.s
@@ -8,10 +8,10 @@
.ent _start
_start: nop
li $k0, 0x18000002 # RESET_STATUS, kernel mode, all else disabled
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: ramTop-8
li $k0, 0x0000007c # CAUSE_STATUS, no exceptions
- mtc0 $k0, cop0_CAUSE # clear CAUSE
+ mtc0 $k0, c0_cause # clear CAUSE
nop
jal main
@@ -33,16 +33,16 @@ _exit: nop # flush pipeline
.ent _excp_180
excp_180:
_excp_180:
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
sw $k0, 0($15) # print CAUSE = 0000.0030
sw $k0, 0($15)
sw $k0, 0($15)
li $k0, 0x18000300 # disable interrupts
- mtc0 $k0, cop0_STATUS
- mfc0 $k0, cop0_EPC # skip exception instruction (add)
+ mtc0 $k0, c0_status
+ mfc0 $k0, c0_epc # skip exception instruction (add)
addiu $k0,$k0,4
- mtc0 $k0, cop0_EPC
- mtc0 $zero, cop0_CAUSE # clear CAUSE
+ mtc0 $k0, c0_epc
+ mtc0 $zero, c0_cause # clear CAUSE
eret
.end _excp_180
diff --git a/cMIPS/tests/slt_s_32.s b/cMIPS/tests/slt_s_32.s
index d360b61e81a4ca569293226653626a2e1477f160..ccc5a552c0ecede0e6261374480e16eefefb354f 100644
--- a/cMIPS/tests/slt_s_32.s
+++ b/cMIPS/tests/slt_s_32.s
@@ -9,10 +9,10 @@
.ent _start
_start: nop
li $k0, 0x18000002 # RESET_STATUS, kernel mode, all else disabled
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: ramTop-8
li $k0, 0x0000007c # CAUSE_STATUS, no exceptions
- mtc0 $k0, cop0_CAUSE # clear CAUSE
+ mtc0 $k0, c0_cause # clear CAUSE
nop
jal main
@@ -35,13 +35,13 @@ _exit: nop # flush pipeline
.ent _excp_180
excp_180:
_excp_180:
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
sw $k0, 0($15) # print CAUSE = 0000.0030
sw $k0, 0($15)
sw $k0, 0($15)
li $k0, 0x18000300 # disable interrupts
- mtc0 $k0, cop0_STATUS
- mtc0 $zero, cop0_CAUSE # clear CAUSE
+ mtc0 $k0, c0_status
+ mtc0 $zero, c0_cause # clear CAUSE
eret
.end _excp_180
diff --git a/cMIPS/tests/slt_u_32.s b/cMIPS/tests/slt_u_32.s
index d4e06cabd1b5b986a41dbd8f3e5b1b075e2d0230..9e614d4794ec32304e46615377a41b37867418f0 100644
--- a/cMIPS/tests/slt_u_32.s
+++ b/cMIPS/tests/slt_u_32.s
@@ -9,10 +9,10 @@
.ent _start
_start: nop
li $k0, 0x18000002 # RESET_STATUS, kernel mode, all else disabled
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: ramTop-8
li $k0, 0x0000007c # CAUSE_STATUS, no exceptions
- mtc0 $k0, cop0_CAUSE # clear CAUSE
+ mtc0 $k0, c0_cause # clear CAUSE
nop
jal main
@@ -35,13 +35,13 @@ _exit: nop # flush pipeline
.ent _excp_180
excp_180:
_excp_180:
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
sw $k0, 0($15) # print CAUSE = 0000.0030
sw $k0, 0($15)
sw $k0, 0($15)
li $k0, 0x18000300 # disable interrupts
- mtc0 $k0, cop0_STATUS
- mtc0 $zero, cop0_CAUSE # clear CAUSE
+ mtc0 $k0, c0_status
+ mtc0 $zero, c0_cause # clear CAUSE
eret
.end _excp_180
diff --git a/cMIPS/tests/syscall.s b/cMIPS/tests/syscall.s
index 341a92bf024a7603d7999fdac0ba05bd6723f6f2..60d3412d9ae490c2978b087e0b64bba7427a16c3 100644
--- a/cMIPS/tests/syscall.s
+++ b/cMIPS/tests/syscall.s
@@ -15,7 +15,7 @@ _start: nop
## set STATUS, cop0, no interrupts enabled
li $k0, 0x10000000
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
j main
nop
@@ -35,7 +35,7 @@ _exit: nop # flush pipeline
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -45,7 +45,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -57,21 +57,21 @@ _excp_0100:
.org x_EXCEPTION_0180,0 # exception vector_180
.ent _excp_180
_excp_180:
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
li $k1, 0x18000310 # disable interrupts, user level
sw $k0,0($15) # print CAUSE
- mtc0 $k1, cop0_STATUS
- mfc0 $k0, cop0_EPC # advance EPC to next instruction
+ mtc0 $k1, c0_status
+ mfc0 $k0, c0_epc # advance EPC to next instruction
addi $k0, $k0, 4
addiu $7,$7,-1
- mtc0 $k0, cop0_EPC
+ mtc0 $k0, c0_epc
eret
.end _excp_180
_excp_0200:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -81,7 +81,7 @@ _excp_0200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
diff --git a/cMIPS/tests/teq_jal.s b/cMIPS/tests/teq_jal.s
index 2e9cf9ef0b82643929d23833abaae1f8753d2c92..f6b964937e08b3f17565cfb6c87643b0595b4e97 100644
--- a/cMIPS/tests/teq_jal.s
+++ b/cMIPS/tests/teq_jal.s
@@ -16,7 +16,7 @@ _start: nop
## set STATUS, cop0, no interrupts enabled
li $k0, 0x10000000
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
j main
nop
@@ -35,7 +35,7 @@ _exit: nop # flush pipeline
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -45,7 +45,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -61,7 +61,7 @@ _excp_180:
##
## print CAUSE
##
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
andi $k1, $k0, 0x0030
srl $k1, $k1, 4
addi $k1, $k1, '0'
@@ -72,14 +72,14 @@ _excp_180:
li $k1, '\n'
sw $k1, x_IO_ADDR_RANGE($15)
- mfc0 $k1, cop0_EPC # move EPC beyond the JAL
+ mfc0 $k1, c0_epc # move EPC beyond the JAL
addi $k1, $k1, 8
- mtc0 $k1, cop0_EPC
+ mtc0 $k1, c0_epc
- mfc0 $k0, cop0_STATUS # go back to user mode, EXL=0
+ mfc0 $k0, c0_status # go back to user mode, EXL=0
li $k1, -16 # ffff.fff0
and $k0, $k0, $k1
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
eret
.end _excp_180
@@ -94,7 +94,7 @@ _excp_200:
##
li $28,-1
sw $28, 0($15) # signal exception to std_out
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
li $k1, 'e'
sw $k1, x_IO_ADDR_RANGE($15)
li $k1, 'r'
@@ -112,7 +112,7 @@ _excp_200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
diff --git a/cMIPS/tests/teq_lw.s b/cMIPS/tests/teq_lw.s
index 0a60c182e0e85a6061821b01252b982688965b50..0413df6cc5cd7da859cb9adbe5ad5e5bcdf1d70a 100644
--- a/cMIPS/tests/teq_lw.s
+++ b/cMIPS/tests/teq_lw.s
@@ -16,7 +16,7 @@ _start: nop
## set STATUS, cop0, no interrupts enabled
li $k0, 0x10000000
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
j main
nop
@@ -35,7 +35,7 @@ _exit: nop # flush pipeline
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -45,7 +45,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -61,7 +61,7 @@ _excp_180:
##
## print CAUSE
##
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
andi $k1, $k0, 0x0030
srl $k1, $k1, 4
addi $k1, $k1, '0'
@@ -72,14 +72,14 @@ _excp_180:
li $k1, '\n'
sw $k1, x_IO_ADDR_RANGE($15)
- mfc0 $k1, cop0_EPC # move EPC forward one instruction
+ mfc0 $k1, c0_epc # move EPC forward one instruction
addi $k1, $k1, 4
- mtc0 $k1, cop0_EPC
+ mtc0 $k1, c0_epc
- mfc0 $k0, cop0_STATUS # go back to user mode, EXL=0
+ mfc0 $k0, c0_status # go back to user mode, EXL=0
li $k1, -16 # ffff.fff0
and $k0, $k0, $k1
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
eret
.end _excp_180
@@ -94,7 +94,7 @@ _excp_200:
##
li $28,-1
sw $28, 0($15) # signal exception to std_out
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
li $k1, 'e'
sw $k1, x_IO_ADDR_RANGE($15)
li $k1, 'r'
@@ -112,7 +112,7 @@ _excp_200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
diff --git a/cMIPS/tests/teq_tne.s b/cMIPS/tests/teq_tne.s
index 78b52141d4f8af747dda2dad3f116823b8d92394..c0e9db8f0d42be193e1ec437f0a2da65d28adf8c 100644
--- a/cMIPS/tests/teq_tne.s
+++ b/cMIPS/tests/teq_tne.s
@@ -15,7 +15,7 @@ _start: nop
## set STATUS, cop0, no interrupts enabled
li $k0, 0x10000000
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
j main
nop
@@ -35,7 +35,7 @@ _exit: nop # flush pipeline
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -45,7 +45,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -61,7 +61,7 @@ _excp_180:
##
## print CAUSE, skip over TRAP instruction
##
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
andi $k1, $k0, 0x0030
srl $k1, $k1, 4
addi $k1, $k1, '0'
@@ -74,14 +74,14 @@ _excp_180:
li $5, 0
addiu $7, $7, -1 # decrement iteration control
- mfc0 $k1, cop0_EPC # move EPC forward to next instruction
+ mfc0 $k1, c0_epc # move EPC forward to next instruction
addi $k1, $k1, 4
- mtc0 $k1, cop0_EPC
+ mtc0 $k1, c0_epc
- mfc0 $k0, cop0_STATUS # go back to user mode, EXL=0
+ mfc0 $k0, c0_status # go back to user mode, EXL=0
li $k1, -16 # ffff.fff0
and $k0, $k0, $k1
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
eret
.end _excp_180
@@ -95,7 +95,7 @@ _excp_200:
##
li $28,-1
sw $28, 0($15) # signal WRONG exception to std_out
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
li $k1, 'e'
sw $k1, x_IO_ADDR_RANGE($15)
li $k1, 'r'
@@ -106,9 +106,9 @@ _excp_200:
sw $k1, x_IO_ADDR_RANGE($15)
sw $k0, 0($15) # print CAUSE
- mfc0 $k1, cop0_EPC # move EPC forward to next instruction
+ mfc0 $k1, c0_epc # move EPC forward to next instruction
addi $k1, $k1, 4
- mtc0 $k1, cop0_EPC
+ mtc0 $k1, c0_epc
eret # and return
nop
@@ -118,7 +118,7 @@ _excp_200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
diff --git a/cMIPS/tests/tlt_tlti.s b/cMIPS/tests/tlt_tlti.s
index ab1ae9b6d96a4bd3a622b7349fc9f13d58744330..67818163548e8e214f97536129638b0b321e528e 100644
--- a/cMIPS/tests/tlt_tlti.s
+++ b/cMIPS/tests/tlt_tlti.s
@@ -20,7 +20,7 @@ _start: nop
## set STATUS, cop0, no interrupts enabled
li $k0, 0x10000000
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
j main
nop
@@ -39,7 +39,7 @@ _exit: nop # flush pipeline
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -49,7 +49,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -64,7 +64,7 @@ _excp_0100:
.org x_EXCEPTION_0180,0 # exception vector_180
.ent _excp_180
_excp_180:
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
andi $k1, $k0, 0x0030
srl $k1, $k1, 4
addi $k1, $k1, '0'
@@ -76,14 +76,14 @@ _excp_180:
sw $k1, x_IO_ADDR_RANGE($15)
addiu $7, $7, -1 # decrement iteration control
- mfc0 $k1, cop0_EPC # move EPC forward to next instruction
+ mfc0 $k1, c0_epc # move EPC forward to next instruction
addi $k1, $k1, 4
- mtc0 $k1, cop0_EPC
+ mtc0 $k1, c0_epc
- mfc0 $k0, cop0_STATUS # go back to user mode, EXL=0
+ mfc0 $k0, c0_status # go back to user mode, EXL=0
li $k1, -16 # ffff.fff0
and $k0, $k0, $k1
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
excp_180ret:
eret
.end _excp_180
@@ -97,7 +97,7 @@ excp_180ret:
_excp_200:
li $28,-1
sw $28, 0($15) # signal exception to std_out
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
li $k1, 'e'
sw $k1, x_IO_ADDR_RANGE($15)
li $k1, 'r'
@@ -115,7 +115,7 @@ _excp_200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
diff --git a/cMIPS/tests/tltu_tgeu.s b/cMIPS/tests/tltu_tgeu.s
index 425ed67067e68f49fd918bb86ba9cf8b4c03aac1..64678c2a393c95d858e79e56767a93ea40ca041d 100644
--- a/cMIPS/tests/tltu_tgeu.s
+++ b/cMIPS/tests/tltu_tgeu.s
@@ -17,10 +17,10 @@
_start: nop
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: ramTop-8
- la $k0, cop0_STATUS_reset # go into user mode
+ la $k0, c0_status_reset # go into user mode
addi $k0, $k0, -2
addi $k0, $k0, 0b10000
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
j main
nop
@@ -41,7 +41,7 @@ _exit: nop # flush pipeline
.org x_EXCEPTION_0000,0
_excp_0000:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -51,7 +51,7 @@ _excp_0000:
.org x_EXCEPTION_0100,0
_excp_0100:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
@@ -65,7 +65,7 @@ _excp_0100:
## print CAUSE, reset counter, decrement iteration control
##
_excp_180:
- mfc0 $k0, cop0_CAUSE
+ mfc0 $k0, c0_cause
andi $k1, $k0, 0x0030
srl $k1, $k1, 4
addi $k1, $k1, '0'
@@ -78,12 +78,12 @@ _excp_180:
li $5, 0
addiu $7, $7, -1 # decrement iteration control
- mfc0 $k1, cop0_EPC # move EPC forward to next instruction
+ mfc0 $k1, c0_epc # move EPC forward to next instruction
addi $k1, $k1, 4
- mtc0 $k1, cop0_EPC
- mfc0 $k0, cop0_STATUS # go back into user mode
+ mtc0 $k1, c0_epc
+ mfc0 $k0, c0_status # go back into user mode
ori $k0, $k0, 0x0010
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
excp_180ret:
eret
.end _excp_180
@@ -96,7 +96,7 @@ _excp_200:
##
## this exception should not happen
##
- mfc0 $k0, cop0_CAUSE # signal exception to std_out
+ mfc0 $k0, c0_cause # signal exception to std_out
li $k1, 'e'
sw $k1, x_IO_ADDR_RANGE($15)
li $k1, 'r'
@@ -113,7 +113,7 @@ _excp_200:
.org x_EXCEPTION_BFC0,0
_excp_BFC0:
la $k0, x_IO_BASE_ADDR
- mfc0 $k1, cop0_CAUSE
+ mfc0 $k1, c0_cause
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
diff --git a/cMIPS/tests/wsbh_seb.s b/cMIPS/tests/wsbh_seb.s
index 2cb06b67ff3d23255ece5c64c0f30fedd936a526..63c42a3b983bd699ac828c78da79dd320eb5646a 100644
--- a/cMIPS/tests/wsbh_seb.s
+++ b/cMIPS/tests/wsbh_seb.s
@@ -8,12 +8,12 @@
.ent _start
_start: nop
li $k0,0x10000002 # RESET_STATUS, kernel mode, all else disabled
- mtc0 $k0,cop0_STATUS
+ mtc0 $k0,c0_status
li $sp,(x_DATA_BASE_ADDR+x_DATA_MEM_SZ-8) # initialize SP: memTop-8
li $k0,0x00000000 # nothing happens
- mtc0 $k0,cop0_CAUSE
+ mtc0 $k0,c0_cause
li $k0, 0x1000ff01 # enable interrupts
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
nop
jal main
exit:
@@ -32,12 +32,12 @@ _exit: nop # flush pipeline
.global excp_180
.ent excp_180
excp_180:
- mfc0 $k0, cop0_CAUSE # show cause
+ mfc0 $k0, c0_cause # show cause
sw $k0, 0($15)
li $k1, 0x00000000 # disable SW interrupt
- mtc0 $k1, cop0_CAUSE
+ mtc0 $k1, c0_cause
li $k0, 0x1000ff00 # disable interrupts
- mtc0 $k0, cop0_STATUS
+ mtc0 $k0, c0_status
eret
.end excp_180
diff --git a/cMIPS/vhdl/SDcard.vhd b/cMIPS/vhdl/SDcard.vhd
index ff8a8e61e2d06f44d6c235aa89c8a03f369aecf4..8938a09a39775af66238a3e99e21818f4b363dad 100644
--- a/cMIPS/vhdl/SDcard.vhd
+++ b/cMIPS/vhdl/SDcard.vhd
@@ -304,6 +304,7 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.CommonPckg.all;
use work.SdCardPckg.all;
+use work.p_wires.all;
entity SdCardCtrl is
@@ -367,6 +368,7 @@ begin
PULSE_SCLK, -- Issue some clock pulses. (Must enter with sclk at zero.)
REPORT_ERROR -- Report error and stall until reset.
);
+ attribute SYN_ENCODING of FsmState_t : type is "safe";
variable state_v : FsmState_t := START_INIT; -- Current state of the FSM.
variable rtnState_v : FsmState_t; -- State FSM returns to when FSM subroutine completes.
@@ -752,70 +754,5 @@ begin
hndShk_o <= hndShk_r; -- Output the generated handshake to the host.
end architecture;
-
-
-
-
--- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--- Handshake interface circuit.
---
--- This circuit transforms a control signal into a handshake interface:
--- the source raises the control (ctrl_i), then waits for the done_o
--- to go high, then lowers the control signal, and then the done_o
--- signal goes low. Meanwhile, the control signal that goes to the
--- destination (ctrl_o) is sequenced so that there is no chance
--- of doing a double operation, and the one-cycle done_i signal
--- from the destination is held high by the handshake circuit so the
--- source has a chance to see it.
---
--- ctrl_i _____/--------------------------\_____ (From source...)
--- ctrl_o _____/--------------\_________________ (to destination.)
--- done_i ____________________/--\______________ (From destination...)
--- done_o ____________________/-----------\_____ (to source.)
-
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-library IEEE;
-use IEEE.std_logic_1164.all;
-use work.CommonPckg.all;
--- use work.XessBoardPckg.all;
-
-entity HandshakeIntfc is
- port (
- ctrl_i : in std_logic; -- Control signal from source.
- ctrl_o : out std_logic := LO; -- Control signal to the destination.
- done_i : in std_logic; -- Op done signal from the destination.
- done_o : out std_logic := LO -- Op done signal to the source.
- );
-end entity;
-
-
-architecture arch of HandshakeIntfc is
- signal done_r : std_logic := LO;
-begin
-
- process(ctrl_i, done_i, done_r)
- begin
-
- -- Raise the control to the destination as soon as the source asserts it,
- -- hold it until the destination finishes the operation, and then lower it.
- if ctrl_i = HI and done_i = LO and done_r = LO then
- ctrl_o <= HI;
- elsif done_i = HI or done_r = HI then
- ctrl_o <= LO;
- end if;
-
- -- Tell the source when the destination finishes doing the operation.
- -- Hold the done signal until the source lowers its control signal.
- if ctrl_i = LO then
- done_r <= LO;
- elsif done_i = HI then
- done_r <= HI;
- end if;
-
- end process;
-
- done_o <= done_r;
-
-end architecture;
--- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
diff --git a/cMIPS/vhdl/io.vhd b/cMIPS/vhdl/io.vhd
index ec5534ab0e2cc607450778fce0eb23e10b8bafbe..d622f68e54ef86660a4d402596dfd18be8fd19a5 100644
--- a/cMIPS/vhdl/io.vhd
+++ b/cMIPS/vhdl/io.vhd
@@ -485,7 +485,7 @@ end behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- peripheral: to_7seg
-- input format:
--- b12 b11 b10 b09 b08 b07..b04 b03..b02
+-- b14 b13 b12 b09 b08 b07..b04 b03..b02
-- red gre blu MSdot msdot MSdigit msdigit
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
@@ -506,7 +506,7 @@ entity to_7seg is
green : out std_logic;
blue : out std_logic);
-- 2 decimal points, 2 hex digits, 3 leds
- constant NUM_BITS : integer := 13;
+ constant NUM_BITS : integer := 15;
subtype c_width is std_logic_vector(NUM_BITS - 1 downto 0);
constant INIT_VALUE : c_width := (others => '0');
end to_7seg;
@@ -534,9 +534,9 @@ begin
U_HOLD_data: registerN generic map (NUM_BITS, INIT_VALUE)
port map (clk, rst, sel, data(NUM_BITS-1 downto 0), value);
- red <= value(12);
- green <= value(11);
- blue <= value(10);
+ red <= value(14);
+ green <= value(13);
+ blue <= value(12);
U_DSP1: display_7seg port map (value(7 downto 4), value(9), display1);
@@ -945,12 +945,26 @@ end behavioral;
-- peripheral: SDcard bus interface (a wrapper to the SDcard controller)
-- base + b"0000" -> address register
-- base + b"0100" -> data registers (RD/WR)
--- base + b"1100" -> status register: busy(31) & "0..0" & error(15..0)
+-- base + b"1000" -> control register
+-- base + b"1100" -> status register
--
-- Software must ALWAYS check status(31) = busy before reading/writing
--- to controller. If controller is busy, check for errors. In case of
--- errors, reset controller by writing 0s into status register.
+-- to controller. If controller is not busy, check for errors.
+-- In case of errors, reset controller by writing 0x10 to control register.
-- Wait states (rdy=0) are inserted as needed by the bus interface.
+--
+-- Control register: bit(4)=1 reset the controller (because of error)
+-- bit(1)=1 perform a sector READ
+-- bit(0)=1 perform a sector WRITE
+-- bit(0) and bit(1) shall not be both set
+--
+-- Status register: bit(31)=1 controller is busy (busy_o=1)
+-- bit(30)=1 simultaneous read and write commands
+-- bit(15..0) controller error bits (see SDcard.vhd)
+--
+-- Address register: 32 bits, can be written to, and read from
+--
+-- Data register: data write (sw by CPU), data read (lw by CPU)
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
@@ -990,21 +1004,10 @@ architecture behavioral of SDcard is
Q: out std_logic_vector);
end component registerN;
- component FFD is
- port(clk, rst, set, D : in std_logic; Q : out std_logic);
- end component FFD;
-
component FFDsimple is
port(clk, rst, D : in std_logic; Q : out std_logic);
end component FFDsimple;
- component HandshakeIntfc is
- port (ctrl_i : in std_logic; -- Control signal from source.
- ctrl_o : out std_logic; -- Control signal to the destination.
- done_i : in std_logic; -- Op done signal from the destination.
- done_o : out std_logic); -- Op done signal to the source.
- end component HandshakeIntfc;
-
component SdCardCtrl is
generic (
FREQ_G : real; -- Master clock frequency (MHz).
@@ -1033,47 +1036,95 @@ architecture behavioral of SDcard is
miso_i : in std_logic); -- Serial data input from SD card.
end component SdCardCtrl;
- signal s_addr, s_stat, s_read, s_write, s_reset, sdc_rst : std_logic;
- signal continue, busy, hndShk_i, hndShk_o : std_logic;
- signal wait1, wait2, waiting, new_trans : std_logic;
+ signal s_addr, s_stat, s_ctrl, s_read, s_write : std_logic;
+ signal continue, busy, hndShk_i, hndShk_o, wr_i, rd_i : std_logic;
+ signal wait1, waiting, new_trans, new_data_rd, sdc_rst : std_logic;
+ signal ctrl_err, set_wr_i, clr_wr_i, set_rd_i, clr_rd_i : std_logic;
+ signal do_reset, do_reset1 : std_logic;
signal data_rd, data_rd_reg, data_wr_reg : reg8;
signal error_o : reg16;
signal addr_reg : reg32;
+ signal sel_data_out : reg3;
+ signal w : reg5;
begin
U_SDcard: SdCardCtrl
generic map (50.0, 0.400, 25.0, 512, SD_CARD_E)
- port map (clk, sdc_rst, s_read, s_write, '0', addr_reg,
- data_wr_reg, data_rd, busy, hndshk_i, hndshk_o, error_o,
+ port map (clk, sdc_rst, rd_i, wr_i, '0', addr_reg,
+ data_wr_reg, data_rd, busy, hndshk_i, open, error_o,
+ -- data_wr_reg, data_rd, busy, hndshk_i, hndshk_o, error_o,
sdc_cs, sdc_clk, sdc_mosi_o, sdc_mosi_i);
+
+ hndshk_i <= waiting;
- -- ctrl_i _____/--------------------------\_____ (From source...)
- -- ctrl_o _____/--------------\_________________ (to destination.)
- -- done_i ____________________/--\______________ (From destination...)
- -- done_o ____________________/-----------\_____ (to source.)
- -- port (ctrl_i, ctrl_o, done_i, done_o);
- U_HANDSHAKE: HandshakeIntfc
- port map (new_trans, hndshk_i, hndshk_o, waiting);
+ U_WAIT1: component wait_states generic map (1)
+ port map (rst, clk, new_trans, wait1);
+
+ U_WAIT: process(rst, clk, wait1, hndshk_o)
+ variable w : std_logic;
+ begin
+ if rst = '0' then
+ w := '0';
+ elsif rising_edge(clk) then
+ if wait1 = '1' then -- new transaction started
+ w := '1';
+ end if;
+ if hndshk_o = '1' then -- transaction ended
+ w := '0';
+ end if;
+ end if;
+ waiting <= w;
+ end process U_WAIT;
+
+ rdy <= not(wait1 or waiting); -- wait for 260ns
+ new_data_rd <= not(hndshk_o);
+
+ U_W1: FFDsimple port map (clk, rst, wait1, w(0));
+ U_W2: FFDsimple port map (clk, rst, w(0), w(1));
+ U_W3: FFDsimple port map (clk, rst, w(1), w(2));
+ U_W4: FFDsimple port map (clk, rst, w(2), w(3));
+ U_W5: FFDsimple port map (clk, rst, w(3), w(4));
+ U_W6: FFDsimple port map (clk, rst, w(4), hndshk_o);
- -- a3a2 wr register (aligned to word addresses (a1a0=00)
+ -- a3a2 wr register (aligned to word addresses: a1a0=00)
-- 00 0 write to ADDR register (32 bits)
- -- 00 1 no effect, returns current value of ADDR
+ -- 00 1 returns current value of ADDR
-- 01 1 read from data register (8 bits, least significant byte)
-- 01 0 write to data register (8 bits, least significant byte)
- -- 10 X no effect
- -- 11 0 reset the SDcard constroller (write to status, value ignored)
+ -- 10 0 write to control register
+ -- 10 1 read from control register
+ -- 11 0 no effect (not possible to write to status register)
-- 11 1 read status register
+
+ new_trans <= '0' when addr = b"01" and sel = '0' else '1';
s_addr <= '0' when sel = '0' and addr = b"00" and wr = '0' else '1';
s_write <= '0' when sel = '0' and addr = b"01" and wr = '0' else '1';
s_read <= '0' when sel = '0' and addr = b"01" and wr = '1' else '1';
+ s_ctrl <= '1' when sel = '0' and addr = b"10" and wr = '1' else '0';
+
s_stat <= '1' when sel = '0' and addr = b"11" and wr = '1' else '0';
- s_reset <= '1' when sel = '0' and addr = b"11" and wr = '0' else '0';
- sdc_rst <= not(rst) or s_reset;
+ do_reset <= '1' when s_ctrl = '1' and data_inp(4) = '1' else '0';
+ U_RESET1: FFDsimple port map (clk, rst, do_reset, do_reset1);
+ sdc_rst <= not(rst) or do_reset or do_reset1; -- held for 2 cycles
+
+ -- set_wr_i <= '1' when else '0';
+ -- clr_wr_i <= rst and s_write;
+
+ set_wr_i <= (s_ctrl and data_inp(0)) or (wr_i and s_write);
+ U_WR_STROBE: FFDsimple port map (clk, clr_wr_i, set_wr_i, wr_i);
+
+ -- set_rd_i <= '1' when s_ctrl = '1' and data_inp(1) = '1' else '0';
+ -- clr_rd_i <= rst and s_read;
+ set_rd_i <= (s_ctrl and data_inp(1)) or (rd_i and s_read);
+ U_RD_STROBE: FFDsimple port map (clk, clr_rd_i, set_rd_i, rd_i);
+
+ ctrl_err <= wr_i and rd_i; -- cannot both read AND write
+
U_ADDR_REG: registerN generic map (32, x"00000000")
port map (clk, rst, s_addr, data_inp, addr_reg);
@@ -1081,23 +1132,18 @@ begin
port map (clk, rst, s_write, data_inp(7 downto 0), data_wr_reg);
U_READ_REG: registerN generic map (8, x"00")
- port map (clk, rst, s_read, data_rd, data_rd_reg);
-
- new_trans <= not(s_write) or not(s_read);
+ port map (clk, rst, new_data_rd, data_rd, data_rd_reg);
- U_WAIT1: component wait_states generic map (1)
- port map (rst, clk, new_trans, wait1);
-
- U_WAIT2: FFDsimple port map (clk, rst, wait1, wait2);
-
- rdy <= not(wait1 or wait2 or waiting); -- wait for 260ns
-
- data_out <= x"000000" & data_rd_reg when s_read = '1' else
- busy & b"000" & x"000" & error_o;
+ sel_data_out <= sel & addr;
+
+ with sel_data_out select
+ data_out <= addr_reg when "000",
+ x"000000" & data_rd_reg when "001",
+ x"000000" & b"000" & ctrl_err & b"00" & rd_i & wr_i when "010",
+ busy & ctrl_err & b"00" & x"000" & error_o when "011",
+ (others => 'X') when others;
end behavioral;
--- ++ simple uart +++++++++++++++++++++++++++++++++++++++++++++++++++++++
-
-
+-- ++ SDcard ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
diff --git a/cMIPS/vhdl/tb_cMIPS.vhd b/cMIPS/vhdl/tb_cMIPS.vhd
index 2bdb815fc0f65da4a2e60232f977cea729cc2d3b..bb25ab896a45d68b32c3fa1385eaa93d33bb5c8a 100644
--- a/cMIPS/vhdl/tb_cMIPS.vhd
+++ b/cMIPS/vhdl/tb_cMIPS.vhd
@@ -471,7 +471,7 @@ architecture TB of tb_cMIPS is
-- Macnica development board's peripherals
signal disp0,disp1 : reg8; -- 7 segment displays
- signal keys : reg12; -- 12 key telephone keyboard
+ signal key : reg12; -- 12 key telephone keyboard
signal sw : reg4; -- 4 slide switches
signal led_r, led_g, led_b : std_logic; -- RGB leds (on board signals)
signal LCD_DATA : std_logic_vector(7 downto 0); -- LCD data bus
@@ -525,7 +525,7 @@ begin -- TB
cpu_i_wait <= inst_wait;
cpu_d_wait <= data_wait and io_wait and sdram_wait;
- io_wait <= io_lcd_wait and io_fpu_wait;
+ io_wait <= io_lcd_wait and io_fpu_wait and io_sdc_wait;
not_waiting <= (inst_wait and data_wait and sdram_wait); -- and io_wait);
@@ -580,7 +580,7 @@ begin -- TB
counter_d_out when b"0111",
fpu_d_out when b"1000",
uart_d_out when b"1001",
- -- sstats_d_out when b"1010",
+ -- sstats_d_out when b"1010",
keybd_d_out when b"1100",
lcd_d_out when b"1101",
sdc_d_out when b"1110",
@@ -633,12 +633,12 @@ begin -- TB
port map (rst,clk,io_7seg_sel, wr, cpu_data, disp0, disp1,
led_r, led_g, led_b);
- keys <= b"000000000000", b"000000000100" after 1 us, b"000000000000" after 2 us, b"001000000000" after 3 us, b"000000000000" after 4 us, b"000001000000" after 5 us, b"000000000000" after 6 us;
+ key <= b"000000000000", b"000000000100" after 1 us, b"000000000000" after 2 us, b"001000000000" after 3 us, b"000000000000" after 4 us, b"000001000000" after 5 us, b"000000000000" after 6 us;
sw <= b"0000";
U_read_keys: read_keys
generic map (6) -- debouncing interval, in clock cycles
- port map (rst,clk, io_keys_sel, keybd_d_out, keys, sw);
+ port map (rst,clk, io_keys_sel, keybd_d_out, key, sw);
U_LCD_display: LCD_display
port map (rst, clk, io_lcd_sel, io_lcd_wait,
@@ -809,16 +809,16 @@ begin
dev_select <= b"0001" when (cpu_d_aVal = '0' and in_range) else b"0000";
assert TRUE -- cpu_d_aVal = '1'
- report "e " & SLV32HEX(addr) &
- " addr " & SLV2str(addr(15 downto 0)) & LF &
- " LO_AD " & integer'image(LO_ADDR) &
- " HI_AD " & integer'image(HI_ADDR) &
+ report LF & "e " & SLV32HEX(addr) &
+ " addr " & SLV2str(addr(15 downto 0)) & LF &
+ " LO_AD " & integer'image(LO_ADDR) &
+ " HI_AD " & integer'image(HI_ADDR) &
" a_hi " & SLV2STR(a_hi) &
" a_lo " & SLV2STR(a_lo) &
" a_bits " & SLV2STR(a_bits) &
" a_mask " & SLV32HEX(a_mask) & LF &
- " LO_RAM " & integer'image(LO_RAM) &
- " HI_RAM " & integer'image(HI_RAM) &
+ " LO_RAM " & integer'image(LO_RAM) &
+ " HI_RAM " & integer'image(HI_RAM) &
" r_hi " & SLV2STR(r_hi) &
" r_lo " & SLV2STR(r_lo) &
" r_mask " & SLV32HEX(r_mask)
@@ -851,7 +851,7 @@ architecture behavioral of busError_addr_decode is
-- I/O constants
constant IO_RANGE : integer := IO_ADDR_RANGE * IO_MAX_NUM_DEVS;
constant LO_DEV : natural := 0;
- constant HI_DEV : natural := log2_ceil(IO_RANGE-1);
+ constant HI_DEV : natural := log2_ceil(IO_RANGE);
constant x_hi : std_logic_vector(31 downto HI_DEV) := (others=>'1');
constant x_lo : std_logic_vector(HI_DEV-1 downto 0) := (others=>'0');
@@ -905,14 +905,14 @@ begin
severity NOTE;
assert TRUE -- cpu_d_aVal = '1' and io_busError
- report LF &
- " e " & SLV32HEX(addr) &
- " addr " & SLV2str(addr(15 downto 0)) & LF &
+ report LF &
+ " e " & SLV32HEX(addr) &
+ " addr " & SLV2str(addr(15 downto 0)) & LF &
" x_hi " & SLV2STR(x_hi) &
" x_lo " & SLV2STR(x_lo) &
" x_mask " & SLV32HEX(x_mask) & LF &
- " LO_DEV " & integer'image(LO_DEV) &
- " HI_DEV " & integer'image(HI_DEV)
+ " LO_DEV " & integer'image(LO_DEV) &
+ " HI_DEV " & integer'image(HI_DEV)
severity NOTE;
end architecture behavioral;
@@ -930,7 +930,8 @@ use work.p_wires.all;
use work.p_memory.all;
entity io_addr_decode is -- CPU side triggers access
- port (rst,clk : in std_logic; -- clk sparates back-to-back refs
+ port (rst : in std_logic;
+ clk : in std_logic; -- clk sparates back-to-back refs
cpu_d_aVal : in std_logic; -- CPU data addr valid (active=0)
addr : in reg32; -- CPU address
dev_select : out reg4; -- select input to CPU
@@ -1128,19 +1129,19 @@ begin
dev_select <= b"1110" when (cpu_d_aVal = '0' and in_range) else b"0000";
assert TRUE -- cpu_d_aVal = '1'
- report "e " & SLV32HEX(addr) &
- " addr " & SLV2str(addr(15 downto 0)) & LF &
- " LO_AD " & integer'image(LO_ADDR) &
- " HI_AD " & integer'image(HI_ADDR) &
- " a_hi " & SLV2STR(a_hi) &
- " a_lo " & SLV2STR(a_lo) &
- " a_bits " & SLV2STR(a_bits) &
- " a_mask " & SLV32HEX(a_mask) & LF &
+ report "e " & SLV32HEX(addr) &
+ " addr " & SLV2str(addr(15 downto 0)) & LF &
+ " LO_AD " & integer'image(LO_ADDR) &
+ " HI_AD " & integer'image(HI_ADDR) &
+ " a_hi " & SLV2STR(a_hi) &
+ " a_lo " & SLV2STR(a_lo) &
+ " a_bits " & SLV2STR(a_bits) &
+ " a_mask " & SLV32HEX(a_mask) & LF &
" LO_RAM " & integer'image(LO_RAM) &
" HI_RAM " & integer'image(HI_RAM) &
- " r_hi " & SLV2STR(r_hi) &
- " r_lo " & SLV2STR(r_lo) &
- " r_mask " & SLV32HEX(r_mask)
+ " r_hi " & SLV2STR(r_hi) &
+ " r_lo " & SLV2STR(r_lo) &
+ " r_mask " & SLV32HEX(r_mask)
severity NOTE;
end architecture behavioral;