From 3ef8ae5ee2f010bf319e1965d0746452f43b298d Mon Sep 17 00:00:00 2001
From: Roberto Hexsel <roberto@inf.ufpr.br>
Date: Sun, 10 May 2015 14:14:40 -0300
Subject: [PATCH] edit to README

---
 README | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README b/README
index 8367c9c..497afe9 100644
--- a/README
+++ b/README
@@ -1,6 +1,6 @@
 cMIPS
 
-cMIPS - an FPGA ready VHDL model for 5-stage pipeline, MIPS32r2 core
+cMIPS is a synthesizable VHDL model for the 5-stage pipeline, MIPS32r2 core.
 
 The VHDL model mimics the pipeline design described in Patterson & Hennessy's
 book (Computer Organisation and Design) and is an (almost) complete
-- 
GitLab