diff --git a/cMIPS/tests/mmu_context.expected b/cMIPS/tests/mmu_context.expected
index 6a722397f0b94e55c599e2ce7338cf1fd68cdd99..22bc56696e9a802c937f0f23da1d2eb9f111a898 100644
--- a/cMIPS/tests/mmu_context.expected
+++ b/cMIPS/tests/mmu_context.expected
@@ -1,6 +1,4 @@
-aa000000
 ok
-55800000
 ok
 excp
 ok
diff --git a/cMIPS/tests/mmu_context.s b/cMIPS/tests/mmu_context.s
index 47475794ca447df9dcc1b15fee69f8a55def0128..327df17ab4f6a704e0f34591517c0931c7699305 100644
--- a/cMIPS/tests/mmu_context.s
+++ b/cMIPS/tests/mmu_context.s
@@ -1,7 +1,8 @@
 	##
 	## Test the Context register.
 	##
-	## Write to the upper 9 bits (PTEbase) then read it back
+	## Write to the upper 16 bits (PTEbase) then read it back
+	##   this register is non-compliant so the TP can be set at low addr
 	## 
 	## Cause an exception by referencing an unmapped address and
 	##   then check BadVPN2
@@ -101,13 +102,14 @@ main:	la $31, x_IO_BASE_ADDR
 	## write PTEbase, twice
 	##
 
-	la   $29, 0xaa000000
+	la   $29, 0xaaaf0000		# 16 MS bits
 	mtc0 $29, cop0_Context
 
-	ehb			     # clear hazards
+	ehb				# clear hazards
 	
 	mfc0 $28, cop0_Context
-	sw   $28, 0($31)
+	#sw   $28, 0($31)
+	#sw   $29, 0($31)
 	bne  $28, $29, error1
 	nop
 
@@ -128,19 +130,19 @@ next1:	li $30, '\n'
 	sw $30, x_IO_ADDR_RANGE($31)
 
 	##
-	## check only top 9 bits are written
+	## check only top 16 bits are written
 	##
 
 	move $28, $zero
-	la   $29, 0x55800000         # can write only 9 MS bits
-	mtc0 $29, cop0_Context
+	la   $29, 0x555f0000		# can write only 16 MS bits
+	mtc0 $29, cop0_Context		# must read back 0x555f0000
 
-	ehb			     # clear hazards
+	ehb				# clear hazards
 	
 	mfc0 $28, cop0_Context
-	sw   $28, 0($31)
-	srl  $28, $28, 23	     # keep only 9 MS bits
-	li   $27, 0b010101011        # check 9 MS bits == 0x551--- = 0x-AB
+	#sw   $28, 0($31)
+	srl  $28, $28, 16	     	# keep only 16 MS bits
+	li   $27, 0x555f		# check 16MS bits = 0x555f---- = 0x555f
 	bne  $28, $27, error2
 	nop
 	
@@ -161,7 +163,7 @@ next2:	li $30, '\n'
 
 
 	##
-	## cause a TLB exception and check only bottom 23 bits are written
+	## cause a TLB exception and check only bottom 18 bits are written
 	##   mark first RAM VPN2 as invalid
 	##
 
@@ -179,7 +181,7 @@ next2:	li $30, '\n'
 
 	tlbwi                        # change mapping
 	
-	la   $29, 0xff800000         # can write only 9 MS bits
+	la   $29, 0xffff0000         # can write only 16 MS bits
 	mtc0 $29, cop0_Context
 
 	ehb			     # clear hazards
@@ -202,7 +204,7 @@ next2:	li $30, '\n'
 	mfc0 $28, cop0_Context
 	# sw   $28, 0($31)
 
-	la   $27, 0xff800000 | (x_DATA_BASE_ADDR >>9)
+	la   $27, 0xffff0000 | (x_DATA_BASE_ADDR >>9)
 	bne  $28, $27, error3
 	nop
 	
diff --git a/cMIPS/vhdl/core.vhd b/cMIPS/vhdl/core.vhd
index 712327925ac006f0150fa7727a2c2779ee09b842..537bf2901ba2d5de0120d4e09878fd126c0c8add 100644
--- a/cMIPS/vhdl/core.vhd
+++ b/cMIPS/vhdl/core.vhd
@@ -2504,16 +2504,17 @@ begin
   -- MMU_ContextPTE: registerN generic map(9, ContextPTE_init)
   --   port map (clk, rst, context_upd_pte,
   --             cop0_inp(31 downto 23), Context(31 downto 23));
-  MMU_ContextPTE: registerN generic map(14, b"00000000000000")
+  MMU_ContextPTE: registerN generic map(16, b"0000000000000000")
     port map (clk, rst, context_upd_pte,
-              cop0_inp(31 downto 18), Context(31 downto 18));
+              cop0_inp(31 downto 16), Context(31 downto 16));
 
   context_upd_bad <= '0' when MM_tlb_exception else '1';
   
   -- MMU_ContextBAD: registerN generic map(19, b"0000000000000000000")
   --   port map (clk, rst, context_upd_bad, tlb_context_inp, Context(22 downto 4));
-  MMU_ContextBAD: registerN generic map(14, b"00000000000000")
-    port map (clk, rst, context_upd_bad, tlb_excp_VA(VA_HI_BIT-5 downto VA_LO_BIT), Context(17 downto 4));
+  MMU_ContextBAD: registerN generic map(12, b"000000000000")
+    port map (clk, rst, context_upd_bad,
+              tlb_excp_VA(VA_HI_BIT-7 downto VA_LO_BIT), Context(15 downto 4));
 
   Context(3 downto 0) <= b"0000";