diff --git a/cMIPS/vhdl/core.vhd b/cMIPS/vhdl/core.vhd
index 9c60723176f2e255464708010fb3e581f379d44d..28e6f9b5743c428bf2737b07e2ec0b9097a7a8d6 100644
--- a/cMIPS/vhdl/core.vhd
+++ b/cMIPS/vhdl/core.vhd
@@ -150,7 +150,7 @@ architecture rtl of core is
   signal TLB_excp_type, MM_TLB_excp_type : exception_type;
   signal trap_instr,EX_trap_instr: instr_type;
   signal RF_PC,EX_PC,MM_PC,WB_PC, LLaddr: reg32;
-  signal MM_LLbit,WB_LLbit: std_logic;
+  signal ll_sc_bit, MM_LLbit,WB_LLbit: std_logic;
   signal LL_update,LL_SC_abort,LL_SC_differ: std_logic;
   signal EX_trapped, MM_trapped, EX_ovfl,MM_ex_ovfl, trap_taken: boolean;
   signal int_req, MM_int_req: reg8;
@@ -1391,8 +1391,8 @@ begin
   U_dmem_stalled: FFD port map (clk => phi2, rst => rst, set => '1',
                                 D => stalled, Q => mm_stalled);
 
-  d_aVal <= MM_aVal;  -- interface signal/port
-  daVal  <= MM_aVal;  -- internal signal
+  d_aVal <= MM_aVal or LL_SC_abort;  -- interface signal/port
+  daVal  <= MM_aVal or LL_SC_abort;  -- internal signal
   
   ram_stall <= not(daVal) and not(d_wait);
   -- end DATA_BUS_STATE_MACHINE -------------------------------------
@@ -2360,7 +2360,7 @@ begin
   COP0_LLaddr: register32 generic map(x"00000000")
     port map (clk, rst, LL_update, MM_result, LLaddr);
 
-  LL_SC_differ <= '0' when (MM_result = LLaddr) else '1';
+  LL_SC_differ <= '0' when (MM_v_addr = LLaddr) else '1';
 
   LL_SC_abort  <= (LL_SC_differ or not(MM_LLbit)) when (is_exception = exSC)
                   else '0';
@@ -2368,19 +2368,21 @@ begin
   COP0_LLbit: process(rst,clk)
   begin
     if rst = '0' then
-      MM_LLbit    <= '0';             -- break SC -> LL
+      ll_sc_bit <= '0';
     elsif rising_edge(clk) then
       case is_exception is
         when exERET =>
-          MM_LLbit <= '0';            -- break SC -> LL
+          ll_sc_bit <= '0';            -- break SC -> LL
         when exLL =>
-          MM_LLbit <= not LL_update;  -- update only if instr is a LL
+          ll_sc_bit <= not LL_update;  -- update only if instr is a LL
         when others =>
           null;
       end case;
+
     end if;
   end process COP0_LLbit;
-  
+
+  MM_llbit <= ll_sc_bit and not(LL_SC_abort);  
 
   
   -- MMU-TLB ===============================================================