diff --git a/cMIPS/vhdl/altera.vhd b/cMIPS/vhdl/altera.vhd
index 928586d3ef9903a81e01e13430d7c6da7df7fbde..0a0aa13a996b5733ad367f4129ffb16d6489f738 100644
--- a/cMIPS/vhdl/altera.vhd
+++ b/cMIPS/vhdl/altera.vhd
@@ -174,6 +174,29 @@ end architecture rtl;
-- -----------------------------------------------------------------------
+
+-- fake ROM megafunction = not used in simulation, only on the FPGA ------
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.p_wires.all;
+use work.p_memory.all;
+
+entity alt_mf_rom is port (
+ address : IN STD_LOGIC_VECTOR ((INST_ADDRS_BITS-1) DOWNTO 0);
+ clken : IN STD_LOGIC := '1';
+ clock : IN STD_LOGIC := '1';
+ q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
+end alt_mf_rom;
+
+architecture fake of alt_mf_rom is
+begin -- fake
+ q <= (others => 'X');
+end fake;
+-- -----------------------------------------------------------------------
+
+
+
-- PLL for CPU clocks ----------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
diff --git a/cMIPS/vhdl/cache.vhd b/cMIPS/vhdl/cache.vhd
index 27602ec90ec56bc1c5b6deaaaf066d4341414d76..eb8c7c6848bf293a82ba827f3441d312887cc716 100644
--- a/cMIPS/vhdl/cache.vhd
+++ b/cMIPS/vhdl/cache.vhd
@@ -398,34 +398,7 @@ end behavioral;
-- fake data cache -- pass along all signals unchanged
-- TODO:
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-library IEEE;
-use IEEE.std_logic_1164.all;
-use work.p_wires.all;
-
-entity fake_D_CACHE is
- port (rst : in std_logic;
- clk4x : in std_logic;
- cpu_sel : in std_logic; -- active in '0'
- cpu_rdy : out std_logic; -- active in '0'
- cpu_wr : in std_logic; -- active in '0'
- cpu_addr : in std_logic_vector;
- cpu_data_inp : in reg32; -- data from CPU
- cpu_data_out : out reg32; -- data to CPU
- cpu_xfer : in std_logic_vector;
- mem_sel : out std_logic; -- active in '0'
- mem_rdy : in std_logic; -- active in '0'
- mem_wr : out std_logic; -- active in '0'
- mem_addr : out std_logic_vector;
- mem_data_inp : in reg32; -- data from memory
- mem_data_out : out reg32; -- data to memory
- mem_xfer : out std_logic_vector;
- ref_cnt : out integer;
- rd_hit_cnt : out integer;
- wr_hit_cnt : out integer;
- flush_cnt : out integer);
-end entity fake_D_CACHE;
-
-architecture behavioral of fake_D_CACHE is
+architecture fake of D_CACHE is
begin
mem_sel <= cpu_sel;
cpu_rdy <= mem_rdy;
@@ -443,7 +416,7 @@ begin
rd_hit_cnt <= 0;
wr_hit_cnt <= 0;
flush_cnt <= 0;
-end behavioral;
+end fake;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
@@ -696,27 +669,7 @@ end behavioral;
-- fake instruction cache -- pass along all signals unchanged
-- TODO:
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-library IEEE;
-use IEEE.std_logic_1164.all;
-use work.p_wires.all;
-
-entity fake_I_CACHE is
- port (rst : in std_logic;
- clk4x : in std_logic;
- ic_reset : out std_logic; -- active in '0'
- cpu_sel : in std_logic; -- active in '0'
- cpu_rdy : out std_logic; -- active in '0'
- cpu_addr : in reg32;
- cpu_data : out reg32;
- mem_sel : out std_logic; -- active in '0'
- mem_rdy : in std_logic; -- active in '0'
- mem_addr : out reg32;
- mem_data : in reg32;
- ref_cnt : out integer;
- hit_cnt : out integer);
-end entity fake_I_CACHE;
-
-architecture behavioral of fake_I_CACHE is
+architecture fake of I_CACHE is
begin
ic_reset <= '1';
mem_sel <= cpu_sel;
@@ -726,5 +679,5 @@ begin
ref_cnt <= 0;
hit_cnt <= 0;
-end behavioral;
+end fake;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
diff --git a/cMIPS/vhdl/fpu.vhd b/cMIPS/vhdl/fpu.vhd
index 452e5eb60aea6779ebd7ff5463d5b2e4a3c4fbdc..229a619db82a8b6016f48e1dc898e80c6dd6887a 100644
--- a/cMIPS/vhdl/fpu.vhd
+++ b/cMIPS/vhdl/fpu.vhd
@@ -105,6 +105,9 @@ begin
-- denormB <= '0' when to_integer(unsigned(in_b(30 downto 23))) = 0 else '1';
end estrutural;
+--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
--+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
@@ -200,6 +203,8 @@ begin
end process check_sig;
end estrutural;
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
@@ -414,8 +419,6 @@ end estrutural;
-
-
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
@@ -784,6 +787,7 @@ end estrutural;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- FPU
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
@@ -802,7 +806,7 @@ entity FPU is
data_out : out reg32);
end FPU;
-architecture estrutural of FPU is
+architecture rtl of FPU is
component wait_states is
generic (NUM_WAIT_STATES :integer);
@@ -892,30 +896,17 @@ begin
RES_SUM when selC_sum = '1' else
(others => 'X');
--RES_DIV when selC_div = '1' else
-end estrutural;
+end rtl;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- fake_FPU
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-library IEEE;
-use IEEE.std_logic_1164.all;
-use work.p_wires.all;
-
-entity fake_FPU is
- port(rst : in std_logic;
- clk : in std_logic;
- sel : in std_logic;
- rdy : out std_logic;
- wr : in std_logic;
- addr : in std_logic_vector;
- data_inp : in reg32;
- data_out : out reg32);
-end fake_FPU;
-
-architecture estrutural of fake_FPU is
+architecture fake of FPU is
begin
rdy <= '1';
data_out <= (others => 'X');
-end estrutural;
+end architecture fake;
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
diff --git a/cMIPS/vhdl/macnica.vhd b/cMIPS/vhdl/macnica.vhd
index 8ed0a07585132026023ef9ca93f9d3cecde48b0d..710a1120a0be9b30248415a6ce68a73df2b105c1 100644
--- a/cMIPS/vhdl/macnica.vhd
+++ b/cMIPS/vhdl/macnica.vhd
@@ -1,3 +1,24 @@
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
+-- Copyright (C) 2013 Roberto Andre Hexsel
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, version 3.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+--
+-- The components below were adapted from Macnica's Mercurio IV lab material
+--
-- ---------------------------------------------------------
@@ -146,3 +167,4 @@ begin -- rtl
end rtl;
-- ----------------------------------------------------------------------
+
diff --git a/cMIPS/vhdl/memory.vhd b/cMIPS/vhdl/memory.vhd
deleted file mode 100644
index 642eebe8ab02f3ae8434b68d0792c2cc74e4c0a3..0000000000000000000000000000000000000000
--- a/cMIPS/vhdl/memory.vhd
+++ /dev/null
@@ -1,330 +0,0 @@
--- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
--- Copyright (C) 2013 Roberto Andre Hexsel
---
--- This program is free software: you can redistribute it and/or modify
--- it under the terms of the GNU General Public License as published by
--- the Free Software Foundation, version 3.
---
--- This program is distributed in the hope that it will be useful,
--- but WITHOUT ANY WARRANTY; without even the implied warranty of
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--- GNU General Public License for more details.
---
--- You should have received a copy of the GNU General Public License
--- along with this program. If not, see <http://www.gnu.org/licenses/>.
--- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-
-
--- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--- syncronous ROM; MIPS executable loaded into ROM at CPU reset, wd-indexed
--- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use std.textio.all;
-use work.p_wires.all;
-use work.p_memory.all;
-
-entity simul_ROM is
- generic (LOAD_FILE_NAME : string := "prog.bin");
- port (rst : in std_logic;
- clk : in std_logic;
- sel : in std_logic; -- active in '0'
- rdy : out std_logic; -- active in '0'
- strobe : in std_logic;
- addr : in reg32;
- data : out reg32);
- constant INST_ADDRS_BITS : natural := log2_ceil(INST_MEM_SZ);
-end entity simul_ROM;
-
-architecture behavioral of simul_ROM is
-
- component wait_states is
- generic (NUM_WAIT_STATES :integer := 0);
- port(rst : in std_logic;
- clk : in std_logic;
- sel : in std_logic; -- active in '0'
- waiting : out std_logic); -- active in '1'
- end component wait_states;
-
- component FFT is
- port(clk, rst, T : in std_logic; Q : out std_logic);
- end component FFT;
-
- constant WAIT_COUNT : max_wait_states := (NUM_MAX_W_STS - ROM_WAIT_STATES);
- constant WAIT_FOR : reg10 := std_logic_vector(to_signed(WAIT_COUNT, 10));
-
- signal waiting, do_wait : std_logic;
-
-begin -- behavioral
-
- U_BUS_WAIT: wait_states generic map (ROM_WAIT_STATES)
- port map (rst, clk, sel, waiting);
-
- rdy <= not(waiting);
-
- U_ROM: process (rst, sel, strobe, addr)
-
- subtype t_address is unsigned((INST_ADDRS_BITS - 1) downto 0);
- variable u_addr : t_address;
-
- subtype word is std_logic_vector(data'length - 1 downto 0);
- type storage_array is
- array( natural range 0 to (INST_MEM_SZ - 1) ) of word;
- variable storage : storage_array;
- variable index, latched : natural;
-
- type binary_file is file of integer;
- file load_file: binary_file open read_mode is LOAD_FILE_NAME;
- variable instr: integer; -- := to_integer(unsigned(NULL_INSTRUCTION));
- variable s_instr : signed(31 downto 0);
-
- begin
-
- if rst = '0' then -- reset, read binary executable
-
- index := 0; -- indexed by word
- for i in 0 to (INST_MEM_SZ - 1) loop
-
- if not endfile(load_file) then
- read(load_file, instr);
- s_instr := to_signed(instr, 32);
- -- assert false report "romINIT["& natural'image(index*4) &"]= " &
- -- SLV32HEX(std_logic_vector(s_instr)); -- DEBUG
- storage(index) := std_logic_vector(s_instr);
- index := index + 1;
- end if;
-
- end loop; -- i
-
- else -- normal operation
-
- u_addr := unsigned(addr((2+(INST_ADDRS_BITS-1)) downto 2)); -- >>2 = /4
- index := to_integer(u_addr); -- indexed by word, not by byte
-
- assert (index >= 0) and (index < INST_MEM_SZ/4)
- report "romRDindex out of bounds: " & SLV32HEX(addr) & " = " &
- natural'image(index) severity warning; -- failure;
-
- if sel = '0' and rising_edge(strobe) then
- latched := index;
- end if;
-
- if sel = '0' then
- data <= storage(latched);
- -- assert false -- DEBUG
- -- report "romRD["& natural'image(index) &"]="& SLV32HEX(storage(index));
- else
- data <= (others => 'X');
- end if;
-
- end if;
-
- end process;
-
-end behavioral;
--- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-
-
-
--- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--- syncronous RAM; initialization Data loaded at CPU reset, byte-indexed
--- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-use std.textio.all;
-use work.p_wires.all;
-use work.p_memory.all;
-
-entity simul_RAM is
- generic (LOAD_FILE_NAME : string := "data.bin";
- DUMP_FILE_NAME : string := "dump.data");
- port (rst : in std_logic;
- clk : in std_logic;
- sel : in std_logic; -- active in '0'
- rdy : out std_logic; -- active in '0'
- wr : in std_logic;
- strobe : in std_logic;
- addr : in reg32;
- data_inp : in reg32;
- data_out : out reg32;
- byte_sel : in reg4;
- dump_ram : in std_logic); -- dump RAM contents
- constant DATA_ADDRS_BITS : natural := log2_ceil(DATA_MEM_SZ);
-end entity simul_RAM;
-
-architecture behavioral of simul_RAM is
-
- component wait_states is
- generic (NUM_WAIT_STATES :integer := 0);
- port(rst : in std_logic;
- clk : in std_logic;
- sel : in std_logic; -- active in '0'
- waiting : out std_logic); -- active in '1'
- end component wait_states;
-
- component FFT is
- port(clk, rst, T : in std_logic; Q : out std_logic);
- end component FFT;
-
- constant WAIT_COUNT : max_wait_states := NUM_MAX_W_STS - RAM_WAIT_STATES;
- signal wait_counter, ram_current : integer;
-
- subtype t_address is unsigned((DATA_ADDRS_BITS - 1) downto 0);
-
- subtype word is std_logic_vector(7 downto 0);
- type storage_array is
- array (natural range 0 to (DATA_MEM_SZ - 1)) of word;
- signal storage : storage_array;
-
- signal enable, waiting, do_wait : std_logic;
-
-begin -- behavioral
-
- U_BUS_WAIT: wait_states generic map (RAM_WAIT_STATES)
- port map (rst, clk, sel, waiting);
-
- rdy <= not(waiting);
-
- enable <= not(sel); -- and not(waiting);
-
-
- accessRAM: process(strobe,enable, wr,rst, addr,byte_sel, data_inp,dump_ram)
- variable u_addr : t_address;
- variable index, latched : natural;
-
- type binary_file is file of integer;
- file load_file: binary_file open read_mode is LOAD_FILE_NAME;
- variable datum: integer;
- variable s_datum: signed(31 downto 0);
-
- file dump_file: binary_file open write_mode is DUMP_FILE_NAME;
-
- variable d : reg32 := (others => 'X');
- variable val, i : integer;
-
- begin
-
- if rst = '0' then -- reset, read-in binary initialized data
-
- index := 0; -- byte indexed
-
- for i in 0 to (DATA_MEM_SZ - 1) loop
-
- if not endfile(load_file) then
-
- read(load_file, datum);
- s_datum := to_signed(datum, 32);
- -- assert false report "ramINIT["& natural'image(index*4)&"]= " &
- -- SLV32HEX(std_logic_vector(s_datum)); -- DEBUG
- storage(index+3) <= std_logic_vector(s_datum(31 downto 24));
- storage(index+2) <= std_logic_vector(s_datum(23 downto 16));
- storage(index+1) <= std_logic_vector(s_datum(15 downto 8));
- storage(index+0) <= std_logic_vector(s_datum(7 downto 0));
- index := index + 4;
- end if;
- end loop;
-
- data_out <= (others=>'X');
-
- else -- (rst = '1'), normal operation
-
- -- to simplify (and accelerate) internal address decoding,
- -- the BASE of the RAM addresses MUST be allocated at an
- -- address that is larger the RAM capacity. Otherwise, the
- -- base must be subtracted from the address on every reference,
- -- which means having an adder in the critical path. Bad idea.
-
- u_addr := unsigned(addr( (DATA_ADDRS_BITS-1) downto 0 ) );
- index := to_integer(u_addr);
-
- if sel = '0' and wr = '0' and rising_edge(strobe) then
-
- assert (index >= 0) and (index < DATA_MEM_SZ)
- report "ramWR index out of bounds: " & natural'image(index)
- severity failure;
-
- case byte_sel is
- when b"1111" => -- SW
- storage(index+3) <= data_inp(31 downto 24);
- storage(index+2) <= data_inp(23 downto 16);
- storage(index+1) <= data_inp(15 downto 8);
- storage(index+0) <= data_inp(7 downto 0);
- when b"1100" | b"0011" => -- SH
- storage(index+1) <= data_inp(15 downto 8);
- storage(index+0) <= data_inp(7 downto 0);
- when b"0001" | b"0010" | b"0100" | b"1000" => -- SB
- storage(index+0) <= data_inp(7 downto 0);
- when others => null;
- end case;
- -- assert false report "ramWR["& natural'image(index) &"] "
- -- & SLV32HEX(data) &" bySel=" & SLV2STR(byte_sel); -- DEBUG
- end if; -- is write?
-
- if sel = '0' and wr = '1' then
-
- assert (index >= 0) and (index < DATA_MEM_SZ)
- report "ramRD index out of bounds: " & natural'image(index)
- severity failure;
-
- case byte_sel is
- when b"1111" => -- LW
- d(31 downto 24) := storage(index+3);
- d(23 downto 16) := storage(index+2);
- d(15 downto 8) := storage(index+1);
- d(7 downto 0) := storage(index+0);
- when b"1100" => -- LH top-half
- d(31 downto 24) := storage(index+1);
- d(23 downto 16) := storage(index+0);
- d(15 downto 0) := (others => 'X');
- when b"0011" => -- LH bottom-half
- d(31 downto 16) := (others => 'X');
- d(15 downto 8) := storage(index+1);
- d(7 downto 0) := storage(index+0);
- when b"0001" => -- LB top byte
- d(31 downto 8) := (others => 'X');
- d(7 downto 0) := storage(index+0);
- when b"0010" => -- LB mid-top byte
- d(31 downto 16) := (others => 'X');
- d(15 downto 8) := storage(index+0);
- d(7 downto 0) := (others => 'X');
- when b"0100" => -- LB mid-bot byte
- d(31 downto 24) := (others => 'X');
- d(23 downto 16) := storage(index+0);
- d(15 downto 0) := (others => 'X');
- when b"1000" => -- LB bottom byte
- d(31 downto 24) := storage(index+0);
- d(23 downto 0) := (others => 'X');
- when others => d := (others => 'X');
- end case;
- -- assert false report "ramRD["& natural'image(index) &"] "
- -- & SLV32HEX(d) &" bySel="& SLV2STR(byte_sel); -- DEBUG
-
- elsif rising_edge(dump_ram) then
-
- i := 0;
- while i < DATA_MEM_SZ-4 loop
- d(31 downto 24) := storage(i+3);
- d(23 downto 16) := storage(i+2);
- d(15 downto 8) := storage(i+1);
- d(7 downto 0) := storage(i+0);
- write( dump_file, to_integer(signed(d)) );
- i := i+4;
- end loop; -- i
-
- else
- d := (others=>'X');
- end if; -- is read?
-
- data_out <= d;
-
- end if; -- is reset?
-
- end process accessRAM; -- ---------------------------------------------
-
-
-end behavioral;
--- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-
diff --git a/cMIPS/vhdl/packageMemory.vhd b/cMIPS/vhdl/packageMemory.vhd
index 4a3341ccd280d12b643f785053f1408a65ccf89c..16752497dbaeb26a2f02e04d5453bc4c8f7ef85b 100644
--- a/cMIPS/vhdl/packageMemory.vhd
+++ b/cMIPS/vhdl/packageMemory.vhd
@@ -58,8 +58,11 @@ package p_MEMORY is
constant INST_BASE_ADDR : integer := to_integer(signed(x_INST_BASE_ADDR));
constant INST_MEM_SZ : integer := to_integer(signed(x_INST_MEM_SZ));
+ constant INST_ADDRS_BITS : natural := log2_ceil(INST_MEM_SZ);
+
constant DATA_BASE_ADDR : integer := to_integer(signed(x_DATA_BASE_ADDR));
constant DATA_MEM_SZ : integer := to_integer(signed(x_DATA_MEM_SZ));
+
constant IO_BASE_ADDR : integer := to_integer(signed(x_IO_BASE_ADDR));
constant IO_MEM_SZ : integer := to_integer(signed(x_IO_MEM_SZ));
constant IO_ADDR_RANGE : integer := to_integer(signed(x_IO_ADDR_RANGE));
diff --git a/cMIPS/vhdl/ram.vhd b/cMIPS/vhdl/ram.vhd
index c1453e828586da9b5511bd022e178599f60b5bb8..fc40895b8f03e909cbc4db2ded482d2afbc5bd6f 100644
--- a/cMIPS/vhdl/ram.vhd
+++ b/cMIPS/vhdl/ram.vhd
@@ -26,7 +26,7 @@ use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
-entity fpga_RAM is
+entity RAM is
generic (LOAD_FILE_NAME : string := "data.bin";
DUMP_FILE_NAME : string := "dump.data");
port (rst : in std_logic;
@@ -40,13 +40,18 @@ entity fpga_RAM is
data_out : out reg32;
byte_sel : in reg4;
dump_ram : in std_logic); -- dump RAM contents
+
+ -- simulation version
+ constant DATA_ADDRS_BITS : natural := log2_ceil(DATA_MEM_SZ);
+
+ -- FPGA version
constant N_WORDS : natural := 8192;
constant ADDRS_BITS : natural := log2_ceil(N_WORDS);
subtype ram_address is integer range 0 to N_WORDS-1;
subtype ram_addr_bits is std_logic_vector(ADDRS_BITS-1 downto 0);
-end entity fpga_RAM;
+end entity RAM;
-architecture rtl of fpga_RAM is
+architecture rtl of RAM is
component mf_ram1port
generic (N_WORDS : integer; ADDRS_BITS : integer);
@@ -215,3 +220,184 @@ begin -- rtl
end architecture rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+
+
+
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+-- syncronous RAM; initialization Data loaded at CPU reset, byte-indexed
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+architecture simulation of RAM is
+
+ component wait_states is
+ generic (NUM_WAIT_STATES :integer := 0);
+ port(rst : in std_logic;
+ clk : in std_logic;
+ sel : in std_logic; -- active in '0'
+ waiting : out std_logic); -- active in '1'
+ end component wait_states;
+
+ component FFT is
+ port(clk, rst, T : in std_logic; Q : out std_logic);
+ end component FFT;
+
+ constant WAIT_COUNT : max_wait_states := NUM_MAX_W_STS - RAM_WAIT_STATES;
+ signal wait_counter, ram_current : integer;
+
+ subtype t_address is unsigned((DATA_ADDRS_BITS - 1) downto 0);
+
+ subtype word is std_logic_vector(7 downto 0);
+ type storage_array is
+ array (natural range 0 to (DATA_MEM_SZ - 1)) of word;
+ signal storage : storage_array;
+
+ signal enable, waiting, do_wait : std_logic;
+
+begin -- simulation
+
+ U_BUS_WAIT: wait_states generic map (RAM_WAIT_STATES)
+ port map (rst, clk, sel, waiting);
+
+ rdy <= not(waiting);
+
+ enable <= not(sel); -- and not(waiting);
+
+
+ accessRAM: process(strobe,enable, wr,rst, addr,byte_sel, data_inp,dump_ram)
+ variable u_addr : t_address;
+ variable index, latched : natural;
+
+ type binary_file is file of integer;
+ file load_file: binary_file open read_mode is LOAD_FILE_NAME;
+ variable datum: integer;
+ variable s_datum: signed(31 downto 0);
+
+ file dump_file: binary_file open write_mode is DUMP_FILE_NAME;
+
+ variable d : reg32 := (others => 'X');
+ variable val, i : integer;
+
+ begin
+
+ if rst = '0' then -- reset, read-in binary initialized data
+
+ index := 0; -- byte indexed
+
+ for i in 0 to (DATA_MEM_SZ - 1) loop
+
+ if not endfile(load_file) then
+
+ read(load_file, datum);
+ s_datum := to_signed(datum, 32);
+ -- assert false report "ramINIT["& natural'image(index*4)&"]= " &
+ -- SLV32HEX(std_logic_vector(s_datum)); -- DEBUG
+ storage(index+3) <= std_logic_vector(s_datum(31 downto 24));
+ storage(index+2) <= std_logic_vector(s_datum(23 downto 16));
+ storage(index+1) <= std_logic_vector(s_datum(15 downto 8));
+ storage(index+0) <= std_logic_vector(s_datum(7 downto 0));
+ index := index + 4;
+ end if;
+ end loop;
+
+ data_out <= (others=>'X');
+
+ else -- (rst = '1'), normal operation
+
+ -- to simplify (and accelerate) internal address decoding,
+ -- the BASE of the RAM addresses MUST be allocated at an
+ -- address that is larger the RAM capacity. Otherwise, the
+ -- base must be subtracted from the address on every reference,
+ -- which means having an adder in the critical path. Bad idea.
+
+ u_addr := unsigned(addr( (DATA_ADDRS_BITS-1) downto 0 ) );
+ index := to_integer(u_addr);
+
+ if sel = '0' and wr = '0' and rising_edge(strobe) then
+
+ assert (index >= 0) and (index < DATA_MEM_SZ)
+ report "ramWR index out of bounds: " & natural'image(index)
+ severity failure;
+
+ case byte_sel is
+ when b"1111" => -- SW
+ storage(index+3) <= data_inp(31 downto 24);
+ storage(index+2) <= data_inp(23 downto 16);
+ storage(index+1) <= data_inp(15 downto 8);
+ storage(index+0) <= data_inp(7 downto 0);
+ when b"1100" | b"0011" => -- SH
+ storage(index+1) <= data_inp(15 downto 8);
+ storage(index+0) <= data_inp(7 downto 0);
+ when b"0001" | b"0010" | b"0100" | b"1000" => -- SB
+ storage(index+0) <= data_inp(7 downto 0);
+ when others => null;
+ end case;
+ -- assert false report "ramWR["& natural'image(index) &"] "
+ -- & SLV32HEX(data) &" bySel=" & SLV2STR(byte_sel); -- DEBUG
+ end if; -- is write?
+
+ if sel = '0' and wr = '1' then
+
+ assert (index >= 0) and (index < DATA_MEM_SZ)
+ report "ramRD index out of bounds: " & natural'image(index)
+ severity failure;
+
+ case byte_sel is
+ when b"1111" => -- LW
+ d(31 downto 24) := storage(index+3);
+ d(23 downto 16) := storage(index+2);
+ d(15 downto 8) := storage(index+1);
+ d(7 downto 0) := storage(index+0);
+ when b"1100" => -- LH top-half
+ d(31 downto 24) := storage(index+1);
+ d(23 downto 16) := storage(index+0);
+ d(15 downto 0) := (others => 'X');
+ when b"0011" => -- LH bottom-half
+ d(31 downto 16) := (others => 'X');
+ d(15 downto 8) := storage(index+1);
+ d(7 downto 0) := storage(index+0);
+ when b"0001" => -- LB top byte
+ d(31 downto 8) := (others => 'X');
+ d(7 downto 0) := storage(index+0);
+ when b"0010" => -- LB mid-top byte
+ d(31 downto 16) := (others => 'X');
+ d(15 downto 8) := storage(index+0);
+ d(7 downto 0) := (others => 'X');
+ when b"0100" => -- LB mid-bot byte
+ d(31 downto 24) := (others => 'X');
+ d(23 downto 16) := storage(index+0);
+ d(15 downto 0) := (others => 'X');
+ when b"1000" => -- LB bottom byte
+ d(31 downto 24) := storage(index+0);
+ d(23 downto 0) := (others => 'X');
+ when others => d := (others => 'X');
+ end case;
+ -- assert false report "ramRD["& natural'image(index) &"] "
+ -- & SLV32HEX(d) &" bySel="& SLV2STR(byte_sel); -- DEBUG
+
+ elsif rising_edge(dump_ram) then
+
+ i := 0;
+ while i < DATA_MEM_SZ-4 loop
+ d(31 downto 24) := storage(i+3);
+ d(23 downto 16) := storage(i+2);
+ d(15 downto 8) := storage(i+1);
+ d(7 downto 0) := storage(i+0);
+ write( dump_file, to_integer(signed(d)) );
+ i := i+4;
+ end loop; -- i
+
+ else
+ d := (others=>'X');
+ end if; -- is read?
+
+ data_out <= d;
+
+ end if; -- is reset?
+
+ end process accessRAM; -- ---------------------------------------------
+
+
+end architecture simulation;
+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
diff --git a/cMIPS/vhdl/rom.vhd b/cMIPS/vhdl/rom.vhd
index 381448509edcaa293c10e54729c3814dfd7586bd..5fcc5dc5c17d458cf30e86ebf963486f2d905623 100644
--- a/cMIPS/vhdl/rom.vhd
+++ b/cMIPS/vhdl/rom.vhd
@@ -17,7 +17,7 @@
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--- syncronous ROM; MIPS executable defined as constant, word-indexed
+-- syncronous ROM; FPGA version, word-indexed
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
@@ -25,7 +25,7 @@ use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
-entity fpga_ROM is
+entity ROM is
generic (LOAD_FILE_NAME : string := "prog.bin"); -- not used with FPGA
port (rst : in std_logic;
clk : in std_logic;
@@ -34,11 +34,13 @@ entity fpga_ROM is
strobe : in std_logic;
addr : in reg32;
data : out reg32);
- constant INST_ADDRS_BITS : natural := log2_ceil(INST_MEM_SZ);
+
+ -- FPGA version
+ -- constant INST_ADDRS_BITS : natural := log2_ceil(INST_MEM_SZ) - 1;
subtype rom_address is natural range 0 to ((INST_MEM_SZ / 4) - 1);
-end entity fpga_ROM;
+end entity ROM;
-architecture rtl of fpga_ROM is
+architecture rtl of ROM is
component wait_states is
generic (NUM_WAIT_STATES :integer := 0);
@@ -56,9 +58,17 @@ architecture rtl of fpga_ROM is
q : out std_logic_vector);
end component single_port_rom;
+ component alt_mf_rom
+ port (address : IN STD_LOGIC_VECTOR ((INST_ADDRS_BITS-1) DOWNTO 0);
+ clken : IN STD_LOGIC := '1';
+ clock : IN STD_LOGIC := '1';
+ q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
+ end component alt_mf_rom;
+
signal instrn : reg32;
signal index : rom_address := 0;
signal waiting, clken : std_logic;
+ signal raw_addr : std_logic_vector((INST_ADDRS_BITS-1) downto 0);
begin -- rtl
@@ -70,11 +80,16 @@ begin -- rtl
clken <= not(sel);
-- >>2 = /4: byte addressed but word indexed
- index <= to_integer(unsigned(addr((INST_ADDRS_BITS-1) downto 2)));
+ index <= to_integer(unsigned(addr((INST_ADDRS_BITS-1)+2 downto 2)));
- U_ROM: single_port_rom generic map (INST_MEM_SZ / 4)
- port map (index, clken, strobe, instrn);
+ -- U_ROM: single_port_rom generic map (INST_MEM_SZ / 4)
+ -- port map (index, clken, strobe, instrn);
+
+
+ raw_addr <= addr((INST_ADDRS_BITS-1)+2 downto 2);
+ U_RTL_ROM: alt_mf_rom port map (raw_addr, clken, strobe, instrn);
+
U_ROM_ACCESS: process (strobe,instrn,sel)
begin
if sel = '0' then
@@ -89,7 +104,7 @@ begin -- rtl
end if;
end process U_ROM_ACCESS;
-end rtl;
+end architecture rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
@@ -121,267 +136,7 @@ architecture rtl of single_port_rom is
-- -e '$s:,: :'
constant test_prog : memory_t := (
-
-x"00000000", -- 0: nop
-x"3c0f0f00", -- 4: lui $15,0xf00
-x"35ef0120", -- 8: ori $15,$15,0x120
-x"24100001", -- c: li $16,1
-x"adf00000", -- 10: sw $16,0($15)
-x"3c040009", -- 14: lui $4,0x9
-x"34848968", -- 18: ori $4,$4,0x8968
-x"0c0000b7", -- 1c: jal 2dc <delay>
-x"00000000", -- 20: nop
-x"3c1a0f00", -- 24: lui $26,0xf00
-x"375a0160", -- 28: ori $26,$26,0x160
-x"24130030", -- 2c: li $19,48
-x"af530000", -- 30: sw $19,0($26)
-x"24040177", -- 34: li $4,375
-x"0c0000b7", -- 38: jal 2dc <delay>
-x"00000000", -- 3c: nop
-x"24130030", -- 40: li $19,48
-x"af530000", -- 44: sw $19,0($26)
-x"24040177", -- 48: li $4,375
-x"0c0000b7", -- 4c: jal 2dc <delay>
-x"00000000", -- 50: nop
-x"24130039", -- 54: li $19,57
-x"af530000", -- 58: sw $19,0($26)
-x"24040177", -- 5c: li $4,375
-x"0c0000b7", -- 60: jal 2dc <delay>
-x"00000000", -- 64: nop
-x"24130014", -- 68: li $19,20
-x"af530000", -- 6c: sw $19,0($26)
-x"24040177", -- 70: li $4,375
-x"0c0000b7", -- 74: jal 2dc <delay>
-x"00000000", -- 78: nop
-x"24130070", -- 7c: li $19,112
-x"af530000", -- 80: sw $19,0($26)
-x"24040177", -- 84: li $4,375
-x"0c0000b7", -- 88: jal 2dc <delay>
-x"00000000", -- 8c: nop
-x"24130056", -- 90: li $19,86
-x"af530000", -- 94: sw $19,0($26)
-x"24040177", -- 98: li $4,375
-x"0c0000b7", -- 9c: jal 2dc <delay>
-x"00000000", -- a0: nop
-x"2413006d", -- a4: li $19,109
-x"af530000", -- a8: sw $19,0($26)
-x"24040177", -- ac: li $4,375
-x"0c0000b7", -- b0: jal 2dc <delay>
-x"00000000", -- b4: nop
-x"24100002", -- b8: li $16,2
-x"adf00000", -- bc: sw $16,0($15)
-x"3c0400be", -- c0: lui $4,0xbe
-x"3484bc20", -- c4: ori $4,$4,0xbc20
-x"0c0000b7", -- c8: jal 2dc <delay>
-x"00000000", -- cc: nop
-x"3c040026", -- d0: lui $4,0x26
-x"348425a0", -- d4: ori $4,$4,0x25a0
-x"0c0000b7", -- d8: jal 2dc <delay>
-x"00000000", -- dc: nop
-x"24100003", -- e0: li $16,3
-x"adf00000", -- e4: sw $16,0($15)
-x"3c0400be", -- e8: lui $4,0xbe
-x"3484bc20", -- ec: ori $4,$4,0xbc20
-x"0c0000b7", -- f0: jal 2dc <delay>
-x"00000000", -- f4: nop
-x"3c1a0f00", -- f8: lui $26,0xf00
-x"375a0160", -- fc: ori $26,$26,0x160
-x"2413000f", -- 100: li $19,15
-x"af530000", -- 104: sw $19,0($26)
-x"24040177", -- 108: li $4,375
-x"0c0000b7", -- 10c: jal 2dc <delay>
-x"00000000", -- 110: nop
-x"24130006", -- 114: li $19,6
-x"af530000", -- 118: sw $19,0($26)
-x"24040177", -- 11c: li $4,375
-x"0c0000b7", -- 120: jal 2dc <delay>
-x"00000000", -- 124: nop
-x"24100004", -- 128: li $16,4
-x"adf00000", -- 12c: sw $16,0($15)
-x"3c0400be", -- 130: lui $4,0xbe
-x"3484bc20", -- 134: ori $4,$4,0xbc20
-x"0c0000b7", -- 138: jal 2dc <delay>
-x"00000000", -- 13c: nop
-x"24130001", -- 140: li $19,1
-x"af530000", -- 144: sw $19,0($26)
-x"24040177", -- 148: li $4,375
-x"0c0000b7", -- 14c: jal 2dc <delay>
-x"00000000", -- 150: nop
-x"24130080", -- 154: li $19,128
-x"af530000", -- 158: sw $19,0($26)
-x"24040177", -- 15c: li $4,375
-x"0c0000b7", -- 160: jal 2dc <delay>
-x"00000000", -- 164: nop
-x"24100005", -- 168: li $16,5
-x"adf00000", -- 16c: sw $16,0($15)
-x"3c0400be", -- 170: lui $4,0xbe
-x"3484bc20", -- 174: ori $4,$4,0xbc20
-x"0c0000b7", -- 178: jal 2dc <delay>
-x"00000000", -- 17c: nop
-x"8f530000", -- 180: lw $19,0($26)
-x"00000000", -- 184: nop
-x"32730080", -- 188: andi $19,$19,0x80
-x"1660fffc", -- 18c: bnez $19,180 <check>
-x"00000000", -- 190: nop
-x"02608021", -- 194: move $16,$19
-x"adf00000", -- 198: sw $16,0($15)
-x"3c0400be", -- 19c: lui $4,0xbe
-x"3484bc20", -- 1a0: ori $4,$4,0xbc20
-x"0c0000b7", -- 1a4: jal 2dc <delay>
-x"00000000", -- 1a8: nop
-x"24130080", -- 1ac: li $19,128
-x"af530000", -- 1b0: sw $19,0($26)
-x"24040177", -- 1b4: li $4,375
-x"0c0000b7", -- 1b8: jal 2dc <delay>
-x"00000000", -- 1bc: nop
-x"3c046c6c", -- 1c0: lui $4,0x6c6c
-x"34846548", -- 1c4: ori $4,$4,0x6548
-x"0c000097", -- 1c8: jal 25c <send>
-x"00000000", -- 1cc: nop
-x"3c046f77", -- 1d0: lui $4,0x6f77
-x"3484206f", -- 1d4: ori $4,$4,0x206f
-x"0c000097", -- 1d8: jal 25c <send>
-x"00000000", -- 1dc: nop
-x"3c042164", -- 1e0: lui $4,0x2164
-x"34846c72", -- 1e4: ori $4,$4,0x6c72
-x"0c000097", -- 1e8: jal 25c <send>
-x"00000000", -- 1ec: nop
-x"24100007", -- 1f0: li $16,7
-x"adf00000", -- 1f4: sw $16,0($15)
-x"3c0400be", -- 1f8: lui $4,0xbe
-x"3484bc20", -- 1fc: ori $4,$4,0xbc20
-x"0c0000b7", -- 200: jal 2dc <delay>
-x"00000000", -- 204: nop
-x"241300c0", -- 208: li $19,192
-x"af530000", -- 20c: sw $19,0($26)
-x"24040177", -- 210: li $4,375
-x"0c0000b7", -- 214: jal 2dc <delay>
-x"00000000", -- 218: nop
-x"3c046961", -- 21c: lui $4,0x6961
-x"34847320", -- 220: ori $4,$4,0x7320
-x"0c000097", -- 224: jal 25c <send>
-x"00000000", -- 228: nop
-x"3c044d63", -- 22c: lui $4,0x4d63
-x"34842064", -- 230: ori $4,$4,0x2064
-x"0c000097", -- 234: jal 25c <send>
-x"00000000", -- 238: nop
-x"3c042053", -- 23c: lui $4,0x2053
-x"34845049", -- 240: ori $4,$4,0x5049
-x"0c000097", -- 244: jal 25c <send>
-x"00000000", -- 248: nop
-x"24100008", -- 24c: li $16,8
-x"adf00000", -- 250: sw $16,0($15)
-x"08000095", -- 254: j 254 <end>
-x"00000000", -- 258: nop
-x"3c1a0f00", -- 25c: lui $26,0xf00
-x"375a0160", -- 260: ori $26,$26,0x160
-x"af440004", -- 264: sw $4,4($26)
-x"00042202", -- 268: srl $4,$4,0x8
-x"240500fa", -- 26c: li $5,250
-x"24a5ffff", -- 270: addiu $5,$5,-1
-x"00000000", -- 274: nop
-x"14a0fffd", -- 278: bnez $5,270 <delay0>
-x"00000000", -- 27c: nop
-x"af440004", -- 280: sw $4,4($26)
-x"00042202", -- 284: srl $4,$4,0x8
-x"240500fa", -- 288: li $5,250
-x"24a5ffff", -- 28c: addiu $5,$5,-1
-x"00000000", -- 290: nop
-x"14a0fffd", -- 294: bnez $5,28c <delay1>
-x"00000000", -- 298: nop
-x"af440004", -- 29c: sw $4,4($26)
-x"00042202", -- 2a0: srl $4,$4,0x8
-x"240500fa", -- 2a4: li $5,250
-x"24a5ffff", -- 2a8: addiu $5,$5,-1
-x"00000000", -- 2ac: nop
-x"14a0fffd", -- 2b0: bnez $5,2a8 <delay2>
-x"00000000", -- 2b4: nop
-x"af440004", -- 2b8: sw $4,4($26)
-x"00000000", -- 2bc: nop
-x"240500fa", -- 2c0: li $5,250
-x"24a5ffff", -- 2c4: addiu $5,$5,-1
-x"00000000", -- 2c8: nop
-x"14a0fffd", -- 2cc: bnez $5,2c4 <delay3>
-x"00000000", -- 2d0: nop
-x"03e00008", -- 2d4: jr $31
-x"00000000", -- 2d8: nop
-x"2484ffff", -- 2dc: addiu $4,$4,-1
-x"00000000", -- 2e0: nop
-x"1480fffd", -- 2e4: bnez $4,2dc <delay>
-x"00000000", -- 2e8: nop
-x"03e00008", -- 2ec: jr $31
-x"00000000", -- 2f0: nop
-x"00000000", -- 2f4: nop
-x"00000000", -- 2f8: nop
-x"00000000", -- 2fc: nop
-x"00000000", -- 300: nop
-x"00000000", -- 304: nop
-x"00000000", -- 308: nop
-x"00000000", -- 30c: nop
-x"00000000", -- 310: nop
-x"00000000", -- 314: nop
-x"00000000", -- 318: nop
-x"00000000", -- 31c: nop
-x"00000000", -- 320: nop
-x"00000000", -- 324: nop
-x"00000000", -- 328: nop
-x"00000000", -- 32c: nop
-x"00000000", -- 330: nop
-x"00000000", -- 334: nop
-x"00000000", -- 338: nop
-x"00000000", -- 33c: nop
-x"00000000", -- 340: nop
-x"00000000", -- 344: nop
-x"00000000", -- 348: nop
-x"00000000", -- 34c: nop
-x"00000000", -- 350: nop
-x"00000000", -- 354: nop
-x"00000000", -- 358: nop
-x"00000000", -- 35c: nop
-x"00000000", -- 360: nop
-x"00000000", -- 364: nop
-x"00000000", -- 368: nop
-x"00000000", -- 36c: nop
-x"00000000", -- 370: nop
-x"00000000", -- 374: nop
-x"00000000", -- 378: nop
-x"00000000", -- 37c: nop
-x"00000000", -- 380: nop
-x"00000000", -- 384: nop
-x"00000000", -- 388: nop
-x"00000000", -- 38c: nop
-x"00000000", -- 390: nop
-x"00000000", -- 394: nop
-x"00000000", -- 398: nop
-x"00000000", -- 39c: nop
-x"00000000", -- 3a0: nop
-x"00000000", -- 3a4: nop
-x"00000000", -- 3a8: nop
-x"00000000", -- 3ac: nop
-x"00000000", -- 3b0: nop
-x"00000000", -- 3b4: nop
-x"00000000", -- 3b8: nop
-x"00000000", -- 3bc: nop
-x"00000000", -- 3c0: nop
-x"00000000", -- 3c4: nop
-x"00000000", -- 3c8: nop
-x"00000000", -- 3cc: nop
-x"00000000", -- 3d0: nop
-x"00000000", -- 3d4: nop
-x"00000000", -- 3d8: nop
-x"00000000", -- 3dc: nop
-x"00000000", -- 3e0: nop
-x"00000000", -- 3e4: nop
-x"00000000", -- 3e8: nop
-x"00000000", -- 3ec: nop
-x"00000000", -- 3f0: nop
-x"00000000", -- 3f4: nop
-x"00000000", -- 3f8: nop
-x"00000000" -- 3fc: nop
-
-
-);
-
+ (others => (others => '0')) );
function init_rom
return memory_t is
@@ -413,5 +168,100 @@ begin
end if;
end process;
-end rtl;
+end architecture rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+
+
+
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+-- syncronous ROM; MIPS executable loaded into ROM at CPU reset, wd-indexed
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+architecture simulation of ROM is
+
+ component wait_states is
+ generic (NUM_WAIT_STATES :integer := 0);
+ port(rst : in std_logic;
+ clk : in std_logic;
+ sel : in std_logic; -- active in '0'
+ waiting : out std_logic); -- active in '1'
+ end component wait_states;
+
+ component FFT is
+ port(clk, rst, T : in std_logic; Q : out std_logic);
+ end component FFT;
+
+ constant WAIT_COUNT : max_wait_states := (NUM_MAX_W_STS - ROM_WAIT_STATES);
+ constant WAIT_FOR : reg10 := std_logic_vector(to_signed(WAIT_COUNT, 10));
+
+ signal waiting, do_wait : std_logic;
+
+begin -- behavioral
+
+ U_BUS_WAIT: wait_states generic map (ROM_WAIT_STATES)
+ port map (rst, clk, sel, waiting);
+
+ rdy <= not(waiting);
+
+ U_ROM: process (rst, sel, strobe, addr)
+
+ subtype t_address is unsigned((INST_ADDRS_BITS - 1) downto 0);
+ variable u_addr : t_address;
+
+ subtype word is std_logic_vector(data'length - 1 downto 0);
+ type storage_array is
+ array( natural range 0 to (INST_MEM_SZ - 1) ) of word;
+ variable storage : storage_array;
+ variable index, latched : natural;
+
+ type binary_file is file of integer;
+ file load_file: binary_file open read_mode is LOAD_FILE_NAME;
+ variable instr: integer; -- := to_integer(unsigned(NULL_INSTRUCTION));
+ variable s_instr : signed(31 downto 0);
+
+ begin
+
+ if rst = '0' then -- reset, read binary executable
+
+ index := 0; -- indexed by word
+ for i in 0 to (INST_MEM_SZ - 1) loop
+
+ if not endfile(load_file) then
+ read(load_file, instr);
+ s_instr := to_signed(instr, 32);
+ -- assert false report "romINIT["& natural'image(index*4) &"]= " &
+ -- SLV32HEX(std_logic_vector(s_instr)); -- DEBUG
+ storage(index) := std_logic_vector(s_instr);
+ index := index + 1;
+ end if;
+
+ end loop; -- i
+
+ else -- normal operation
+
+ u_addr := unsigned(addr((2+(INST_ADDRS_BITS-1)) downto 2)); -- >>2 = /4
+ index := to_integer(u_addr); -- indexed by word, not by byte
+
+ assert (index >= 0) and (index < INST_MEM_SZ/4)
+ report "romRDindex out of bounds: " & SLV32HEX(addr) & " = " &
+ natural'image(index) severity warning; -- failure;
+
+ if sel = '0' and rising_edge(strobe) then
+ latched := index;
+ end if;
+
+ if sel = '0' then
+ data <= storage(latched);
+ -- assert false -- DEBUG
+ -- report "romRD["& natural'image(index) &"]="& SLV32HEX(storage(index));
+ else
+ data <= (others => 'X');
+ end if;
+
+ end if;
+
+ end process;
+
+end architecture simulation;
+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
diff --git a/cMIPS/vhdl/sdram.vhd b/cMIPS/vhdl/sdram.vhd
index 3073715cabcb3f9a0d6f9c51625c6a99ae6322d5..f1678ff49e5668fc9d43cd26982b540d12f55340 100644
--- a/cMIPS/vhdl/sdram.vhd
+++ b/cMIPS/vhdl/sdram.vhd
@@ -436,37 +436,8 @@ end simple;
-- fake SDRAM controller for Macnica's development board Mercurio IV
-- IS42S16320B, 512Mbit SDRAM, 146MHz, 32Mx16bit
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-library IEEE;
-use IEEE.std_logic_1164.all;
-use work.p_wires.all;
-
-entity fake_SDRAM_controller is
- port (rst : in std_logic; -- FPGA reset (=0)
- clk2x : in std_logic; -- 100MHz clock
-
- hcs : in std_logic; -- host side chip select (=0)
- rdy : out std_logic; -- tell CPU to wait (=0)
- wr : in std_logic; -- host side write enable (=0)
- bsel : in reg4; -- byte select
- haddr : in reg26; -- host side address
- hDinp : in reg32; -- host side data input
- hDout : out reg32; -- host side data output
- cke : out std_logic; -- ram side clock enable
- scs : out std_logic; -- ram side chip select
- ras : out std_logic; -- ram side RAS
- cas : out std_logic; -- ram side CAS
- we : out std_logic; -- ram side write enable
- dqm0 : out std_logic; -- ram side byte0 output enable
- dqm1 : out std_logic; -- ram side byte0 output enable
- ba0 : out std_logic; -- ram side bank select 0
- ba1 : out std_logic; -- ram side bank select 1
- saddr : out reg12; -- ram side address
- sdata : inout reg16); -- ram side data
-
-end entity fake_SDRAM_controller;
-
-architecture fake of fake_SDRAM_controller is
+architecture fake of SDRAM_controller is
begin
rdy <= '1';
@@ -486,3 +457,4 @@ begin
end architecture fake;
+-- ---------------------------------------------------------------------
diff --git a/cMIPS/vhdl/tb_cMIPS.vhd b/cMIPS/vhdl/tb_cMIPS.vhd
index 6484cb5dd72241eb681e35001fadec64cc70e5d7..0d40cb58b7d10aecf403885505d62085964bd3eb 100644
--- a/cMIPS/vhdl/tb_cMIPS.vhd
+++ b/cMIPS/vhdl/tb_cMIPS.vhd
@@ -155,17 +155,6 @@ architecture TB of tb_cMIPS is
data_out : out std_logic_vector);
end component FPU;
- component fake_FPU is
- port (rst : in std_logic;
- clk : in std_logic;
- sel : in std_logic;
- rdy : out std_logic;
- wr : in std_logic;
- addr : in std_logic_vector;
- data_inp : in std_logic_vector;
- data_out : out std_logic_vector);
- end component fake_FPU;
-
component remota is
generic(OUTPUT_FILE_NAME : string; INPUT_FILE_NAME : string);
port(rst, clk : in std_logic;
@@ -246,7 +235,7 @@ architecture TB of tb_cMIPS is
data : out std_logic_vector);
end component simul_ROM;
- component fpga_ROM is
+ component ROM is
generic (LOAD_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
@@ -255,9 +244,9 @@ architecture TB of tb_cMIPS is
strobe : in std_logic;
addr : in std_logic_vector;
data : out std_logic_vector);
- end component fpga_ROM;
+ end component ROM;
- component simul_RAM is
+ component RAM is
generic (LOAD_FILE_NAME : string; DUMP_FILE_NAME : string);
port (rst : in std_logic;
clk : in std_logic;
@@ -270,7 +259,7 @@ architecture TB of tb_cMIPS is
data_out : out std_logic_vector;
byte_sel : in std_logic_vector;
dump_ram : in std_logic);
- end component simul_RAM;
+ end component RAM;
component fpga_RAM is
generic (LOAD_FILE_NAME : string; DUMP_FILE_NAME : string);
@@ -310,45 +299,6 @@ architecture TB of tb_cMIPS is
sdata : inout reg16); -- ram side data
end component SDRAM_controller;
- component fake_SDRAM_controller is
- port (rst : in std_logic; -- FPGA reset (=0)
- clk2x : in std_logic; -- 100MHz clock
- hcs : in std_logic; -- host side chip select (=0)
- rdy : out std_logic; -- tell CPU to wait (=0)
- wr : in std_logic; -- host side write enable (=0)
- bsel : in reg4; -- byte select
- haddr : in reg26; -- host side address
- hDinp : in reg32; -- host side data input
- hDout : out reg32; -- host side data output
- cke : out std_logic; -- ram side clock enable
- scs : out std_logic; -- ram side chip select
- ras : out std_logic; -- ram side RAS
- cas : out std_logic; -- ram side CAS
- we : out std_logic; -- ram side write enable
- dqm0 : out std_logic; -- ram side byte0 output enable
- dqm1 : out std_logic; -- ram side byte0 output enable
- ba0 : out std_logic; -- ram side bank select 0
- ba1 : out std_logic; -- ram side bank select 1
- saddr : out reg12; -- ram side address
- sdata : inout reg16); -- ram side data
- end component fake_SDRAM_controller;
-
- component fake_I_CACHE is
- port (rst : in std_logic;
- clk4x : in std_logic;
- ic_reset : out std_logic;
- cpu_sel : in std_logic;
- cpu_rdy : out std_logic;
- cpu_addr : in std_logic_vector;
- cpu_data : out std_logic_vector;
- mem_sel : out std_logic;
- mem_rdy : in std_logic;
- mem_addr : out std_logic_vector;
- mem_data : in std_logic_vector;
- ref_cnt : out integer;
- hit_cnt : out integer);
- end component fake_I_CACHE;
-
component I_CACHE is
port (rst : in std_logic;
clk4x : in std_logic;
@@ -381,29 +331,6 @@ architecture TB of tb_cMIPS is
hit_cnt : out integer);
end component I_CACHE_fpga;
- component fake_D_CACHE is
- port (rst : in std_logic;
- clk4x : in std_logic;
- cpu_sel : in std_logic;
- cpu_rdy : out std_logic;
- cpu_wr : in std_logic;
- cpu_addr : in std_logic_vector;
- cpu_data_inp : in std_logic_vector;
- cpu_data_out : out std_logic_vector;
- cpu_xfer : in std_logic_vector;
- mem_sel : out std_logic;
- mem_rdy : in std_logic;
- mem_wr : out std_logic;
- mem_addr : out std_logic_vector;
- mem_data_inp : in std_logic_vector;
- mem_data_out : out std_logic_vector;
- mem_xfer : out std_logic_vector;
- ref_cnt : out integer;
- rd_hit_cnt : out integer;
- wr_hit_cnt : out integer;
- flush_cnt : out integer);
- end component fake_D_CACHE;
-
component D_CACHE is
port (rst : in std_logic;
clk4x : in std_logic;
@@ -601,15 +528,13 @@ begin -- TB
U_INST_ADDR_DEC: inst_addr_decode
port map (rst, cpu_i_aVal, i_addr, inst_aVal, i_busError);
- U_I_CACHE: fake_i_cache -- or i_cache
- -- U_I_CACHE: i_cache -- or fake_i_cache
-- U_I_CACHE: i_cache_fpga -- or FPGA implementation
+ U_I_CACHE: i_cache
port map (rst, clk4x, ic_reset,
inst_aVal, inst_wait, i_addr, cpu_instr,
mem_i_sel, rom_rdy, mem_i_addr, datrom, cnt_i_ref,cnt_i_hit);
- U_ROM: simul_ROM generic map ("prog.bin")
- -- U_ROM: fpga_ROM generic map ("prog.bin")
+ U_ROM: ROM generic map ("prog.bin")
port map (rst, clk, mem_i_sel,rom_rdy, phi3, mem_i_addr,datrom);
U_DATA_BUS_ERROR_DEC: busError_addr_decode
@@ -639,8 +564,7 @@ begin -- TB
lcd_d_out when b"1101",
(others => 'X') when others;
- U_D_CACHE: fake_d_cache -- or d_cache
- -- U_D_CACHE: d_cache -- or fake_d_cache
+ U_D_CACHE: d_cache
port map (rst, clk4x,
data_aVal, data_wait, wr,
d_addr, cpu_data, d_cache_d_out, cpu_xfer,
@@ -648,13 +572,11 @@ begin -- TB
mem_addr, datram_inp, datram_out, mem_xfer,
cnt_d_ref, cnt_d_rd_hit, cnt_d_wr_hit, cnt_d_flush);
- U_RAM: simul_RAM generic map ("data.bin", "dump.data")
- -- U_RAM: fpga_RAM generic map ("data.bin", "dump.data")
+ U_RAM: RAM generic map ("data.bin", "dump.data")
port map (rst, clk, mem_d_sel, ram_rdy, mem_wr, phi2,
mem_addr, datram_out, datram_inp, mem_xfer, dump_ram);
- -- U_SDRAM_controller : SDRAM_controller port map
- U_SDRAM_controller : fake_SDRAM_controller port map
+ U_SDRAM_controller: SDRAM_controller port map
(rst, clk,hcs,sdram_rdy,wr,cpu_xfer,haddr,hDinp,hDout,
sdcke,sdscs,sdras,sdcas,sdwe,sddqm0,sddqm1,sdba0,sdba1,sdaddr,sddata);
@@ -714,7 +636,6 @@ begin -- TB
U_uart_remota: remota generic map ("serial.out","serial.inp")
port map (rst, clk, start_remota, uart_txd, uart_rxd, bit_rt);
- -- U_FPU: fake_FPU
U_FPU: FPU
port map (rst,clk, io_FPU_sel,io_FPU_wait, wr, d_addr(5 downto 2),
cpu_data,fpu_d_out);
@@ -1101,10 +1022,44 @@ end architecture behavioral;
--++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--- --------------------------------------------------------------
+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
configuration CFG_TB of TB_CMIPS is
- for TB
- end for;
+ for TB
+
+ -- use fake / behavioral
+ for U_I_CACHE : I_cache
+ use entity work.I_cache(fake);
+ end for;
+
+ -- use simulation / rtl
+ for U_ROM : ROM
+ use entity work.ROM(simulation);
+ end for;
+
+ -- use simulation / rtl
+ for U_RAM : RAM
+ use entity work.RAM(simulation);
+ end for;
+
+ -- use fake / behavioral
+ for U_D_CACHE : D_cache
+ use entity work.D_cache(fake);
+ end for;
+
+
+ -- use fake / rtl
+ for U_FPU: FPU
+ use entity work.FPU(fake);
+ end for;
+
+ -- use fake / simple
+ for U_SDRAM_controller : SDRAM_controller
+ use entity work.SDRAM_controller(fake);
+ end for;
+
+
+ end for;
end configuration CFG_TB;
--- --------------------------------------------------------------
+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+