From 9d0ced85d1db7fb8aabefa0f7553f92a946ae66b Mon Sep 17 00:00:00 2001
From: Roberto Hexsel <roberto@inf.ufpr.br>
Date: Wed, 8 Jul 2015 21:26:51 -0300
Subject: [PATCH] what is wrong with teq_tlt?
---
cMIPS/bin/compile.sh | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/cMIPS/bin/compile.sh b/cMIPS/bin/compile.sh
index 831eb43..2a9e459 100755
--- a/cMIPS/bin/compile.sh
+++ b/cMIPS/bin/compile.sh
@@ -33,7 +33,7 @@ OPTIONS:
-h Show this message
-O n Optimization level, defaults to n=1 {0,1,2,3}
-v Verbose, creates memory map: source.map
- -W GIve -Wall to GCC
+ -W Pass -Wall on to GCC
-mif Generate output file ROM.mif for Altera's FPGAs
-syn Compile for synthesis, else for simulation
EOF
@@ -127,9 +127,11 @@ dat=data.bin
if [ $verbose = true ]; then memory_map="-Map ${inp}.map" ; fi
-if [ $synth = true ];
-then S="-D FOR_SYNTHESIS" ;
-else S="-U FOR_SYNTHESIS" ; fi
+if [ $synth = true ]; then
+ S="-D FOR_SYNTHESIS" ;
+else
+ S="-U FOR_SYNTHESIS" ;
+fi
(mips-gcc -O${level} $warn -DcMIPS -mno-gpopt -I"${include}" \
-S ${src} $S -o ${asm} || exit 1) && \
--
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