From 9e0868814788b181020fe9f9d0056268183fcfa9 Mon Sep 17 00:00:00 2001 From: Roberto Hexsel <roberto@inf.ufpr.br> Date: Fri, 16 Oct 2015 11:49:36 -0300 Subject: [PATCH] fixed exception priorities --- cMIPS/bin/assemble.sh | 2 +- cMIPS/tests/mmu_refill2.s | 56 +++++++++++++++++++++++++----- cMIPS/vhdl/core.vhd | 73 ++++++++++++--------------------------- cMIPS/vhdl/exception.vhd | 25 +++----------- 4 files changed, 74 insertions(+), 82 deletions(-) diff --git a/cMIPS/bin/assemble.sh b/cMIPS/bin/assemble.sh index c657f6e..df07423 100755 --- a/cMIPS/bin/assemble.sh +++ b/cMIPS/bin/assemble.sh @@ -82,7 +82,7 @@ while true ; do ;; -v) verbose=true ;; - -mif) miffile=true + -mif|-m) miffile=true ;; -x) set -x ;; diff --git a/cMIPS/tests/mmu_refill2.s b/cMIPS/tests/mmu_refill2.s index e95bd7e..1d47ed8 100644 --- a/cMIPS/tests/mmu_refill2.s +++ b/cMIPS/tests/mmu_refill2.s @@ -77,18 +77,26 @@ _excp_0100: nop nop nop - wait 0x02 + wait 0x01 nop + + .org x_EXCEPTION_0180,0 _excp_0180: la $k0, x_IO_BASE_ADDR mfc0 $k1, cop0_CAUSE sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation - nop + + la $a0, not_enough_ram + jal kprintf + nop nop nop wait 0x02 nop + + + .org x_EXCEPTION_0200,0 _excp_0200: la $k0, x_IO_BASE_ADDR mfc0 $k1, cop0_CAUSE @@ -98,7 +106,9 @@ _excp_0200: nop wait 0x03 nop - .org x_EXCEPTION_BFC0,0 + + + .org x_EXCEPTION_BFC0,0 _excp_BFC0: la $k0, x_IO_BASE_ADDR mfc0 $k1, cop0_CAUSE @@ -110,19 +120,24 @@ _excp_BFC0: nop + + ## dirty trick: there is not enough memory for a full PT, thus + ## we set the PT at the bottom of RAM addresses and have + ## Context pointing into that address range + .set PTbase, x_DATA_BASE_ADDR + .set PTsize, 1024 # set 1/4 page for PT + .data +_PageTable: + .space PTsize, 0 + ## ##================================================================ ## normal code starts here ## + .text .org x_ENTRY_POINT,0 - - ## dirty trick: there is not enough memory for a full PT, thus - ## we set the PT at the bottom of RAM addresses and have - ## Context pointing into that address range - - .set PTbase, x_DATA_BASE_ADDR .ent main main: la $20, x_IO_BASE_ADDR @@ -276,7 +291,29 @@ goBack: li $30, 'a' nop nop +kprintf: + la $a3, x_IO_BASE_ADDR +kloop: lbu $a1, 0($a0) # while (*p++ != '\0') putc(*p) ; + addi $a0, $a0, 1 + beq $a1, $zero, kend + nop + j kloop + sw $a1, x_IO_ADDR_RANGE($a3) + +kend: li $a1, '\n' # print a newline + jr $ra + sw $a1, x_IO_ADDR_RANGE($a3) + + + .data +not_enough_ram: + .asciiz "\n\tneed >=4 ROM pages & >=8 RAM pages for this test\n" + .text + + ## + ## set destination to a far far away place + ## .org (x_INST_BASE_ADDR + 2*4096), 0 there: li $30, 't' @@ -311,3 +348,4 @@ _exit: nop nop .end main + diff --git a/cMIPS/vhdl/core.vhd b/cMIPS/vhdl/core.vhd index dbbb8e5..e714031 100644 --- a/cMIPS/vhdl/core.vhd +++ b/cMIPS/vhdl/core.vhd @@ -73,8 +73,8 @@ architecture rtl of core is EX_can_trap: out std_logic_vector; RF_exception: in exception_type; EX_exception: out exception_type; - RF_trap_instr: in instr_type; - EX_trap_instr: out instr_type; +-- RF_trap_instr: in instr_type; +-- EX_trap_instr: out instr_type; RF_is_delayslot: in std_logic; EX_is_delayslot: out std_logic; RF_PC_abort: in boolean; @@ -101,8 +101,6 @@ architecture rtl of core is MM_addrError: out boolean; EX_addrErr_stage_mm: in boolean; MM_addrErr_stage_mm: out boolean; - EX_mem_excp_type: in exception_type; - MM_mem_excp_type: out exception_type; EX_is_delayslot: in std_logic; MM_is_delayslot: out std_logic; EX_trapped: in boolean; @@ -111,8 +109,6 @@ architecture rtl of core is MM_ll_sc_abort: out boolean; EX_tlb_exception: in boolean; MM_tlb_exception: out boolean; - EX_tlb_excp_type: in exception_type; - MM_tlb_excp_type: out exception_type; EX_tlb_stage_MM: in boolean; MM_tlb_stage_MM: out boolean; EX_int_req: in reg8; @@ -121,12 +117,9 @@ architecture rtl of core is MM_is_SC: out boolean; EX_is_MFC0: in boolean; MM_is_MFC0: out boolean; - EX_ext_event: in boolean; - MM_ext_event: out boolean; - EX_ext_event_type: in exception_type; - MM_ext_event_type: out exception_type; - EX_int_event_type: in exception_type; - MM_int_event_type: out exception_type); + EX_is_exception: in exception_type; + MM_is_exception: out exception_type); + end component reg_excp_EX_MM; component reg_excp_MM_WB is @@ -148,9 +141,8 @@ architecture rtl of core is signal addrError, MM_addrError, abort_ref, MM_ll_sc_abort : boolean; signal PC_abort, RF_PC_abort, EX_PC_abort : boolean; signal IF_excp_type,RF_excp_type : exception_type; - signal mem_excp_type, MM_mem_excp_type : exception_type; - signal tlb_excp_type, MM_tlb_excp_type : exception_type; - signal trap_instr,EX_trap_instr: instr_type; + signal mem_excp_type, tlb_excp_type : exception_type; + signal trap_instr: instr_type; signal RF_PC,EX_PC,MM_PC,WB_PC, LLaddr: reg32; signal ll_sc_bit, MM_LLbit,WB_LLbit: std_logic; signal LL_update, LL_SC_abort, LL_SC_differ: std_logic; @@ -169,7 +161,7 @@ architecture rtl of core is signal COUNT, COMPARE : reg32; signal count_eq_compare,count_update,count_enable : std_logic; signal exception,EX_exception, MM_exception : exception_type; - signal is_exception, MM_is_exception : exception_type; + signal is_exception, EX_is_exception : exception_type; signal ExcCode : reg5 := cop0code_NULL; signal exception_dec,TLB_excp_num,trap_dec: integer; -- debugging signal RF_is_delayslot,EX_is_delayslot,MM_is_delayslot,WB_is_delayslot,is_delayslot : std_logic; @@ -180,10 +172,8 @@ architecture rtl of core is signal BadVAddr_update : std_logic; signal is_SC, MM_is_SC, is_MFC0, MM_is_MFC0 : boolean; - signal is_busError, is_nmi, is_interr, is_ovfl, ext_event, MM_ext_event : boolean; + signal is_busError, is_nmi, is_interr, is_ovfl : boolean; signal busError_type : exception_type; - signal ext_event_type, MM_ext_event_type : exception_type; - signal int_event_type, MM_int_event_type : exception_type; -- MMU signals -- signal INDEX, index_inp, RANDOM, WIRED, wired_inp : reg32; @@ -1101,7 +1091,7 @@ begin RF_DECODE_FUNCT: process (opcode,IF_RF_ld,ctrl_word,funct_word,rimm_word, func,shamt, a_rs,a_rd, STATUS, - RF_excp_type,RF_instruction, mem_excp_type) + RF_excp_type,RF_instruction) variable i_wreg : std_logic; variable i_csel : reg2; variable i_oper : t_alu_fun := opNOP; @@ -1777,7 +1767,7 @@ begin port map (clk, rst, excp_RF_EX_ld, cop0_reg,EX_cop0_reg, cop0_sel,EX_cop0_sel, can_trap,EX_can_trap, - exception,EX_exception, trap_instr,EX_trap_instr, + exception,EX_exception, RF_is_delayslot,EX_is_delayslot, RF_PC_abort,EX_PC_abort, RF_PC,EX_PC, trap_taken,EX_trapped); @@ -1815,18 +1805,17 @@ begin exNOP; is_busError <= (i_busErr = '0') or (d_busErr = '0'); - ext_event <= is_nmi or is_interr or is_busError; - ext_event_type <= busError_type when is_busError else - exNMI when is_nmi else - exInterr when is_interr else - exNOP; - -- must always check for these - int_event_type <= mem_excp_type when addrError else - exTrap when EX_trapped else - exOvfl when is_ovfl else - IFaddressError when EX_PC_abort else - EX_exception; + EX_is_exception <= busError_type when is_busError else + TLB_excp_type when tlb_exception else + mem_excp_type when addrError else + IFaddressError when EX_PC_abort else + exTrap when EX_trapped else + exOvfl when is_ovfl else + exNMI when is_nmi else + exInterr when is_interr else + EX_exception; + -- ---------------------------------------------------------------------- PIPESTAGE_EXCP_EX_MM: reg_excp_EX_MM @@ -1835,32 +1824,14 @@ begin EX_PC,MM_PC, v_addr,MM_v_addr, nullify,MM_nullify, addrError,MM_addrError, addrErr_stage_mm,MM_addrErr_stage_mm, - mem_excp_type, MM_mem_excp_type, EX_is_delayslot,MM_is_delayslot, EX_trapped,MM_trapped, SL2BOOL(LL_SC_abort), MM_ll_sc_abort, tlb_exception,MM_tlb_exception, - tlb_excp_type,MM_tlb_excp_type, tlb_stage_mm,MM_tlb_stage_mm, int_req,MM_int_req, is_SC, MM_is_SC, is_MFC0, MM_is_MFC0, - ext_event, MM_ext_event, - ext_event_type, MM_ext_event_type, - int_event_type, MM_int_event_type); - - -- kkkkk --- is_exception <= MM_ext_event_type when MM_ext_event else --- MM_TLB_excp_type when MM_tlb_exception else --- MM_mem_excp_type when MM_addrError else --- exTrap when MM_trapped else --- exOvfl when MM_ovfl else --- IFaddressError when MM_PC_abort else --- MM_exception; - - is_exception <= MM_ext_event_type when MM_ext_event else - MM_TLB_excp_type when MM_tlb_exception else - MM_int_event_type; - + EX_is_exception, is_exception); -- STATUS -- pg 79 -- cop0_12 -------------------- diff --git a/cMIPS/vhdl/exception.vhd b/cMIPS/vhdl/exception.vhd index b6c60f5..07fc845 100644 --- a/cMIPS/vhdl/exception.vhd +++ b/cMIPS/vhdl/exception.vhd @@ -71,8 +71,6 @@ entity reg_excp_RF_EX is EX_can_trap: out reg2; RF_exception: in exception_type; EX_exception: out exception_type; - RF_trap_instr: in instr_type; - EX_trap_instr: out instr_type; RF_is_delayslot: in std_logic; EX_is_delayslot: out std_logic; RF_PC_abort: in boolean; @@ -97,7 +95,6 @@ begin EX_cop0_sel <= RF_cop0_sel ; EX_can_trap <= RF_can_trap ; EX_exception <= RF_exception ; - EX_trap_instr <= RF_trap_instr ; EX_is_delayslot <= RF_is_delayslot ; EX_PC_abort <= RF_PC_abort ; EX_PC <= RF_PC ; @@ -132,8 +129,6 @@ entity reg_excp_EX_MM is MM_addrError: out boolean; EX_addrErr_stage_mm: in boolean; MM_addrErr_stage_mm: out boolean; - EX_mem_excp_type: in exception_type; - MM_mem_excp_type: out exception_type; EX_is_delayslot: in std_logic; MM_is_delayslot: out std_logic; EX_trapped: in boolean; @@ -142,8 +137,6 @@ entity reg_excp_EX_MM is MM_ll_sc_abort: out boolean; EX_tlb_exception: in boolean; MM_tlb_exception: out boolean; - EX_tlb_excp_type: in exception_type; - MM_tlb_excp_type: out exception_type; EX_tlb_stage_mm: in boolean; MM_tlb_stage_mm: out boolean; EX_int_req: in reg8; @@ -152,12 +145,8 @@ entity reg_excp_EX_MM is MM_is_SC: out boolean; EX_is_MFC0: in boolean; MM_is_MFC0: out boolean; - EX_ext_event: in boolean; - MM_ext_event: out boolean; - EX_ext_event_type: in exception_type; - MM_ext_event_type: out exception_type; - EX_int_event_type: in exception_type; - MM_int_event_type: out exception_type); + EX_is_exception: in exception_type; + MM_is_exception: out exception_type); end reg_excp_EX_MM; architecture funcional of reg_excp_EX_MM is @@ -170,9 +159,7 @@ begin MM_addrError <= FALSE; MM_trapped <= FALSE; MM_tlb_exception <= FALSE; - MM_ext_event <= FALSE; - MM_ext_event_type <= exNOP; - MM_int_event_type <= exNOP; + MM_is_exception <= exNOP; elsif rising_edge(clk) then if ld = '0' then MM_cop0_reg <= EX_cop0_reg ; @@ -182,19 +169,15 @@ begin MM_nullify <= EX_nullify ; MM_addrError <= EX_addrError ; MM_addrErr_stage_mm <= EX_addrErr_stage_mm; - MM_mem_excp_type <= EX_mem_excp_type; MM_is_delayslot <= EX_is_delayslot; MM_trapped <= EX_trapped ; MM_ll_sc_abort <= EX_ll_sc_abort ; MM_tlb_exception <= EX_tlb_exception; - MM_tlb_excp_type <= EX_tlb_excp_type; MM_tlb_stage_MM <= EX_tlb_stage_MM; MM_int_req <= EX_int_req ; MM_is_SC <= EX_is_SC ; MM_is_MFC0 <= EX_is_MFC0 ; - MM_ext_event <= EX_ext_event ; - MM_ext_event_type <= EX_ext_event_type; - MM_int_event_type <= EX_int_event_type; + MM_is_exception <= EX_is_exception; end if; end if; end process; -- GitLab