diff --git a/cMIPS/include/start.s b/cMIPS/include/start.s
index b8ba5df34668ebc05165a6d3c718ff683346a686..d324172d136fddf5dcd66181ebf06fd5d46d4d13 100644
--- a/cMIPS/include/start.s
+++ b/cMIPS/include/start.s
@@ -134,7 +134,7 @@ _start:
 	# set STATUS, c0, hw interrupts IRQ7,IRQ6,IRQ5 enabled, user mode
         li   $k0, c0_status_normal
         mtc0 $k0, c0_status
-
+	ehb
 	
 	jal  main # on returning from main(), MUST go into exit()
 	nop       #   to stop the simulation.
@@ -284,6 +284,7 @@ _excp_0180ret:
                                    #  and do not modify its contents
 	ori  $k0, $k0, M_StatusIEn #  and keep user/kernel mode
 	mtc0 $k0, c0_status	   #  but enable all interrupts
+	ehb
 	eret			   # Return from exception
 
 	.end _excp_0180
@@ -351,6 +352,7 @@ _excp_0200ret:
 	mfc0 $k0, c0_status	   # Read STATUS register
 	ori  $k0, $k0, M_StatusIEn #  and re-enable interrupts
 	mtc0 $k0, c0_status        #  else keep as it was on int entry 	
+	ehb
 	eret			   # Return from interrupt
 	nop
 
diff --git a/cMIPS/vhdl/core.vhd b/cMIPS/vhdl/core.vhd
index ccf6fb437b37af72f01d0a744ad7348a4e409cf3..898c1a708363afde65959e4de1fa13132d445dd8 100644
--- a/cMIPS/vhdl/core.vhd
+++ b/cMIPS/vhdl/core.vhd
@@ -278,6 +278,7 @@ architecture rtl of core is
          C:        out std_logic_vector;
          LO:       out std_logic_vector;
          HI:       out std_logic_vector;
+         wr_hilo:  in  std_logic;
          move_ok:  out std_logic;
          fun:      in  t_alu_fun;
          postn:    in  std_logic_vector;
@@ -1350,7 +1351,7 @@ begin
   alu_inp_B <= alu_fwd_B when (EX_selB = '0') else EX_displ32;
 
   U_ALU: alu port map(clk,rst,
-                      alu_inp_A, alu_inp_B, result, LO, HI,
+                      alu_inp_A, alu_inp_B, result, LO, HI, EX_wreg,
                       alu_move_ok, EX_oper,EX_postn,EX_shamt, ovfl);
 
   
diff --git a/cMIPS/vhdl/units.vhd b/cMIPS/vhdl/units.vhd
index bd43137874ac5b7b20c9b2b05d9210f6cded6b93..01600cb4b8a441b012ab7a8e097b04a461b74e62 100644
--- a/cMIPS/vhdl/units.vhd
+++ b/cMIPS/vhdl/units.vhd
@@ -188,6 +188,7 @@ entity alu is
        C:       out reg32;
        LO:      out reg32;
        HI:      out reg32;
+       wr_hilo: in  std_logic;          -- write to HI & LO, active high
        move_ok: out std_logic;
        fun:     in  t_alu_fun;
        postn:   in  reg5;
@@ -370,9 +371,9 @@ begin
         i_HI := i_prod(63 downto 32);
       when opDIV | opDIVU =>
         if ( B = x"00000000" ) then     -- NO exceptions caused by division
-          -- assert false report
-          --   "div by zero A="& SLV32HEX(A) &"["& integer'image(operation)&"]"
-          --   & SLV32HEX(B); -- DEBUG
+          assert true report
+            "div by zero A="& SLV32HEX(A) &"["& integer'image(operation)&"]"
+            & SLV32HEX(B); -- DEBUG
           i_quoc := x"FFFFFFFF";
           i_rem  := x"FFFFFFFF";
         else
@@ -395,23 +396,23 @@ begin
   end process U_HILO; -- -------------------------------------------
   
   
-  U_hilo_inp: process (A, fun, s_HI, s_LO)
+  U_hilo_inp: process (A, fun, s_HI, s_LO, wr_hilo)
   begin
     wr_lo <= '1';
     wr_hi <= '1';
     case fun is
       when opMULT | opMULTU | opDIV | opDIVU =>
-        wr_lo  <= '0';
-        wr_hi  <= '0';
+        wr_lo  <= not(wr_hilo);
+        wr_hi  <= not(wr_hilo);
         inp_HI <= s_HI;
         inp_LO <= s_LO;
       when opMTLO =>
-        wr_lo  <= '0';
+        wr_lo  <= not(wr_hilo);
         inp_LO <= A;
         wr_hi  <= '1';
         inp_HI <= (others => 'X');                 
       when opMTHI =>
-        wr_hi  <= '0';
+        wr_hi  <= not(wr_hilo);
         inp_HI <= A;
         wr_lo  <= '1';
         inp_LO <= (others => 'X');