From ac8cf6f003dc430aedf0b84b717c386274d926b3 Mon Sep 17 00:00:00 2001
From: Roberto Hexsel <roberto@inf.ufpr.br>
Date: Sat, 15 Apr 2017 09:12:21 -0300
Subject: [PATCH] fixed: HI and LO updated only if MULT/DIV/MOD were not
nullified
---
cMIPS/include/start.s | 4 +++-
cMIPS/vhdl/core.vhd | 3 ++-
cMIPS/vhdl/units.vhd | 17 +++++++++--------
3 files changed, 14 insertions(+), 10 deletions(-)
diff --git a/cMIPS/include/start.s b/cMIPS/include/start.s
index b8ba5df..d324172 100644
--- a/cMIPS/include/start.s
+++ b/cMIPS/include/start.s
@@ -134,7 +134,7 @@ _start:
# set STATUS, c0, hw interrupts IRQ7,IRQ6,IRQ5 enabled, user mode
li $k0, c0_status_normal
mtc0 $k0, c0_status
-
+ ehb
jal main # on returning from main(), MUST go into exit()
nop # to stop the simulation.
@@ -284,6 +284,7 @@ _excp_0180ret:
# and do not modify its contents
ori $k0, $k0, M_StatusIEn # and keep user/kernel mode
mtc0 $k0, c0_status # but enable all interrupts
+ ehb
eret # Return from exception
.end _excp_0180
@@ -351,6 +352,7 @@ _excp_0200ret:
mfc0 $k0, c0_status # Read STATUS register
ori $k0, $k0, M_StatusIEn # and re-enable interrupts
mtc0 $k0, c0_status # else keep as it was on int entry
+ ehb
eret # Return from interrupt
nop
diff --git a/cMIPS/vhdl/core.vhd b/cMIPS/vhdl/core.vhd
index ccf6fb4..898c1a7 100644
--- a/cMIPS/vhdl/core.vhd
+++ b/cMIPS/vhdl/core.vhd
@@ -278,6 +278,7 @@ architecture rtl of core is
C: out std_logic_vector;
LO: out std_logic_vector;
HI: out std_logic_vector;
+ wr_hilo: in std_logic;
move_ok: out std_logic;
fun: in t_alu_fun;
postn: in std_logic_vector;
@@ -1350,7 +1351,7 @@ begin
alu_inp_B <= alu_fwd_B when (EX_selB = '0') else EX_displ32;
U_ALU: alu port map(clk,rst,
- alu_inp_A, alu_inp_B, result, LO, HI,
+ alu_inp_A, alu_inp_B, result, LO, HI, EX_wreg,
alu_move_ok, EX_oper,EX_postn,EX_shamt, ovfl);
diff --git a/cMIPS/vhdl/units.vhd b/cMIPS/vhdl/units.vhd
index bd43137..01600cb 100644
--- a/cMIPS/vhdl/units.vhd
+++ b/cMIPS/vhdl/units.vhd
@@ -188,6 +188,7 @@ entity alu is
C: out reg32;
LO: out reg32;
HI: out reg32;
+ wr_hilo: in std_logic; -- write to HI & LO, active high
move_ok: out std_logic;
fun: in t_alu_fun;
postn: in reg5;
@@ -370,9 +371,9 @@ begin
i_HI := i_prod(63 downto 32);
when opDIV | opDIVU =>
if ( B = x"00000000" ) then -- NO exceptions caused by division
- -- assert false report
- -- "div by zero A="& SLV32HEX(A) &"["& integer'image(operation)&"]"
- -- & SLV32HEX(B); -- DEBUG
+ assert true report
+ "div by zero A="& SLV32HEX(A) &"["& integer'image(operation)&"]"
+ & SLV32HEX(B); -- DEBUG
i_quoc := x"FFFFFFFF";
i_rem := x"FFFFFFFF";
else
@@ -395,23 +396,23 @@ begin
end process U_HILO; -- -------------------------------------------
- U_hilo_inp: process (A, fun, s_HI, s_LO)
+ U_hilo_inp: process (A, fun, s_HI, s_LO, wr_hilo)
begin
wr_lo <= '1';
wr_hi <= '1';
case fun is
when opMULT | opMULTU | opDIV | opDIVU =>
- wr_lo <= '0';
- wr_hi <= '0';
+ wr_lo <= not(wr_hilo);
+ wr_hi <= not(wr_hilo);
inp_HI <= s_HI;
inp_LO <= s_LO;
when opMTLO =>
- wr_lo <= '0';
+ wr_lo <= not(wr_hilo);
inp_LO <= A;
wr_hi <= '1';
inp_HI <= (others => 'X');
when opMTHI =>
- wr_hi <= '0';
+ wr_hi <= not(wr_hilo);
inp_HI <= A;
wr_lo <= '1';
inp_LO <= (others => 'X');
--
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