From c6c42ec6b62e15b31f44d02885356ad320c6f189 Mon Sep 17 00:00:00 2001
From: Roberto Hexsel <roberto@inf.ufpr.br>
Date: Fri, 14 Oct 2016 17:54:14 -0300
Subject: [PATCH] CAUSE always updated -- except if STATUS.EXL=1
---
cMIPS/include/start.s | 1 -
cMIPS/tests/badVAddr.s | 2 +-
cMIPS/tests/interr_x2.s | 2 +-
cMIPS/tests/mmu_inval.s | 2 +-
cMIPS/tests/mmu_inval2.s | 2 +-
cMIPS/tests/mmu_refill.s | 2 +-
cMIPS/tests/mmu_refill2.s | 2 +-
cMIPS/tests/mmu_refill3.s | 2 +-
cMIPS/tests/pt_walk.c | 4 ++--
9 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/cMIPS/include/start.s b/cMIPS/include/start.s
index 5f2ca43..ac090a7 100644
--- a/cMIPS/include/start.s
+++ b/cMIPS/include/start.s
@@ -169,7 +169,6 @@ _excp_0000:
mtc0 $k1, c0_entrylo1 # EntryLo1 <- k1 = odd element
ehb
tlbwr # update TLB
- mfc0 $zero, c0_cause # clear excCode in Cause
eret
.end _excp_0000
diff --git a/cMIPS/tests/badVAddr.s b/cMIPS/tests/badVAddr.s
index 81d611c..74b6d95 100644
--- a/cMIPS/tests/badVAddr.s
+++ b/cMIPS/tests/badVAddr.s
@@ -62,7 +62,7 @@ excp_180:
mfc0 $k0, c0_cause
sw $k0, 0($14) # print CAUSE
- mfc0 $k0, c0_epc # fix return address
+ mfc0 $k0, c0_epc # fix return address
sw $k0, 0($14) # print EPC
addiu $k1, $zero, -4 # -4 = 0xffff.fffc
and $k1, $k1, $k0 # fix the invalid address
diff --git a/cMIPS/tests/interr_x2.s b/cMIPS/tests/interr_x2.s
index 380b84b..72bdfe1 100644
--- a/cMIPS/tests/interr_x2.s
+++ b/cMIPS/tests/interr_x2.s
@@ -139,7 +139,7 @@ lo_pri: lui $k0, %hi(ext_restart)
rf_irq: sw $k1, 0x20($15) # print IRQ source
sw $13, 0x20($15)
- li $k0, 0x1000f003 # CP0active, enable COUNT irq, EXL=1
+ li $k0, 0x1000f001 # CP0active, enable COUNT irq, EXL=0, IE=1
mtc0 $k0, c0_status
eret
#
diff --git a/cMIPS/tests/mmu_inval.s b/cMIPS/tests/mmu_inval.s
index b9099eb..5c43a7c 100644
--- a/cMIPS/tests/mmu_inval.s
+++ b/cMIPS/tests/mmu_inval.s
@@ -36,7 +36,7 @@
.globl _start,_exit
.ent _start
- ## set STATUS, cop0, no interrupts enabled
+ ## set STATUS, cop0, no interrupts enabled, EXL=0
_start: li $k0, 0x10000000
mtc0 $k0, cop0_STATUS
diff --git a/cMIPS/tests/mmu_inval2.s b/cMIPS/tests/mmu_inval2.s
index e171c0d..5187383 100644
--- a/cMIPS/tests/mmu_inval2.s
+++ b/cMIPS/tests/mmu_inval2.s
@@ -36,7 +36,7 @@
.globl _start,_exit
.ent _start
- ## set STATUS, cop0, no interrupts enabled
+ ## set STATUS, cop0, no interrupts enabled, UM=0, EXL=0
_start: li $k0, 0x10000000
mtc0 $k0, cop0_STATUS
diff --git a/cMIPS/tests/mmu_refill.s b/cMIPS/tests/mmu_refill.s
index 9958c11..207a594 100644
--- a/cMIPS/tests/mmu_refill.s
+++ b/cMIPS/tests/mmu_refill.s
@@ -40,7 +40,7 @@
.globl _start
.ent _start
- ## set STATUS, cop0, no interrupts enabled
+ ## set STATUS, cop0, no interrupts enabled, EXL=0
_start: li $k0, 0x10000000
mtc0 $k0, cop0_STATUS
diff --git a/cMIPS/tests/mmu_refill2.s b/cMIPS/tests/mmu_refill2.s
index 1d47ed8..225978d 100644
--- a/cMIPS/tests/mmu_refill2.s
+++ b/cMIPS/tests/mmu_refill2.s
@@ -21,7 +21,7 @@
.globl _start, _exit
.ent _start
- ## set STATUS, cop0, no interrupts enabled, kernel mode
+ ## set STATUS, cop0, no interrupts enabled, UM=0, EXL=0
_start: li $k0, 0x10000000
mtc0 $k0, cop0_STATUS
diff --git a/cMIPS/tests/mmu_refill3.s b/cMIPS/tests/mmu_refill3.s
index 3e7f29b..d3fbc06 100644
--- a/cMIPS/tests/mmu_refill3.s
+++ b/cMIPS/tests/mmu_refill3.s
@@ -37,7 +37,7 @@
.globl _start,_exit
.ent _start
- ## set STATUS, cop0, no interrupts enabled
+ ## set STATUS, cop0, no interrupts enabled, UM=0, EXL=0
_start: li $k0, 0x10000000
mtc0 $k0, cop0_STATUS
diff --git a/cMIPS/tests/pt_walk.c b/cMIPS/tests/pt_walk.c
index fd3a2d7..42bd705 100644
--- a/cMIPS/tests/pt_walk.c
+++ b/cMIPS/tests/pt_walk.c
@@ -17,8 +17,8 @@
//-----------------------------------------------------------------------
// decide on the tests to run
-#define WALK_THE_PT 0
-#define TLB_MODIFIED 1
+#define WALK_THE_PT 1
+#define TLB_MODIFIED 0
#define DOUBLE_FAULT 0
// these will abort the simulation when the fault is detected/handled
--
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