diff --git a/cMIPS/vhdl/tb_cMIPS.vhd b/cMIPS/vhdl/tb_cMIPS.vhd
index c86a12ccfde8d7b961f596a95b9c4c4115b8a737..3f4f552aa14094209157a704134ebcc90bda0cc8 100644
--- a/cMIPS/vhdl/tb_cMIPS.vhd
+++ b/cMIPS/vhdl/tb_cMIPS.vhd
@@ -511,7 +511,7 @@ begin  -- TB
   cpu_d_wait <= data_wait and io_wait;
   io_wait    <= io_lcd_wait and io_fpu_wait;
 
-  not_waiting <= (inst_wait and data_wait and io_wait);
+  not_waiting <= (inst_wait and data_wait); --  and io_wait);
 
   -- irq <= b"000000"; -- NO interrupt requests
   irq <= uart_irq & counter_irq & b"0000"; -- uart+counter interrupts
@@ -905,23 +905,22 @@ architecture behavioral of io_addr_decode is
   constant x_hi   : std_logic_vector(31 downto HI_DEV)  := (others=>'1');
   constant x_lo   : std_logic_vector(HI_DEV-1 downto 0) := (others=>'0');
   constant x_mask : std_logic_vector := x_hi & x_lo;  -- 1..10..0
-  
+
+  signal in_range : boolean;
   signal aVal : std_logic;
   signal dev  : integer;                    -- DEBUGGING only
 begin
 
---   aVal <= '0' when ( cpu_d_aVal = '0' and rst = '1' and not_waiting = '1' and
---                      ((addr and x_mask) = x_IO_BASE_ADDR) ) else
---           '1';
+  -- in_range <= ((addr and x_mask) = x_IO_BASE_ADDR);
+  
+  in_range <= ((addr(HI_ADDR downto LO_ADDR) and in_r) /= ng_r) and
+              ((addr(HI_SEL_BITS downto HI_ADDR+1) and oth) = ng_o);
 
   dev <= to_integer(signed(addr(HI_SEL_ADDR downto LO_SEL_ADDR)));
-   
+  
   aVal <= '0' when ( cpu_d_aVal = '0' and rst = '1' and not_waiting = '1' and
-                     ((addr(HI_ADDR downto LO_ADDR) and in_r) /= ng_r) and
-                     ((addr(HI_SEL_BITS downto HI_ADDR+1) and oth) = ng_o)
-                   ) else
-          '1';
-
+                     in_range ) else '1';
+  
   U_decode: process(clk, aVal, addr, dev)
     variable dev_sel    : reg4;
     constant is_noise   : integer := 0;