diff --git a/cMIPS/v_irx.sav b/cMIPS/v_irx.sav
index d270feb4c17675c87575c9164ac4b7065dbd4f05..66c2a0e603a415a415db0ffb02ed3b0b33f72e38 100644
--- a/cMIPS/v_irx.sav
+++ b/cMIPS/v_irx.sav
@@ -1,20 +1,20 @@
[*]
[*] GTKWave Analyzer v3.3.37 (w)1999-2012 BSI
-[*] Mon Mar 23 00:21:20 2015
+[*] Sun May 17 23:47:43 2015
[*]
[dumpfile] "/home/roberto/cMIPS/v_cMIPS.vcd"
-[dumpfile_mtime] "Mon Mar 23 00:06:43 2015"
-[dumpfile_size] 21610740
-[savefile] "/home/roberto/cmips.git/cMIPS/v_irx.sav"
-[timestart] 6484000000
-[size] 1062 950
-[pos] 854 0
-*-28.000000 7780000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[dumpfile_mtime] "Sun May 17 23:34:01 2015"
+[dumpfile_size] 24210019
+[savefile] "/home/roberto/cMIPS/v_irx.sav"
+[timestart] 6435000000
+[size] 1200 908
+[pos] 676 118
+*-29.000000 7800000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] u_simple_uart.
[sst_width] 210
-[signals_width] 249
+[signals_width] 221
[sst_expanded] 1
-[sst_vpaned_height] 280
+[sst_vpaned_height] 266
@28
clk
@22
diff --git a/cMIPS/v_rx.sav b/cMIPS/v_rx.sav
index 409d8e99a3f039333358bb92234aa8b6b050542b..5b5101b1ec441f6d4281674156e17aef587b2133 100644
--- a/cMIPS/v_rx.sav
+++ b/cMIPS/v_rx.sav
@@ -1,18 +1,18 @@
[*]
[*] GTKWave Analyzer v3.3.37 (w)1999-2012 BSI
-[*] Fri Mar 20 22:47:56 2015
+[*] Sun May 17 23:18:38 2015
[*]
[dumpfile] "/home/roberto/cMIPS/v_cMIPS.vcd"
-[dumpfile_mtime] "Fri Mar 20 22:35:01 2015"
-[dumpfile_size] 21835141
-[savefile] "/home/roberto/cmips.git/cMIPS/v_rx.sav"
-[timestart] 57013700000
+[dumpfile_mtime] "Sun May 17 23:11:59 2015"
+[dumpfile_size] 27081351
+[savefile] "/home/roberto/cMIPS/v_rx.sav"
+[timestart] 56766300000
[size] 1062 914
-[pos] 854 0
-*-27.000000 57200000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[pos] -1 -1
+*-27.000000 56960000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] u_simple_uart.
[sst_width] 210
-[signals_width] 249
+[signals_width] 227
[sst_expanded] 1
[sst_vpaned_height] 267
@28
diff --git a/cMIPS/v_tx.sav b/cMIPS/v_tx.sav
index 740042cb21205adcd89312087678d4369c97269a..261b7313fa421dfee501cd8452607178063ab7de 100644
--- a/cMIPS/v_tx.sav
+++ b/cMIPS/v_tx.sav
@@ -1,33 +1,30 @@
[*]
[*] GTKWave Analyzer v3.3.37 (w)1999-2012 BSI
-[*] Fri Mar 20 22:26:10 2015
+[*] Sun May 17 23:22:05 2015
[*]
[dumpfile] "/home/roberto/cMIPS/v_cMIPS.vcd"
-[dumpfile_mtime] "Fri Mar 20 22:00:50 2015"
-[dumpfile_size] 32537287
-[savefile] "/home/roberto/cmips.git/cMIPS/v_tx.sav"
-[timestart] 83864500000
-[size] 1062 927
-[pos] -1 -1
-*-26.000000 83960000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[dumpfile_mtime] "Sun May 17 23:20:27 2015"
+[dumpfile_size] 22609843
+[savefile] "/home/roberto/cMIPS/v_tx.sav"
+[timestart] 1526000000
+[size] 1062 917
+[pos] 676 109
+*-30.000000 2000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] u_core.
[treeopen] u_core.u_alu.
[treeopen] u_simple_uart.
[sst_width] 210
-[signals_width] 235
+[signals_width] 218
[sst_expanded] 1
-[sst_vpaned_height] 271
+[sst_vpaned_height] 268
@28
clk
-@200
-- fetch
@22
u_core.pc[31:0]
u_core.instr_fetched[31:0]
@200
- decode, reg fetch
@22
-u_core.rf_instruction[31:0]
u_core.regs_a[31:0]
u_core.regs_b[31:0]
@200
@@ -48,16 +45,7 @@ d_addr[31:0]
cpu_d_aval
u_core.mm_wrmem
@22
-cpu_data_inp[31:0]
-cpu_data_out[31:0]
-@200
-- write-back
-@28
-u_core.wb_muxc[2:0]
-u_core.wb_wreg
-@22
-u_core.wb_a_c[4:0]
-u_core.wb_c[31:0]
+u_print_data.data[31:0]
@200
- UART
@28
@@ -80,7 +68,7 @@ u_simple_uart.u_uart.tx_dbg_st[31:0]
u_simple_uart.u_uart.tx_shr_full
u_simple_uart.u_uart.txclk
u_simple_uart.u_uart.txdat
-@22
+@23
u_interrupt_counter.q[29:0]
@200
- REMOTE (fake) UART
@@ -88,7 +76,15 @@ u_interrupt_counter.q[29:0]
u_uart_remota.rx_dbg_st[31:0]
@28
u_uart_remota.recv[7:0]
-@23
+@22
u_uart_remota.recv[7:0]
+@200
+- write-back
+@28
+u_core.wb_muxc[2:0]
+u_core.wb_wreg
+@22
+u_core.wb_a_c[4:0]
+u_core.wb_c[31:0]
[pattern_trace] 1
[pattern_trace] 0
diff --git a/cMIPS/vhdl/altera.vhd b/cMIPS/vhdl/altera.vhd
index f6f43698d2956a7894549eec312296259b829735..38bdea44cfe7f2ca8abe31669dbd09e199745e07 100644
--- a/cMIPS/vhdl/altera.vhd
+++ b/cMIPS/vhdl/altera.vhd
@@ -219,7 +219,7 @@ begin
c0 <= phi0;
c1 <= phi2_dlyd;
- c2 <= phi2;
+ c2 <= phi1;
c3 <= phi3;
c4 <= inclk0;
diff --git a/cMIPS/vhdl/core.vhd b/cMIPS/vhdl/core.vhd
index 0b9fce3079b0bfdc9751a5af5d2e6927d3c2ca0c..4bc95f977f98d535fe076dc0a9cb9cb4dfe68e82 100644
--- a/cMIPS/vhdl/core.vhd
+++ b/cMIPS/vhdl/core.vhd
@@ -1708,7 +1708,7 @@ begin
newSTATUS := STATUS;
i_epc_update := '1';
- i_epc_source := b"000";
+ i_epc_source := EPC_src_PC;
i_excp_PCsel := PCsel_EXC_none; -- PC <= normal processing PC
i_update := '0';
i_update_r := b"00000";
@@ -1751,7 +1751,7 @@ begin
i_stall := '0';
when cop0reg_EPC =>
i_epc_update := '0';
- i_epc_source := b"100"; -- EX_B
+ i_epc_source := EPC_src_B; -- EX_B
i_stall := '0';
when others =>
i_stall := '0';
@@ -1838,27 +1838,27 @@ begin
when BREAK => ExcCode <= cop0code_Bp;
when others => null;
end case;
- newSTATUS(STATUS_EXL) := '1'; -- at exception level
- newSTATUS(STATUS_UM) := '0'; -- enter kernel mode
- newSTATUS(STATUS_IE) := '0'; -- disable interrupts
+ newSTATUS(STATUS_EXL) := '1'; -- at exception level
+ newSTATUS(STATUS_UM) := '0'; -- enter kernel mode
+ newSTATUS(STATUS_IE) := '0'; -- disable interrupts
i_update := '1';
i_update_r := cop0reg_STATUS;
i_stall := '0';
i_epc_update := '0';
- i_nullify := '1'; -- nullify instructions in IF,RF
- if EX_is_delayslot = '1' then -- instr is in delay slot
- i_epc_source := b"010"; -- EX_PC, re-execute branch/jump
+ i_nullify := '1'; -- nullify instructions in IF,RF
+ if EX_is_delayslot = '1' then -- instr is in delay slot
+ i_epc_source := EPC_src_EX; -- EX_PC, re-execute branch/jump
is_delayslot <= EX_is_delayslot;
else
- i_epc_source := b"001"; -- RF_PC
+ i_epc_source := EPC_src_RF; -- RF_PC
is_delayslot <= RF_is_delayslot;
end if;
- i_excp_PCsel := PCsel_EXC_0180; -- PC <= exception_180
+ i_excp_PCsel := PCsel_EXC_0180;-- PC <= exception_180
else
trap_taken <= '0';
end if;
- when exLL => -- load linked (not a real exception)
+ when exLL => -- load linked (not a real exception)
i_update := '1';
i_update_r := cop0reg_LLaddr;
@@ -1883,10 +1883,10 @@ begin
i_nullify := '1'; -- nullify instructions in IF,RF
nullify_EX <= '1'; -- and instruction in EX
if WB_is_delayslot = '1' then -- instr is in delay slot
- i_epc_source := b"101"; -- WB_PC, re-execute branch/jump
+ i_epc_source := EPC_src_WB; -- WB_PC, re-execute branch/jump
is_delayslot <= WB_is_delayslot;
else
- i_epc_source := b"011"; -- offending instr PC is in MM_PC
+ i_epc_source := EPC_src_MM; -- offending instr PC is in MM_PC
is_delayslot <= MM_is_delayslot;
end if;
@@ -1908,7 +1908,7 @@ begin
if is_exception = IFaddressError then
i_nullify := '1'; -- nullify instructions in IF,RF
end if;
- i_epc_source := b"010"; -- bad address is in EXCP_EX_PC
+ i_epc_source := EPC_src_EX; -- bad address is in EXCP_EX_PC
is_delayslot <= EX_is_delayslot;
when exEHB => -- stall processor to clear hazards
@@ -1925,28 +1925,28 @@ begin
when exTLBrefillIF =>
ExcCode <= cop0code_TLBL;
if RF_is_delayslot = '1' then -- instr is in delay slot
- i_epc_source := b"001"; -- RF_PC, re-execute branch/jump
+ i_epc_source := EPC_src_RF; -- RF_PC, re-execute branch/jump
is_delayslot <= RF_is_delayslot;
else
- i_epc_source := b"000"; -- PC
+ i_epc_source := EPC_src_PC; -- PC
is_delayslot <= '0';
end if;
when exTLBrefillRD =>
ExcCode <= cop0code_TLBL;
if MM_is_delayslot = '1' then -- instr is in delay slot
- i_epc_source := b"011"; -- MM_PC, re-execute branch/jump
+ i_epc_source := EPC_src_MM; -- MM_PC, re-execute branch/jump
is_delayslot <= MM_is_delayslot;
else
- i_epc_source := b"010"; -- EX_PC
+ i_epc_source := EPC_src_EX; -- EX_PC
is_delayslot <= EX_is_delayslot;
end if;
when exTLBrefillWR =>
ExcCode <= cop0code_TLBS;
if MM_is_delayslot = '1' then -- instr is in delay slot
- i_epc_source := b"011"; -- EX_PC, re-execute branch/jump
+ i_epc_source := EPC_src_MM; -- MM_PC, re-execute branch/jump
is_delayslot <= MM_is_delayslot;
else
- i_epc_source := b"010"; -- RF_PC
+ i_epc_source := EPC_src_EX; -- EX_PC
is_delayslot <= EX_is_delayslot;
end if;
when others => null;
@@ -1965,37 +1965,37 @@ begin
when exTLBinvalIF | exTLBdblFaultIF =>
ExcCode <= cop0code_TLBL;
if RF_is_delayslot = '1' then -- instr is in delay slot
- i_epc_source := b"001"; -- RF_PC, re-execute branch/jump
+ i_epc_source := EPC_src_RF; -- RF_PC, re-execute branch/jump
is_delayslot <= RF_is_delayslot;
else
- i_epc_source := b"000"; -- PC
+ i_epc_source := EPC_src_PC; -- PC
is_delayslot <= '0';
end if;
when exTLBinvalRD | exTLBdblFaultRD =>
ExcCode <= cop0code_TLBL;
if MM_is_delayslot = '1' then -- instr is in delay slot
- i_epc_source := b"011"; -- MM_PC, re-execute branch/jump
+ i_epc_source := EPC_src_MM; -- MM_PC, re-execute branch/jump
is_delayslot <= MM_is_delayslot;
else
- i_epc_source := b"010"; -- EX_PC
+ i_epc_source := EPC_src_EX; -- EX_PC
is_delayslot <= EX_is_delayslot;
end if;
when exTLBinvalWR | exTLBdblFaultWR =>
ExcCode <= cop0code_TLBS;
if MM_is_delayslot = '1' then -- instr is in delay slot
- i_epc_source := b"011"; -- MM_PC, re-execute branch/jump
+ i_epc_source := EPC_src_MM; -- MM_PC, re-execute branch/jump
is_delayslot <= MM_is_delayslot;
else
- i_epc_source := b"010"; -- EX_PC
+ i_epc_source := EPC_src_EX; -- EX_PC
is_delayslot <= EX_is_delayslot;
end if;
when exTLBmod =>
ExcCode <= cop0code_Mod;
if MM_is_delayslot = '1' then -- instr is in delay slot
- i_epc_source := b"011"; -- MM_PC, re-execute branch/jump
+ i_epc_source := EPC_src_MM; -- MM_PC, re-execute branch/jump
is_delayslot <= MM_is_delayslot;
else
- i_epc_source := b"010"; -- EX_PC
+ i_epc_source := EPC_src_EX; -- EX_PC
is_delayslot <= EX_is_delayslot;
end if;
when others => null;
@@ -2026,10 +2026,10 @@ begin
i_epc_update := '0';
i_nullify := '1'; -- nullify instructions in IF,RF
if EX_is_delayslot = '1' then -- instr is in delay slot
- i_epc_source := b"010"; -- EX_PC, re-execute branch/jump
+ i_epc_source := EPC_src_EX; -- EX_PC, re-execute branch/jump
is_delayslot <= EX_is_delayslot;
else
- i_epc_source := b"001"; -- RF_PC
+ i_epc_source := EPC_src_RF; -- RF_PC
is_delayslot <= RF_is_delayslot;
end if;
i_excp_PCsel := PCsel_EXC_0000; -- PC <= exception_0000
@@ -2050,10 +2050,10 @@ begin
i_epc_update := '0';
i_nullify := '1'; -- nullify instructions in IF,RF
if EX_is_delayslot = '1' then -- instr is in delay slot
- i_epc_source := b"010"; -- EX_PC, re-execute branch/jump
+ i_epc_source := EPC_src_EX; -- EX_PC, re-execute branch/jump
is_delayslot <= EX_is_delayslot;
else
- i_epc_source := b"001"; -- RF_PC
+ i_epc_source := EPC_src_RF; -- RF_PC
is_delayslot <= RF_is_delayslot;
end if;
if CAUSE(CAUSE_IV) = '1' then
@@ -2183,13 +2183,13 @@ begin
-- EPC -- pg 97 -- cop0_14 -------------------
with epc_source select EPCinp <=
- PC when b"000", -- instr fetch exception
- RF_PC when b"001", -- invalid instr exception
- EX_PC when b"010", -- interrupt, eret, overflow
- MM_PC when b"011", -- data memory exception
- alu_fwd_B when b"100", -- mtc0
- WB_PC when others; -- overflow in a branch delay slot
- -- (others => 'X') when others; -- invalid selection
+ PC when EPC_src_PC, -- instr fetch exception
+ RF_PC when EPC_src_RF, -- invalid instr exception
+ EX_PC when EPC_src_EX, -- interrupt, eret, overflow
+ MM_PC when EPC_src_MM, -- data memory exception
+ WB_PC when EPC_src_WB, -- overflow in a branch delay slot
+ alu_fwd_B when EPC_src_B, -- mtc0
+ (others => 'X') when others; -- invalid selection
COP0_EPC: register32 generic map (x"00000000")
port map (clk, rst, epc_update, EPCinp, EPC);
diff --git a/cMIPS/vhdl/packageExcp.vhd b/cMIPS/vhdl/packageExcp.vhd
index 85578fe7c40463dd69035b2481a8cf621688251c..e9aaae067c92caa990bf58a6301215ea357ed7db 100644
--- a/cMIPS/vhdl/packageExcp.vhd
+++ b/cMIPS/vhdl/packageExcp.vhd
@@ -135,7 +135,7 @@ package p_EXCEPTION is
constant CAUSE_ExcCodehi: integer := 6; -- exception code
constant CAUSE_ExcCodelo: integer := 2; -- exception code
- -- Sources of Exception Hnadler's addresses; signal excp_PCsel
+ -- Sources of Exception Handler's addresses; signal excp_PCsel
constant PCsel_EXC_none : reg3 := b"000"; -- no exception
constant PCsel_EXC_EPC : reg3 := b"001"; -- ERET
constant PCsel_EXC_0180 : reg3 := b"010"; -- general exception handler
@@ -143,6 +143,13 @@ package p_EXCEPTION is
constant PCsel_EXC_0100 : reg3 := b"100"; -- TLBmiss entry point
constant PCsel_EXC_0000 : reg3 := b"110"; -- NMI or soft-reset handler
+ -- Sources for EPC; signal EPC_source
+ constant EPC_src_PC : reg3 := b"000"; -- from PC
+ constant EPC_src_RF : reg3 := b"001"; -- from RF pipestage
+ constant EPC_src_EX : reg3 := b"010"; -- from EX pipestage
+ constant EPC_src_MM : reg3 := b"011"; -- from MM pipestage
+ constant EPC_src_WB : reg3 := b"100"; -- from WB pipestage
+ constant EPC_src_B : reg3 := b"101"; -- from B register
end p_EXCEPTION;
diff --git a/cMIPS/vhdl/packageMemory.vhd b/cMIPS/vhdl/packageMemory.vhd
index 16999efaf86bcc0ed67c20f5b5f0aebdafb7d0ea..d8143e47a13e7b86271c11b8d7b98a27b7a07bf0 100644
--- a/cMIPS/vhdl/packageMemory.vhd
+++ b/cMIPS/vhdl/packageMemory.vhd
@@ -208,6 +208,7 @@ package p_MEMORY is
constant tag_zeros : std_logic_vector(PAGE_SZ_BITS downto 0) := (others => '0');
constant tag_ones : std_logic_vector(VABITS-1 downto PAGE_SZ_BITS+1) := (others => '1');
constant tag_mask : reg32 := tag_ones & tag_zeros;
+ constant tag_g : reg32 := x"00000100";
-- physical addresses for 8 ROM pages
@@ -221,25 +222,25 @@ package p_MEMORY is
constant x_ROM_PPN_6 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_ROM_PPN_7 : reg32 := std_logic_vector(to_signed(INST_BASE_ADDR + 7*PAGE_SZ, 32));
- constant MMU_ini_tag_ROM0 : reg32 := x_ROM_PPN_0 and tag_mask;
+ constant MMU_ini_tag_ROM0 : reg32 := (x_ROM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM0 : mmu_dat_reg :=
x_ROM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM1 : mmu_dat_reg :=
x_ROM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
- constant MMU_ini_tag_ROM2 : reg32 := x_ROM_PPN_2 and tag_mask;
+ constant MMU_ini_tag_ROM2 : reg32 := (x_ROM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM2 : mmu_dat_reg :=
x_ROM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM3 : mmu_dat_reg :=
x_ROM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
- constant MMU_ini_tag_ROM4 : reg32 := x_ROM_PPN_4 and tag_mask;
+ constant MMU_ini_tag_ROM4 : reg32 := (x_ROM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM4 : mmu_dat_reg :=
x_ROM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM5 : mmu_dat_reg :=
x_ROM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
- constant MMU_ini_tag_ROM6 : reg32 := x_ROM_PPN_6 and tag_mask;
+ constant MMU_ini_tag_ROM6 : reg32 := (x_ROM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_ROM6 : mmu_dat_reg :=
x_ROM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_ROM7 : mmu_dat_reg :=
@@ -257,25 +258,25 @@ package p_MEMORY is
constant x_RAM_PPN_6 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 6*PAGE_SZ, 32));
constant x_RAM_PPN_7 : reg32 := std_logic_vector(to_signed(DATA_BASE_ADDR + 7*PAGE_SZ, 32));
- constant MMU_ini_tag_RAM0 : reg32 := x_RAM_PPN_0 and tag_mask;
+ constant MMU_ini_tag_RAM0 : reg32 := (x_RAM_PPN_0 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM0 : mmu_dat_reg :=
x_RAM_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM1 : mmu_dat_reg :=
x_RAM_PPN_1(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
- constant MMU_ini_tag_RAM2 : reg32 := x_RAM_PPN_2 and tag_mask;
+ constant MMU_ini_tag_RAM2 : reg32 := (x_RAM_PPN_2 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM2 : mmu_dat_reg :=
x_RAM_PPN_2(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM3 : mmu_dat_reg :=
x_RAM_PPN_3(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
- constant MMU_ini_tag_RAM4 : reg32 := x_RAM_PPN_4 and tag_mask;
+ constant MMU_ini_tag_RAM4 : reg32 := (x_RAM_PPN_4 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM4 : mmu_dat_reg :=
x_RAM_PPN_4(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM5 : mmu_dat_reg :=
x_RAM_PPN_5(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
- constant MMU_ini_tag_RAM6 : reg32 := x_RAM_PPN_6 and tag_mask;
+ constant MMU_ini_tag_RAM6 : reg32 := (x_RAM_PPN_6 and tag_mask) or tag_g;
constant MMU_ini_dat_RAM6 : mmu_dat_reg :=
x_RAM_PPN_6(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_RAM7 : mmu_dat_reg :=
@@ -287,7 +288,7 @@ package p_MEMORY is
constant x_IO_PPN_0 : reg32 := std_logic_vector(to_signed(IO_BASE_ADDR + 0*PAGE_SZ, 32));
constant x_IO_PPN_1 : reg32 := std_logic_vector(to_signed(IO_BASE_ADDR + 1*PAGE_SZ, 32));
- constant MMU_ini_tag_IO : reg32 := x_IO_BASE_ADDR and tag_mask;
+ constant MMU_ini_tag_IO : reg32 := (x_IO_BASE_ADDR and tag_mask) or tag_g;
constant MMU_ini_dat_IO0 : mmu_dat_reg :=
x_IO_PPN_0(PABITS-1 downto PAGE_SZ_BITS) & b"000111"; -- d,v,g=1
constant MMU_ini_dat_IO1 : mmu_dat_reg :=
diff --git a/cMIPS/vhdl/tb_cMIPS.vhd b/cMIPS/vhdl/tb_cMIPS.vhd
index e87a1384ee7566d3d62c6a3d5d15dcf8324c148a..b6557a1c3a22249246f6654ec0e6729abbbabb49 100644
--- a/cMIPS/vhdl/tb_cMIPS.vhd
+++ b/cMIPS/vhdl/tb_cMIPS.vhd
@@ -603,7 +603,7 @@ begin -- TB
uart_cts <= '1';
- start_remota <= '0', '1' after 400*CLOCK_PER;
+ start_remota <= '0', '1' after 200*CLOCK_PER;
U_uart_remota: remota generic map ("serial.out","serial.inp")
port map (rst, clk, start_remota, uart_txd, uart_rxd, bit_rt);