diff --git a/cMIPS/include/cMIPS.s b/cMIPS/include/cMIPS.s index ae9a8578bee915a007d74a95241258beb6f5a0a1..8a8e876143dbd6c7435c8cea4dc561848665a0c0 100644 --- a/cMIPS/include/cMIPS.s +++ b/cMIPS/include/cMIPS.s @@ -18,7 +18,7 @@ # see vhdl/packageExcp.vhd for addresses .set x_EXCEPTION_0000,0x00000080 - .set x_EXCEPTION_0180,0x000000c0 + .set x_EXCEPTION_0180,0x000000C0 .set x_EXCEPTION_0200,0x00000140 .set x_ENTRY_POINT,0x00000300 diff --git a/cMIPS/vhdl/.last_import b/cMIPS/vhdl/.last_import deleted file mode 100644 index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..0000000000000000000000000000000000000000 diff --git a/cMIPS/vhdl/altera.o b/cMIPS/vhdl/altera.o deleted file mode 100644 index 525c7cca611963a53c9043776597597e36cba186..0000000000000000000000000000000000000000 Binary files a/cMIPS/vhdl/altera.o and /dev/null differ diff --git a/cMIPS/vhdl/aux.o b/cMIPS/vhdl/aux.o deleted file mode 100644 index bf2a616843e9f9a8f07e31e942c2e6f807ac33cc..0000000000000000000000000000000000000000 Binary files a/cMIPS/vhdl/aux.o and /dev/null differ diff --git a/cMIPS/vhdl/cache.o b/cMIPS/vhdl/cache.o deleted file mode 100644 index 1c9c7141cd10ff4cd0d5deaca2f48bb0014e4eb2..0000000000000000000000000000000000000000 Binary files a/cMIPS/vhdl/cache.o and /dev/null differ diff --git a/cMIPS/vhdl/core.o b/cMIPS/vhdl/core.o deleted file mode 100644 index cc33fc4e57c1b5f830f85f525b1153fdb9ef19b8..0000000000000000000000000000000000000000 Binary files a/cMIPS/vhdl/core.o and /dev/null differ diff --git a/cMIPS/vhdl/exception.o b/cMIPS/vhdl/exception.o deleted file mode 100644 index c79d3aef892c64fdb6bb28d6bfb647b61ddd47dc..0000000000000000000000000000000000000000 Binary files a/cMIPS/vhdl/exception.o and /dev/null differ diff --git a/cMIPS/vhdl/e~tb_cmips.o b/cMIPS/vhdl/e~tb_cmips.o deleted file mode 100644 index dd130995d38c991035dd6348bb446ee2faab72a2..0000000000000000000000000000000000000000 Binary files a/cMIPS/vhdl/e~tb_cmips.o and /dev/null differ diff --git a/cMIPS/vhdl/io.o b/cMIPS/vhdl/io.o deleted file mode 100644 index 54832266bb78857a58847fff185291fea5a07ce0..0000000000000000000000000000000000000000 Binary files a/cMIPS/vhdl/io.o and /dev/null differ diff --git a/cMIPS/vhdl/macnica.o b/cMIPS/vhdl/macnica.o deleted file mode 100644 index a71432bafdbd48211c7239817a4f8d6752ad6ba0..0000000000000000000000000000000000000000 Binary files a/cMIPS/vhdl/macnica.o and /dev/null differ diff --git a/cMIPS/vhdl/memory.o b/cMIPS/vhdl/memory.o deleted file mode 100644 index eb88c6adfa64151d34f0650d89fc1cd8a59172ab..0000000000000000000000000000000000000000 Binary files a/cMIPS/vhdl/memory.o and /dev/null differ diff --git a/cMIPS/vhdl/packageExcp.o b/cMIPS/vhdl/packageExcp.o deleted file mode 100644 index 660a0bc321e398cc34da4addd2ceb8c3a3f851dd..0000000000000000000000000000000000000000 Binary files a/cMIPS/vhdl/packageExcp.o and /dev/null differ diff --git a/cMIPS/vhdl/packageMemory.o b/cMIPS/vhdl/packageMemory.o deleted file mode 100644 index 496502efe8d212745b79b7b0b3823bf0b33e9f90..0000000000000000000000000000000000000000 Binary files a/cMIPS/vhdl/packageMemory.o and /dev/null differ diff --git a/cMIPS/vhdl/packageWires.o b/cMIPS/vhdl/packageWires.o deleted file mode 100644 index f6f20fa9a3002e1c5e5858f38c158e23c1ec9977..0000000000000000000000000000000000000000 Binary files a/cMIPS/vhdl/packageWires.o and /dev/null differ diff --git a/cMIPS/vhdl/pipestages.o b/cMIPS/vhdl/pipestages.o deleted file mode 100644 index 645729c3f1dac869ff3f864d84eed57bb96d2ae6..0000000000000000000000000000000000000000 Binary files a/cMIPS/vhdl/pipestages.o and /dev/null differ diff --git a/cMIPS/vhdl/remota.vhd b/cMIPS/vhdl/remota.vhd deleted file mode 100644 index 2f12dd5c34c69c64d2c279511123642e45bab0a2..0000000000000000000000000000000000000000 --- a/cMIPS/vhdl/remota.vhd +++ /dev/null @@ -1,360 +0,0 @@ --- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --- UFPR, BCC, ci212 2013-2 trabalho semestral, autor: Roberto Hexsel, 01nov --- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - --- ESTE ARQUIVO NAO PODE SER ALTERADO - --- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ --- modelo funcional do computador remoto --- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ -library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use std.textio.all; -use work.p_WIRES.all; - - -entity remota is - generic(OUTPUT_FILE_NAME : string := "serial.out"; - INPUT_FILE_NAME : string := "serial.inp"); - port(rst, clk : in std_logic; - start : in std_logic; -- start operation =1 - inpDat : in std_logic; -- serial input - outDat : out std_logic; -- serial output - bit_rt : in reg3); -- selects bit rate -end remota; - -architecture behavior of remota is - - component counter8 is - port(rel, rst, ld, en: in std_logic; - D: in std_logic_vector; - Q: out std_logic_vector); - end component counter8; - - - -- transmission signals & states ----------------------------------------- - type tx_state is (st_init, st_idle, st_start, - st_b0, st_b1, st_b2, st_b3, st_b4, st_b5, st_b6, st_b7, - st_stop, st_wait, st_done); - signal tx_current_st, tx_next_st : tx_state; - signal tx_dbg_st : integer; -- for debugging only - - signal tx_bit_rt : reg8; - signal tx_clk, tx_run : std_logic; - - file input_stream : text open read_mode is INPUT_FILE_NAME; - -- file input_stream : text open read_mode is "STD_INPUT"; - -- ----------------------------------------------------------------------- - - -- reception signals & states -------------------------------------------- - type rx_state is (st_idle, st_check, st_start, - st_b0, st_b1, st_b2, st_b3, st_b4, st_b5, st_b6, st_b7, - st_stop, st_done); - signal rx_current_st, rx_next_st : rx_state; - signal rx_dbg_st : integer; -- for debugging only - - signal recv, rx_bit_rt : reg8; - signal rx_clk, rx_run, reset_rxck : std_logic; - - signal tx_baud_div, rx_baud_div : integer := 0; - - -- file output_stream : text open write_mode is OUTPUT_FILE_NAME; - file output_stream : text open write_mode is "STD_OUTPUT"; - -- ----------------------------------------------------------------------- - - -begin - - -- transmission control SM ---------------------------------------------- - U_TX_st_reg: process(rst,tx_clk) - begin - if rst = '0' then - tx_current_st <= st_wait; - elsif rising_edge(tx_clk) then - tx_current_st <= tx_next_st; - end if; - end process U_TX_st_reg; - - tx_dbg_st <= integer(tx_state'pos(tx_current_st)); -- debugging only - - U_tx: process (tx_current_st, start) - variable sentence : line; - variable char : character; - variable good, send_null : boolean; - variable bfr : reg8; - variable j : integer; - begin - - case tx_current_st is - when st_wait => -- 12 wait for starting signal - outDat <= '1'; - tx_run <= '0'; -- hold TX clock - send_null := FALSE; - if start = '0' then - tx_next_st <= st_wait; - else - if not endfile(input_stream) then - readline( input_stream, sentence ); -- read first line of text - -- assert false report "fst line: "&integer'image(sentence'length); - j := 1; - tx_next_st <= st_init; - else - tx_next_st <= st_done; -- no input, done! - end if; - end if; - when st_init => -- 0 - outDat <= '1'; - tx_run <= '1'; -- start TX clock - tx_next_st <= st_idle; - when st_idle => -- 1 - if not endfile(input_stream) then - if j > sentence'right then -- read new line of input - readline( input_stream, sentence ); - -- assert false report "new line: "&integer'image(sentence'length); - bfr := x"0a"; -- new line - j := 0; - elsif sentence'length = 0 then - bfr := x"0a"; -- send new line for empty line - -- assert false report "empty line: " & integer'image(j)&" " & LF; - else - read (sentence, char, good); - -- assert false report "read: " & integer'image(j) & " " &char; - bfr := std_logic_vector(to_signed( character'pos(char), 8)); - end if; - tx_next_st <= st_start; - else - tx_next_st <= st_done; -- no more input, done! - end if; - when st_start => -- 2 - outDat <= '0'; - tx_next_st <= st_b0; - when st_b0 => -- 3 - outDat <= bfr(0); - tx_next_st <= st_b1; - when st_b1 => -- 4 - outDat <= bfr(1); - tx_next_st <= st_b2; - when st_b2 => -- 5 - outDat <= bfr(2); - tx_next_st <= st_b3; - when st_b3 => -- 6 - outDat <= bfr(3); - tx_next_st <= st_b4; - when st_b4 => -- 7 - outDat <= bfr(4); - tx_next_st <= st_b5; - when st_b5 => -- 8 - outDat <= bfr(5); - tx_next_st <= st_b6; - when st_b6 => -- 9 - outDat <= bfr(6); - tx_next_st <= st_b7; - when st_b7 => -- 10 - outDat <= bfr(7); - tx_next_st <= st_stop; - when st_stop => -- 11 - j := j + 1; - outDat <= '1'; - tx_next_st <= st_idle; - when st_done => -- 13 wait forever - if send_null = FALSE then - bfr := x"00"; -- send out a NULL character - send_null := TRUE; - tx_next_st <= st_start; - else - tx_next_st <= st_done; -- no more input, done! - outDat <= '1'; - end if; - tx_run <= '0'; -- stop clock - when others => - assert false report "REMOTE TX stateMachine broken" - & integer'image(tx_state'pos(tx_current_st)) severity failure; - end case; - - end process U_tx; - -- ====================================================================== - - - - -- reception ============================================================ - - -- reception control SM ------------------------------------------------- - U_RX_st_reg: process(rst,clk) - begin - if rst = '0' then - rx_current_st <= st_idle; - elsif rising_edge(clk) then - rx_current_st <= rx_next_st; - end if; - end process U_RX_st_reg; - - rx_dbg_st <= integer(rx_state'pos(rx_current_st)); -- debugging only - - U_rx: process(rx_current_st, rx_clk, inpDat) - variable msg : line; - begin - case rx_current_st is - when st_idle => - reset_rxck <= '0'; - rx_run <= '0'; - recv <= (others => 'U'); - if falling_edge(inpDat) then -- start bit - rx_next_st <= st_check; - else - rx_next_st <= st_idle; - end if; - when st_check => - reset_rxck <= '1'; - rx_run <= '1'; - rx_next_st <= st_start; - when st_start => - reset_rxck <= '0'; - -- if rising_edge(rx_clk) then - rx_next_st <= st_b0; - -- else - -- rx_next_st <= st_start; - -- end if; - when st_b0 => - if falling_edge(rx_clk) then - recv(0) <= inpDat; - rx_next_st <= st_b1; - else - rx_next_st <= st_b0; - end if; - when st_b1 => - if falling_edge(rx_clk) then - recv(1) <= inpDat; - rx_next_st <= st_b2; - else - rx_next_st <= st_b1; - end if; - when st_b2 => - if falling_edge(rx_clk) then - recv(2) <= inpDat; - rx_next_st <= st_b3; - else - rx_next_st <= st_b2; - end if; - when st_b3 => - if falling_edge(rx_clk) then - recv(3) <= inpDat; - rx_next_st <= st_b4; - else - rx_next_st <= st_b3; - end if; - when st_b4 => - if falling_edge(rx_clk) then - recv(4) <= inpDat; - rx_next_st <= st_b5; - else - rx_next_st <= st_b4; - end if; - when st_b5 => - if falling_edge(rx_clk) then - recv(5) <= inpDat; - rx_next_st <= st_b6; - else - rx_next_st <= st_b5; - end if; - when st_b6 => - if falling_edge(rx_clk) then - recv(6) <= inpDat; - rx_next_st <= st_b7; - else - rx_next_st <= st_b6; - end if; - when st_b7 => - if falling_edge(rx_clk) then - recv(7) <= inpDat; - rx_next_st <= st_stop; - else - rx_next_st <= st_b7; - end if; - when st_stop => - if falling_edge(rx_clk) then - rx_next_st <= st_done; - else - rx_next_st <= st_stop; - end if; - when st_done => - rx_run <= '0'; - rx_next_st <= st_idle; - - write ( msg, character'val(to_integer( unsigned(recv))) ); - if recv = x"00" or recv = x"0a" then - writeline( output_stream, msg ); - end if; - - when others => - assert false report "REMOTE RX stateMachine broken" - & integer'image(rx_state'pos(rx_current_st)) severity failure; - end case; - end process U_rx; - - - -- baud rate generators --------------------------------------------- - - with bit_rt select - tx_baud_div <= 8/2 when b"000", - 16/2 when b"001", - 32/2 when b"010", - 434/2 when b"011", - 868/2 when b"100", - 1302/2 when b"101", - 1736/2 when b"110", - 2604/2 when others; - -- 3472/2 when b"110", - -- 5208/2 when others; - - U_bit_rt_tx: process(clk, rst) - variable baud_cnt : integer; - begin - if rst = '0' then - baud_cnt := 0; - tx_clk <= '0'; - elsif rising_edge(clk) then - if baud_cnt = tx_baud_div then - tx_clk <= not(tx_clk); - baud_cnt := 1; - else - baud_cnt := baud_cnt + 1; - end if; - end if; - end process U_bit_rt_tx; - - - -- RX clock daud rate - with bit_rt select - rx_baud_div <= 8/2 when b"000", - 16/2 when b"001", - 32/2 when b"010", - 434/2 when b"011", - 868/2 when b"100", - 1302/2 when b"101", - 1736/2 when b"110", - 2604/2 when others; - -- 3472/2 when b"110", - -- 5208/2 when others; - - U_bit_rt_rx: process(clk, rst, reset_rxck, rx_run) - variable baud_cnt : integer; - begin - if rst = '0' then - baud_cnt := 0; - rx_clk <= '0'; - elsif reset_rxck = '1' and rising_edge(clk) then - baud_cnt := 1; - rx_clk <= '0'; - elsif rx_run = '1' and rising_edge(clk) then - if baud_cnt = rx_baud_div then - rx_clk <= not(rx_clk); - baud_cnt := 1; - else - baud_cnt := baud_cnt + 1; - end if; - end if; - end process U_bit_rt_rx; - - -end behavior; --- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ - diff --git a/cMIPS/vhdl/tb_cMIPS.o b/cMIPS/vhdl/tb_cMIPS.o deleted file mode 100644 index 381fd14bb506e6eda10495c0020f929e60bd2711..0000000000000000000000000000000000000000 Binary files a/cMIPS/vhdl/tb_cMIPS.o and /dev/null differ diff --git a/cMIPS/vhdl/uart.o b/cMIPS/vhdl/uart.o deleted file mode 100644 index b57b1db8df897495521b6f6a27d23f8419ed1c15..0000000000000000000000000000000000000000 Binary files a/cMIPS/vhdl/uart.o and /dev/null differ diff --git a/cMIPS/vhdl/units.o b/cMIPS/vhdl/units.o deleted file mode 100644 index d23cc2508aa979559336e42d8cb3af82a31ebf5e..0000000000000000000000000000000000000000 Binary files a/cMIPS/vhdl/units.o and /dev/null differ diff --git a/cMIPS/vhdl/work-obj93.cf b/cMIPS/vhdl/work-obj93.cf deleted file mode 100644 index 7f5121b216f6b477b194b2ed111e5f43e02076bc..0000000000000000000000000000000000000000 --- a/cMIPS/vhdl/work-obj93.cf +++ /dev/null @@ -1,149 +0,0 @@ -v 3 -file . "packageExcp.vhd" "20150314142907.000" "20150319144751.802": - package p_exception at 18( 859) + 0 on 44; -file . "packageMemory.vhd" "20150314142907.000" "20150319144751.497": - package p_memory at 18( 859) + 0 on 13; -file . "packageWires.vhd" "20150314142907.000" "20150319144751.182": - package p_wires at 18( 859) + 0 on 11 body; - package body p_wires at 179( 8849) + 0 on 12; -file . "altera.vhd" "20150314142907.000" "20150319144751.538": - entity mf_alt_add_4 at 25( 1283) + 0 on 14; - architecture functional of mf_alt_add_4 at 33( 1498) + 0 on 15; - entity mf_alt_adder at 41( 1779) + 0 on 16; - architecture functional of mf_alt_adder at 50( 2047) + 0 on 17; - entity mf_alt_add_sub at 58( 2340) + 0 on 18; - architecture functional of mf_alt_add_sub at 69( 2735) + 0 on 19; - entity mf_ram1port at 93( 3592) + 0 on 20; - architecture rtl of mf_ram1port at 108( 4049) + 0 on 21; - entity mf_altpll at 148( 4984) + 0 on 22; - architecture functional of mf_altpll at 162( 5561) + 0 on 23; - entity mf_altpll_io at 203( 6514) + 0 on 24; - architecture functional of mf_altpll_io at 215( 6902) + 0 on 25; - entity mf_altclkctrl at 246( 7617) + 0 on 26; - architecture functional of mf_altclkctrl at 254( 7772) + 0 on 27; -file . "macnica.vhd" "20150314142907.000" "20150319144754.867": - entity display_7seg at 10( 253) + 0 on 119; - architecture behavior of display_7seg at 20( 477) + 0 on 120; - entity teclado_base at 60( 1841) + 0 on 121; - architecture behavior of teclado_base at 72( 2193) + 0 on 122; - entity reset_sync at 120( 3955) + 0 on 123; - architecture rtl of reset_sync at 130( 4200) + 0 on 124; -file . "aux.vhd" "20150314142907.000" "20150319144751.676": - entity register32 at 23( 1054) + 0 on 28; - architecture functional of register32 at 33( 1307) + 0 on 29; - entity registern at 56( 1896) + 0 on 30; - architecture functional of registern at 67( 2278) + 0 on 31; - entity counter32 at 90( 2892) + 0 on 32; - architecture functional of counter32 at 101( 3181) + 0 on 33; - entity countnup at 127( 3858) + 0 on 34; - architecture functional of countnup at 139( 4224) + 0 on 35; - entity count4phases at 172( 5093) + 0 on 36; - architecture functional of count4phases at 182( 5383) + 0 on 37; - entity ffd at 208( 5990) + 0 on 38; - architecture functional of ffd at 216( 6150) + 0 on 39; - entity fft at 239( 6709) + 0 on 40; - architecture functional of fft at 247( 6864) + 0 on 41; - entity subtr32 at 267( 7271) + 0 on 42; - architecture functional of subtr32 at 277( 7541) + 0 on 43; -file . "memory.vhd" "20150314142907.000" "20150319144753.461": - entity simul_rom at 22( 1088) + 0 on 55; - architecture behavioral of simul_rom at 41( 1662) + 0 on 56; - entity simul_ram at 134( 4660) + 0 on 57; - architecture behavioral of simul_ram at 158( 5462) + 0 on 58; -file . "cache.vhd" "20150314142907.000" "20150319144753.090": - entity d_cache at 23( 1157) + 0 on 47; - architecture behavioral of d_cache at 66( 2911) + 0 on 48; - entity fake_d_cache at 401( 15163) + 0 on 49; - architecture behavioral of fake_d_cache at 428( 16271) + 0 on 50; - entity i_cache at 459( 17093) + 0 on 51; - architecture behavioral of i_cache at 493( 18343) + 0 on 52; - entity fake_i_cache at 700( 24428) + 0 on 53; - architecture behavioral of fake_i_cache at 720( 25117) + 0 on 54; -file . "instrcache.vhd" "20150314142907.000" "20150319144750.589": - entity i_cache_fpga at 25( 1106) + 0 on 4; - architecture structural of i_cache_fpga at 67( 2954) + 0 on 4; -file . "ram.vhd" "20150314142907.000" "20150319144750.589": - entity fpga_ram at 23( 1076) + 0 on 4; - architecture rtl of fpga_ram at 49( 2058) + 0 on 4; -file . "rom.vhd" "20150314142907.000" "20150319144750.590": - entity fpga_rom at 22( 1081) + 0 on 4; - architecture rtl of fpga_rom at 41( 1725) + 0 on 4; - entity single_port_rom at 99( 3489) + 0 on 4; - architecture rtl of single_port_rom at 112( 3806) + 0 on 4; -file . "units.vhd" "20150314142907.000" "20150319144754.409": - entity ram_dual at 23( 1076) + 0 on 96; - architecture rtl of ram_dual at 38( 1508) + 0 on 97; - entity reg_bank at 73( 2343) + 0 on 98; - architecture rtl of reg_bank at 89( 2808) + 0 on 99; - architecture dual_port_ram of reg_bank at 133( 4272) + 0 on 100; - entity alu at 180( 5838) + 0 on 101; - architecture functional of alu at 198( 6239) + 0 on 102; - entity mask_off_bits at 472( 15345) + 0 on 103; - architecture table of mask_off_bits at 480( 15525) + 0 on 104; - entity shift_left32 at 524( 16557) + 0 on 105; - architecture functional of shift_left32 at 533( 16743) + 0 on 106; - entity shift_right32 at 566( 17815) + 0 on 107; - architecture functional of shift_right32 at 576( 18033) + 0 on 108; - entity wait_states at 615( 19456) + 0 on 109; - architecture structural of wait_states at 626( 19783) + 0 on 110; -file . "io.vhd" "20150314142907.000" "20150319144753.606": - entity print_data at 24( 1098) + 0 on 59; - architecture behavioral of print_data at 40( 1472) + 0 on 60; - entity to_stdout at 65( 2136) + 0 on 61; - architecture behavioral of to_stdout at 81( 2530) + 0 on 62; - entity write_data_file at 113( 3512) + 0 on 63; - architecture behavioral of write_data_file at 132( 4022) + 0 on 64; - entity read_data_file at 174( 5341) + 0 on 65; - architecture behavioral of read_data_file at 192( 5813) + 0 on 66; - entity do_interrupt at 252( 7710) + 0 on 67; - architecture behavioral of do_interrupt at 271( 8344) + 0 on 68; - entity simple_uart at 335( 10288) + 0 on 69; - architecture behavioral of simple_uart at 356( 11062) + 0 on 70; - entity sys_stats at 410( 13019) + 0 on 71; - architecture behavioral of sys_stats at 431( 13601) + 0 on 72; - entity to_7seg at 465( 14512) + 0 on 73; - architecture behavioral of to_7seg at 483( 15000) + 0 on 74; - entity read_keys at 527( 16258) + 0 on 75; - architecture behavioral of read_keys at 547( 16973) + 0 on 76; - entity lcd_display at 699( 21991) + 0 on 77; - architecture behavioral of lcd_display at 720( 22782) + 0 on 78; -file . "uart.vhd" "20150314142907.000" "20150319144754.954": - entity uart_int at 51( 2177) + 0 on 125; - architecture estrutural of uart_int at 67( 2899) + 0 on 126; - entity register8 at 642( 20610) + 0 on 127; - architecture functional of register8 at 651( 20811) + 0 on 128; - entity par_ser10 at 674( 21415) + 0 on 129; - architecture functional of par_ser10 at 683( 21640) + 0 on 130; - entity ser_par10 at 709( 22424) + 0 on 131; - architecture functional of ser_par10 at 718( 22637) + 0 on 132; -file . "pipestages.vhd" "20150314142907.000" "20150319144754.259": - entity reg_if_rf at 27( 1198) + 0 on 88; - architecture funcional of reg_if_rf at 39( 1465) + 0 on 89; - entity reg_rf_ex at 61( 2020) + 0 on 90; - architecture funcional of reg_rf_ex at 104( 3294) + 0 on 91; - entity reg_ex_mm at 142( 4374) + 0 on 92; - architecture funcional of reg_ex_mm at 179( 5466) + 0 on 93; - entity reg_mm_wb at 215( 6508) + 0 on 94; - architecture funcional of reg_mm_wb at 246( 7366) + 0 on 95; -file . "exception.vhd" "20150314142907.000" "20150319144754.775": - entity reg_excp_if_rf at 27( 1213) + 0 on 111; - architecture funcional of reg_excp_if_rf at 39( 1533) + 0 on 112; - entity reg_excp_rf_ex at 57( 2035) + 0 on 113; - architecture funcional of reg_excp_rf_ex at 89( 3116) + 0 on 114; - entity reg_excp_ex_mm at 120( 4170) + 0 on 115; - architecture funcional of reg_excp_ex_mm at 142( 4837) + 0 on 116; - entity reg_excp_mm_wb at 169( 5660) + 0 on 117; - architecture funcional of reg_excp_mm_wb at 191( 6327) + 0 on 118; -file . "core.vhd" "20150314142907.000" "20150319144751.842": - entity core at 22( 1024) + 0 on 45; - architecture rtl of core at 49( 1730) + 0 on 46; -file . "tb_cMIPS.vhd" "20150314142907.000" "20150319144753.957": - entity tb_cmips at 23( 1042) + 0 on 79; - architecture tb of tb_cmips at 32( 1191) + 0 on 80; - entity inst_addr_decode at 638( 24146) + 0 on 81; - architecture behavioral of inst_addr_decode at 653( 24692) + 0 on 82; - entity ram_addr_decode at 669( 25271) + 0 on 83; - architecture behavioral of ram_addr_decode at 685( 25868) + 0 on 84; - entity io_addr_decode at 708( 26711) + 0 on 85; - architecture behavioral of io_addr_decode at 736( 28170) + 0 on 86; - configuration cfg_tb at 821( 31433) + 0 on 87;