Adição de .vhd

ADD.vhd

+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+--  Complete implementation of Patterson and Hennessy single cycle MIPS processor
+--  Copyright (C) 2015  Darci Luiz Tomasi Junior
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, version 3.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--  Engineer: 	Darci Luiz Tomasi Junior
+--	 E-mail: 	dltj007@gmail.com
+--  Date :    	08/07/2015 - 18:58
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.all;
+
+ENTITY ADD IS
+	PORT(
+		IN_A :						IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		IN_B :						IN	STD_LOGIC_VECTOR(31 DOWNTO 0);
+		OUT_A :						OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END ADD;
+
+ARCHITECTURE ARC_ADD OF ADD IS
+
+BEGIN
+
+	OUT_A <= STD_LOGIC_VECTOR (UNSIGNED(IN_A ) + UNSIGNED(IN_B));
+
+END ARC_ADD;
+

ADD_PC.vhd

+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+--  Complete implementation of Patterson and Hennessy single cycle MIPS processor
+--  Copyright (C) 2015  Darci Luiz Tomasi Junior
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, version 3.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--  Engineer: 	Darci Luiz Tomasi Junior
+--	 E-mail: 	dltj007@gmail.com
+--  Date :    	01/07/2015 - 20:00
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+ENTITY ADD_PC IS
+	PORT(
+		IN_A :		IN 		STD_LOGIC_VECTOR(31 DOWNTO 0);
+		OUT_A :		OUT		STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END ADD_PC;
+
+ARCHITECTURE ARC_ADD_PC OF ADD_PC IS
+	CONSTANT PC_INCREMENT :			UNSIGNED(31 DOWNTO 0):= X"00000004";
+
+BEGIN
+	OUT_A <= STD_LOGIC_VECTOR(UNSIGNED(IN_A) + PC_INCREMENT);
+
+END ARC_ADD_PC;
+

AND.vhd

+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+--  Complete implementation of Patterson and Hennessy single cycle MIPS processor
+--  Copyright (C) 2015  Darci Luiz Tomasi Junior
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, version 3.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--  Engineer: 	Darci Luiz Tomasi Junior
+--	 E-mail: 	dltj007@gmail.com
+--  Date :    	05/08/2015 - 20:35
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY AND_1 IS
+	PORT(
+		Branch :		 		IN  	STD_LOGIC;
+		IN_A :				IN		STD_LOGIC;
+		OUT_A  :				OUT	STD_LOGIC
+	);
+END AND_1;
+
+ARCHITECTURE ARC_AND_1 OF AND_1 IS
+
+BEGIN
+	OUT_A <= Branch AND IN_A;
+
+END ARC_AND_1;
+

CONCAT.vhd

+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+--  Complete implementation of Patterson and Hennessy single cycle MIPS processor
+--  Copyright (C) 2015  Darci Luiz Tomasi Junior
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, version 3.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--  Engineer: 	Darci Luiz Tomasi Junior
+--	 E-mail: 	dltj007@gmail.com
+--  Date :    	05/08/2015 - 22:02
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY CONCAT IS
+	PORT(
+		IN_A :					IN 			STD_LOGIC_VECTOR(31 DOWNTO 0);
+		IN_B :					IN				STD_LOGIC_VECTOR(31 DOWNTO 0);
+		OUT_A :					OUT 			STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END CONCAT;
+
+ARCHITECTURE ARC_CONCAT OF CONCAT IS
+
+	SIGNAL MONTA_OUT_S :				STD_LOGIC_VECTOR(31 DOWNTO 0); 
+
+BEGIN	
+	OUT_A <= IN_B(31 DOWNTO 28) & IN_A(27 DOWNTO 0);
+	
+END ARC_CONCAT;
+

CTRL.vhd

+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+--  Complete implementation of Patterson and Hennessy single cycle MIPS processor
+--  Copyright (C) 2015  Darci Luiz Tomasi Junior
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, version 3.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--  Engineer: 	Darci Luiz Tomasi Junior
+--	 E-mail: 	dltj007@gmail.com
+--  Date :    	25/06/2015 - 19:35
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY CTRL IS
+	PORT(
+		OPCode : 			IN			STD_LOGIC_VECTOR(5 DOWNTO 0);
+		RegDst :				OUT		STD_LOGIC;
+		Jump :				OUT		STD_LOGIC;
+		Branch :				OUT		STD_LOGIC;
+		MemRead :			OUT		STD_LOGIC;
+		MemtoReg :			OUT		STD_LOGIC;
+		ALUOp :				OUT		STD_LOGIC_VECTOR(1 DOWNTO 0);
+		MemWrite :			OUT		STD_LOGIC;
+		ALUSrc :				OUT		STD_LOGIC;
+		RegWrite :			OUT		STD_LOGIC
+	);
+END CTRL;
+
+ARCHITECTURE ARC_CTRL OF CTRL IS
+	
+BEGIN
+	PROCESS(OPCode)
+	BEGIN
+		CASE OPCode IS
+			--TYPE R
+			WHEN "000000" =>  RegDst <=		'1';
+									Jump <=			'0';
+									ALUSrc <=		'0';
+									MemtoReg <=		'0';
+									RegWrite <=		'1';
+									MemRead <=		'0';
+									MemWrite <=		'0';
+									Branch <=		'0';
+									ALUOp(1) <=		'1';
+									ALUOp(0) <=		'0';	
+			--TYPE LW						
+			WHEN "100011" =>  RegDst <= 		'0';
+									Jump <=			'0';
+									ALUSrc <=		'1';
+									MemtoReg <=		'1';
+									RegWrite <=		'1';
+									MemRead <=		'1';
+									MemWrite <=		'0';
+									Branch <=		'0';
+									ALUOp(1) <=		'0';
+									ALUOp(0) <=		'0';
+			--TYPE SW					
+			WHEN "101011" =>  RegDst <=		'0'; --X
+									Jump <=			'0';
+									ALUSrc <=		'1';
+									MemtoReg <=		'0'; --X
+									RegWrite <=		'0';
+									MemRead <=		'0';
+									MemWrite <=		'1';
+									Branch <=		'0';
+									ALUOp(1) <=		'0';
+									ALUOp(0) <=		'0';
+			--TYPE JUMP
+			WHEN "000010" =>  RegDst <=		'0'; --X
+									Jump <=			'1';
+									ALUSrc <=		'0';
+									MemtoReg <=		'0'; --X
+									RegWrite <=		'0';
+									MemRead <=		'0';
+									MemWrite <=		'0';
+									Branch <=		'0';
+									ALUOp(1) <=		'1';
+									ALUOp(0) <=		'0';
+			--TYPE BEQ
+			WHEN OTHERS => 	RegDst <=		'0'; --X
+									Jump <=			'0';
+									ALUSrc <=		'0';
+									MemtoReg <=		'0'; --X
+									RegWrite <=		'0';
+									MemRead <=		'0';
+									MemWrite <=		'0';
+									Branch <=		'1';
+									ALUOp(1) <=		'0';
+									ALUOp(0) <=		'1';	
+									
+		END CASE;
+	END PROCESS;
+
+END ARC_CTRL;
+

EXTEND.vhd

+---------------------------------------------------------------------------------
+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+--  Complete implementation of Patterson and Hennessy single cycle MIPS processor
+--  Copyright (C) 2015  Darci Luiz Tomasi Junior
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, version 3.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--  Engineer: 	Darci Luiz Tomasi Junior
+--	 E-mail: 	dltj007@gmail.com
+--  Date :    	18/06/2015 - 20:12
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
+
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+ENTITY EXTEND_SIGNAL IS
+	PORT(
+		IN_A :				IN		STD_LOGIC_VECTOR (15 DOWNTO 0);
+		OUT_A : 				OUT  	STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END EXTEND_SIGNAL;
+
+ARCHITECTURE ARC_EXTEND_SIGNAL OF EXTEND_SIGNAL IS
+
+BEGIN
+	
+	OUT_A <= STD_LOGIC_VECTOR(RESIZE(SIGNED(IN_A), OUT_A'LENGTH));
+	
+END ARC_EXTEND_SIGNAL;
+
+
+

INST.vhd

+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+--  Complete implementation of Patterson and Hennessy single cycle MIPS processor
+--  Copyright (C) 2015  Darci Luiz Tomasi Junior
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, version 3.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--  Engineer: 	Darci Luiz Tomasi Junior
+--	 E-mail: 	dltj007@gmail.com
+--  Date :    	01/07/2015 - 19:14
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+
+ENTITY INST IS
+	PORT(
+		IN_A :			IN 	STD_LOGIC_VECTOR(31 DOWNTO 0);
+		OUT_A :			OUT	STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END INST;
+
+ARCHITECTURE ARC_INST OF INST IS
+	--DEVE SER 0 TO 255 O ARRAY PARA FACILITAR A LEITURA DO PROGRAMA EM ORDEM CRESCENTE
+	TYPE MEMORY IS ARRAY (0 TO 255) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
+	SIGNAL PROGRAM : MEMORY := (	X"01095024", X"01485025" ,X"014a5020",X"01285022",X"0149582a",X"00004820",X"11490002",X"01284820",X"08100006",X"ae2a0000",X"8e300000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
+													X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
+													X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
+													X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
+													X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
+													X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
+													X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
+													X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
+													X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
+													X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
+													X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
+													X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
+													X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
+													X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
+													X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
+													X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000"	);
+	BEGIN
+		--O FATOR - X"00400000"  DEVIDO AO INCIO DAS INSTRUES NO SOFTWARE MARS
+		OUT_A <= PROGRAM(TO_INTEGER((UNSIGNED(IN_A) - X"00400000") SRL 2));
+	
+END ARC_INST;
+

MAIN_CTTRL.vhd

+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+--  Complete implementation of Patterson and Hennessy single cycle MIPS processor
+--  Copyright (C) 2015  Darci Luiz Tomasi Junior
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, version 3.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--  Engineer: 	Darci Luiz Tomasi Junior
+--	 E-mail: 	dltj007@gmail.com
+--  Date :    	01/07/2015 - 22:08 
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+ENTITY MAIN_PROCESSOR IS
+	PORT(
+		CLK :										IN 				STD_LOGIC;
+		RESET :									IN 				STD_LOGIC
+	);
+END MAIN_PROCESSOR;
+
+ARCHITECTURE ARC_MAIN_PROCESSOR OF MAIN_PROCESSOR IS
+
+	COMPONENT ADD_PC IS
+		PORT(
+			IN_A :			IN 		STD_LOGIC_VECTOR(31 DOWNTO 0);
+			OUT_A :			OUT		STD_LOGIC_VECTOR(31 DOWNTO 0)
+		);
+	END COMPONENT;
+
+	COMPONENT ADD IS
+		PORT(
+			IN_A :			IN 		STD_LOGIC_VECTOR(31 DOWNTO 0);
+			IN_B :			IN			STD_LOGIC_VECTOR(31 DOWNTO 0);
+			OUT_A :			OUT 		STD_LOGIC_VECTOR(31 DOWNTO 0)
+		);
+	END COMPONENT;
+	
+	COMPONENT AND_1 IS
+		PORT(
+			Branch :		 	IN  		STD_LOGIC;
+			IN_A :			IN			STD_LOGIC;
+			OUT_A  :			OUT		STD_LOGIC
+		);
+	END COMPONENT;	
+
+	COMPONENT CONCAT IS
+		PORT(
+			IN_A :			IN 		STD_LOGIC_VECTOR(31 DOWNTO 0);
+			IN_B :			IN			STD_LOGIC_VECTOR(31 DOWNTO 0);
+			OUT_A :			OUT 		STD_LOGIC_VECTOR(31 DOWNTO 0)
+		);
+	END COMPONENT;
+	
+	COMPONENT CTRL IS
+		PORT(
+			OPCode : 		IN			STD_LOGIC_VECTOR(5 DOWNTO 0);
+			RegDst :			OUT		STD_LOGIC;
+			Jump :			OUT		STD_LOGIC;
+			Branch :			OUT		STD_LOGIC;
+			MemRead :		OUT		STD_LOGIC;
+			MemtoReg :		OUT		STD_LOGIC;
+			ALUOp :			OUT		STD_LOGIC_VECTOR(1 DOWNTO 0);
+			MemWrite :		OUT		STD_LOGIC;
+			ALUSrc :			OUT		STD_LOGIC;
+			RegWrite :		OUT		STD_LOGIC
+		);
+	END COMPONENT;
+	
+	COMPONENT EXTEND_SIGNAL IS
+		PORT(
+			IN_A :			IN			STD_LOGIC_VECTOR (15 DOWNTO 0);
+			OUT_A : 			OUT  		STD_LOGIC_VECTOR (31 DOWNTO 0)
+		);
+	END COMPONENT;
+	
+	COMPONENT INST IS
+		PORT(
+			IN_A :			IN 		STD_LOGIC_VECTOR(31 DOWNTO 0);
+			OUT_A :			OUT		STD_LOGIC_VECTOR(31 DOWNTO 0)
+		);
+	END COMPONENT;
+	
+	COMPONENT MEM IS
+		PORT(
+			CLK :				IN 		STD_LOGIC;
+			RESET :			IN 		STD_LOGIC;
+			MemWrite :		IN 		STD_LOGIC;
+			MemRead :		IN 		STD_LOGIC;
+			IN_A :			IN 		STD_LOGIC_VECTOR(31 DOWNTO 0); 
+			IN_B :			IN 		STD_LOGIC_VECTOR(31 DOWNTO 0);
+			OUT_A :			OUT 		STD_LOGIC_VECTOR(31 DOWNTO 0)
+		);
+	END COMPONENT;
+	
+	COMPONENT MX_1 IS
+		PORT(
+			RegDst :			IN			STD_LOGIC;	
+			IN_A :			IN 		STD_LOGIC_VECTOR(4 DOWNTO 0);
+			IN_B :			IN			STD_LOGIC_VECTOR(4 DOWNTO 0);
+			OUT_A :			OUT 		STD_LOGIC_VECTOR(4 DOWNTO 0)
+		);
+	END COMPONENT;
+	
+	COMPONENT MX_2 IS
+		PORT(
+			AluSrc :			IN			STD_LOGIC;
+			IN_A :			IN 		STD_LOGIC_VECTOR(31 DOWNTO 0);
+			IN_B : 			IN  		STD_LOGIC_VECTOR(31 DOWNTO 0);
+			OUT_A :			OUT		STD_LOGIC_VECTOR(31 DOWNTO 0)			
+		);
+	END COMPONENT;
+	
+	COMPONENT MX_3 IS
+		PORT(
+			IN_A :			IN 		STD_LOGIC_VECTOR(31 DOWNTO 0);
+			IN_B :			IN 		STD_LOGIC_VECTOR(31 DOWNTO 0);
+			IN_C :			IN 		STD_LOGIC;
+			OUT_A :			OUT 		STD_LOGIC_VECTOR(31 DOWNTO 0)
+		);
+	END COMPONENT;
+	
+	COMPONENT MX_4 IS
+		PORT(
+			Jump :			IN 		STD_LOGIC;
+			IN_A :			IN 		STD_LOGIC_VECTOR(31 DOWNTO 0);
+			IN_B :			IN 		STD_LOGIC_VECTOR(31 DOWNTO 0);
+			OUT_A :			OUT 		STD_LOGIC_VECTOR(31 DOWNTO 0)
+		);
+	END COMPONENT;
+	
+	COMPONENT MX_5 IS
+		PORT(
+			MemtoReg :		IN 		STD_LOGIC;
+			IN_A :			IN 		STD_LOGIC_VECTOR(31 DOWNTO 0);
+			IN_B :			IN 		STD_LOGIC_VECTOR(31 DOWNTO 0);
+			OUT_A :			OUT 		STD_LOGIC_VECTOR(31 DOWNTO 0)
+		);
+	END COMPONENT;
+	
+	COMPONENT PC IS
+		PORT(
+			CLK :				IN			STD_LOGIC;
+			RESET :			IN			STD_LOGIC;
+			IN_A :			IN 		STD_LOGIC_VECTOR(31 DOWNTO 0);
+			OUT_A :			OUT		STD_LOGIC_VECTOR(31 DOWNTO 0)
+		);
+	END COMPONENT;
+	
+	COMPONENT REG IS
+		PORT(
+			CLK :				IN 		STD_LOGIC;
+			RESET :			IN			STD_LOGIC;
+			RegWrite :		IN 		STD_LOGIC;
+			IN_A :			IN			STD_LOGIC_VECTOR(4 DOWNTO 0);
+			IN_B :			IN 		STD_LOGIC_VECTOR(4 DOWNTO 0);
+			IN_C :			IN 		STD_LOGIC_VECTOR(4 DOWNTO 0);
+			IN_D :			IN 		STD_LOGIC_VECTOR(31 DOWNTO 0);
+			OUT_A	:			OUT 		STD_LOGIC_VECTOR(31 DOWNTO 0);
+			OUT_B :			OUT 		STD_LOGIC_VECTOR(31 DOWNTO 0)
+		);
+	END COMPONENT;
+	
+	COMPONENT SL_1 IS
+		PORT(
+			IN_A :		 	IN  		STD_LOGIC_VECTOR (31 DOWNTO 0);
+			OUT_A  :			OUT		STD_LOGIC_VECTOR (31 DOWNTO 0)
+		);
+	END COMPONENT;
+	
+	COMPONENT SL_2 IS
+		PORT(
+			IN_A : 			IN  		STD_LOGIC_VECTOR (31 DOWNTO 0);
+			OUT_A	  :		OUT		STD_LOGIC_VECTOR (31 DOWNTO 0)
+		);
+	END COMPONENT;
+	
+	COMPONENT ULA_CTRL IS
+		PORT ( 
+			ALUOp : 			IN  		STD_LOGIC_VECTOR (1 DOWNTO 0);
+			IN_A : 			IN  		STD_LOGIC_VECTOR (5 DOWNTO 0);
+			OUT_A : 			OUT  		STD_LOGIC_VECTOR (2 DOWNTO 0)
+		);
+	END COMPONENT;
+	
+	COMPONENT ULA IS
+		PORT(
+			IN_A : 				IN  	STD_LOGIC_VECTOR (31 downto 0);				--RS
+			IN_B : 				IN  	STD_LOGIC_VECTOR (31 downto 0);				--RT
+			IN_C : 				IN 	STD_LOGIC_VECTOR (2 downto 0);
+         OUT_A :		 		OUT  	STD_LOGIC_VECTOR (31 downto 0);
+			ZERO : 				OUT  	STD_LOGIC	
+		);
+	END COMPONENT;
+	
+	--ADD_PC
+	SIGNAL S_ADD_PC_OUT_A : 		STD_LOGIC_VECTOR(31 DOWNTO 0);
+	
+	--ADD
+	SIGNAL S_ADD_OUT_A :			 	STD_LOGIC_VECTOR(31 DOWNTO 0);
+	
+	--AND_1
+	SIGNAL S_AND_1_OUT_A  :			STD_LOGIC;
+	
+	--CONCAT
+	SIGNAL S_CONCAT_OUT_A :			STD_LOGIC_VECTOR(31 DOWNTO 0);
+	
+	--CTRL
+	SIGNAL S_CTRL_RegDst :			STD_LOGIC;	
+	SIGNAL S_CTRL_Jump :				STD_LOGIC;	
+	SIGNAL S_CTRL_Branch :			STD_LOGIC;
+	SIGNAL S_CTRL_MemRead :			STD_LOGIC;
+	SIGNAL S_CTRL_MemtoReg :		STD_LOGIC;
+	SIGNAL S_CTRL_ALUOp :			STD_LOGIC_VECTOR(1 DOWNTO 0);
+	SIGNAL S_CTRL_MemWrite :		STD_LOGIC;
+	SIGNAL S_CTRL_ALUSrc :			STD_LOGIC;
+	SIGNAL S_CTRL_RegWrite :		STD_LOGIC;
+	
+	--INST
+	SIGNAL S_INST_OUT_A :			STD_LOGIC_VECTOR(31 DOWNTO 0);
+	
+	--EXTEND_SIGNAL
+	SIGNAL S_EXTEND_SIGNAL_OUT_A :STD_LOGIC_VECTOR (31 DOWNTO 0);
+	
+	--MEM
+	SIGNAL S_MEM_OUT_A :				STD_LOGIC_VECTOR(31 DOWNTO 0);
+	
+	--MX_1
+	SIGNAL S_MX_1_OUT_A :			STD_LOGIC_VECTOR(4 DOWNTO 0);
+	
+	--MX_2
+	SIGNAL S_MX_2_OUT_A :			STD_LOGIC_VECTOR(31 DOWNTO 0);
+	
+	--MX_3
+	SIGNAL S_MX_3_OUT_A :			STD_LOGIC_VECTOR(31 DOWNTO 0);
+	
+	--MX_4
+	SIGNAL S_MX_4_OUT_A :			STD_LOGIC_VECTOR(31 DOWNTO 0);
+	
+	--MX_5
+	SIGNAL S_MX_5_OUT_A :			STD_LOGIC_VECTOR(31 DOWNTO 0);
+	
+	--PC
+	SIGNAL S_PC_OUT_A :				STD_LOGIC_VECTOR(31 DOWNTO 0);
+	
+	--REG
+	SIGNAL S_REG_OUT_A :		 		STD_LOGIC_VECTOR(31 DOWNTO 0);
+	SIGNAL S_REG_OUT_B :				STD_LOGIC_VECTOR(31 DOWNTO 0);
+	
+	--SL_1
+	SIGNAL S_SL_1_OUT_A	  :		STD_LOGIC_VECTOR (31 DOWNTO 0);
+	
+	--SL_2
+	SIGNAL S_SL_2_OUT_A	  :		STD_LOGIC_VECTOR (31 DOWNTO 0);
+	
+	--ULA_CTRL
+	SIGNAL S_ULA_CTRL_OUT_A : 		STD_LOGIC_VECTOR (2 DOWNTO 0);
+	
+	--ULA
+	SIGNAL S_ULA_OUT_A :				STD_LOGIC_VECTOR (31 downto 0);
+	SIGNAL S_ULA_ZERO :  			STD_LOGIC;
+	
+	--DEMAIS SINAIS
+	SIGNAL S_GERAL_OPCode :			STD_LOGIC_VECTOR(5 DOWNTO 0);
+	SIGNAL S_GERAL_RS : 				STD_LOGIC_VECTOR(4 DOWNTO 0);	
+	SIGNAL S_GERAL_RT : 				STD_LOGIC_VECTOR(4 DOWNTO 0);	
+	SIGNAL S_GERAL_RD : 				STD_LOGIC_VECTOR(4 DOWNTO 0);	
+	SIGNAL S_GERAL_I_TYPE :			STD_LOGIC_VECTOR(15 DOWNTO 0);
+	SIGNAL S_GERAL_FUNCT :			STD_LOGIC_VECTOR(5 DOWNTO 0);
+	SIGNAL S_GERAL_JUMP :			STD_LOGIC_VECTOR(31 DOWNTO 0);
+	SIGNAL S_GERAL_PC_4 :			STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+BEGIN
+	S_GERAL_OPCode 	<= S_INST_OUT_A(31 DOWNTO 26);
+	S_GERAL_RS 			<= S_INST_OUT_A(25 DOWNTO 21);
+	S_GERAL_RT			<= S_INST_OUT_A(20 DOWNTO 16);
+	S_GERAL_RD 			<= S_INST_OUT_A(15 DOWNTO 11);
+	S_GERAL_I_TYPE 	<= S_INST_OUT_A(15 DOWNTO 0);
+	S_GERAL_FUNCT		<= S_INST_OUT_A(5 DOWNTO 0);
+	S_GERAL_JUMP		<= S_INST_OUT_A(31 DOWNTO 0);
+	S_GERAL_PC_4		<= S_ADD_PC_OUT_A(31 DOWNTO 0);
+
+	C_PC :					PC PORT MAP(CLK, RESET, S_MX_4_OUT_A, S_PC_OUT_A);
+	C_ADD_PC :				ADD_PC PORT MAP(S_PC_OUT_A, S_ADD_PC_OUT_A);
+	C_INST :					INST PORT MAP(S_PC_OUT_A, S_INST_OUT_A);
+	C_SL_1 :					SL_1 PORT MAP(S_GERAL_JUMP, S_SL_1_OUT_A);
+	C_CTRL :					CTRL PORT MAP(S_GERAL_OPCode, S_CTRL_RegDst, S_CTRL_Jump, S_CTRL_Branch, S_CTRL_MemRead, S_CTRL_MemtoReg, S_CTRL_ALUOp, S_CTRL_MemWrite, S_CTRL_ALUSrc, S_CTRL_RegWrite);
+	C_CONCAT :				CONCAT PORT MAP(S_SL_1_OUT_A, S_GERAL_PC_4, S_CONCAT_OUT_A);
+	C_MX_1 :					MX_1 PORT MAP(S_CTRL_RegDst, S_GERAL_RT, S_GERAL_RD, S_MX_1_OUT_A);
+	C_SL_2 :					SL_2 PORT MAP(S_EXTEND_SIGNAL_OUT_A, S_SL_2_OUT_A);
+	C_REG :					REG PORT MAP(CLK, RESET, S_CTRL_RegWrite, S_GERAL_RS, S_GERAL_RT, S_MX_1_OUT_A, S_MX_5_OUT_A, S_REG_OUT_A, S_REG_OUT_B);
+	C_EXTEND_SIGNAL :		EXTEND_SIGNAL PORT MAP(S_GERAL_I_TYPE, S_EXTEND_SIGNAL_OUT_A);
+	C_ADD :					ADD PORT MAP(S_ADD_PC_OUT_A, S_SL_2_OUT_A, S_ADD_OUT_A);
+	C_ULA :					ULA PORT MAP(S_REG_OUT_A, S_MX_2_OUT_A, S_ULA_CTRL_OUT_A, S_ULA_OUT_A, S_ULA_ZERO);
+	C_MX_2 :					MX_2 PORT MAP(S_CTRL_ALUSrc, S_REG_OUT_B, S_EXTEND_SIGNAL_OUT_A, S_MX_2_OUT_A);
+	C_ULA_CTRL :			ULA_CTRL PORT MAP(S_CTRL_ALUOp, S_GERAL_FUNCT, S_ULA_CTRL_OUT_A);
+	C_MX_3 :					MX_3 PORT MAP(S_ADD_PC_OUT_A, S_ADD_OUT_A, S_AND_1_OUT_A, S_MX_3_OUT_A);
+	C_AND_1 :				AND_1 PORT MAP(S_CTRL_Branch, S_ULA_ZERO, S_AND_1_OUT_A);
+	C_MEM :					MEM PORT MAP(CLK, RESET, S_CTRL_MemWrite, S_CTRL_MemRead, S_ULA_OUT_A, S_REG_OUT_B, S_MEM_OUT_A);
+	C_MX_4 :					MX_4 PORT MAP(S_CTRL_Jump, S_CONCAT_OUT_A, S_MX_3_OUT_A, S_MX_4_OUT_A);
+	C_MX_5 :					MX_5 PORT MAP(S_CTRL_MemtoReg, S_MEM_OUT_A, S_ULA_OUT_A, S_MX_5_OUT_A);
+	
+END ARC_MAIN_PROCESSOR;
+

MEM.vhd

+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+--  Complete implementation of Patterson and Hennessy single cycle MIPS processor
+--  Copyright (C) 2015  Darci Luiz Tomasi Junior
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, version 3.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--  Engineer: 	Darci Luiz Tomasi Junior
+--	 E-mail: 	dltj007@gmail.com
+--  Date :    	08/07/2015 - 20:07
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+ENTITY MEM IS
+	PORT(
+		CLK :						IN STD_LOGIC;
+		RESET :					IN STD_LOGIC;
+		MemWrite :				IN STD_LOGIC;
+		MemRead :				IN STD_LOGIC;
+		IN_A :					IN STD_LOGIC_VECTOR(31 DOWNTO 0); 
+		IN_B :					IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		OUT_A :					OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END MEM;
+
+ARCHITECTURE ARC_MEM OF MEM IS
+	TYPE 		RAM_TYPE IS ARRAY(0 TO 255) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
+	SIGNAL	RAM: RAM_TYPE;
+	SIGNAL 	ADRESS :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+	
+BEGIN
+	PROCESS(CLK)
+		BEGIN
+			IF RESET = '1' THEN
+			
+				RAM <= ((OTHERS => (OTHERS=>'0')));
+				
+			ELSIF CLK'EVENT AND CLK = '1' THEN
+				IF MemWrite = '1' THEN
+					
+					--MIPS ARMAZEMA EM BYTES OU SEJA 4 EM 4
+					--POR ISSO PEGA DE 31 A 2, POIS DEVIDO A POSIO DE ORDENAO DO ARRAY SER DE 1 EM 1...
+					--...SE DESLOCA DOIS PARA DIREITA EX:
+					--						SW $S0, 4($T0)					1010110100101000 0000000000000100
+					--												[31-2]
+					--															1010110100101000 00000000000001  = 1
+					--						SW $S0, 8($T0) 				1010110100101000 0000000000001000
+					--												[31-2]
+					--															1010110100101000 00000000000010  = 2
+					RAM(TO_INTEGER (UNSIGNED(ADRESS(31 DOWNTO 2)))) <= IN_B;
+				END IF;
+			END IF;
+	END PROCESS;
+	
+	OUT_A	<=	RAM(TO_INTEGER(UNSIGNED(ADRESS(31 DOWNTO 2)))) WHEN MemRead ='1';
+	
+	--PARA UTILIZAR COM O MARS
+	ADRESS <= STD_LOGIC_VECTOR(UNSIGNED(IN_A) - X"FFFF0000");
+
+END ARC_MEM;
+

MX_1.vhd

+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+--  Complete implementation of Patterson and Hennessy single cycle MIPS processor
+--  Copyright (C) 2015  Darci Luiz Tomasi Junior
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, version 3.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--  Engineer: 	Darci Luiz Tomasi Junior
+--	 E-mail: 	dltj007@gmail.com
+--  Date :    	02/07/2015 - 21:48
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY MX_1 IS
+	PORT(
+		RegDst :					IN				STD_LOGIC;	
+		IN_A :					IN 			STD_LOGIC_VECTOR(4 DOWNTO 0);
+		IN_B :					IN				STD_LOGIC_VECTOR(4 DOWNTO 0);
+		OUT_A :					OUT 			STD_LOGIC_VECTOR(4 DOWNTO 0)
+	);
+END MX_1;
+
+ARCHITECTURE ARC_MX_1 OF MX_1 IS
+
+BEGIN
+	OUT_A <= IN_A WHEN RegDst = '0' ELSE IN_B;
+
+END ARC_MX_1;
+

MX_2.vhd

+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+--  Complete implementation of Patterson and Hennessy single cycle MIPS processor
+--  Copyright (C) 2015  Darci Luiz Tomasi Junior
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, version 3.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--  Engineer: 	Darci Luiz Tomasi Junior
+--	 E-mail: 	dltj007@gmail.com
+--  Date :    	06/07/2015 - 22:06
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY MX_2 IS
+	PORT(
+		AluSrc :					IN				STD_LOGIC;
+		IN_A :					IN 			STD_LOGIC_VECTOR(31 DOWNTO 0);
+		IN_B : 					IN  			STD_LOGIC_VECTOR(31 DOWNTO 0);
+		OUT_A :					OUT			STD_LOGIC_VECTOR(31 DOWNTO 0)			
+	);
+END MX_2;
+
+ARCHITECTURE ARC_MX_2 OF MX_2 IS
+
+BEGIN
+	OUT_A <= IN_A WHEN AluSrc ='0' ELSE IN_B;
+
+END ARC_MX_2;
+

MX_3.vhd

+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+--  Complete implementation of Patterson and Hennessy single cycle MIPS processor
+--  Copyright (C) 2015  Darci Luiz Tomasi Junior
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, version 3.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--  Engineer: 	Darci Luiz Tomasi Junior
+--	 E-mail: 	dltj007@gmail.com
+--  Date :    	08/07/2015 - 19:11
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY MX_3 IS
+	PORT(
+		IN_A :					IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		IN_B :					IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		IN_C :					IN STD_LOGIC;
+		OUT_A :					OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END MX_3;
+
+ARCHITECTURE ARC_MX_3 OF MX_3 IS
+
+BEGIN
+	OUT_A <= IN_A  WHEN IN_C = '0' ELSE IN_B;
+
+END ARC_MX_3;
+

MX_4.vhd

+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+--  Complete implementation of Patterson and Hennessy single cycle MIPS processor
+--  Copyright (C) 2015  Darci Luiz Tomasi Junior
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, version 3.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--  Engineer: 	Darci Luiz Tomasi Junior
+--	 E-mail: 	dltj007@gmail.com
+--  Date :    	08/07/2015 - 19:11
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY MX_4 IS
+	PORT(
+		Jump :					IN STD_LOGIC;
+		IN_A :					IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		IN_B :					IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		OUT_A :					OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END MX_4;
+
+ARCHITECTURE ARC_MX_4 OF MX_4 IS
+
+BEGIN
+	OUT_A <= IN_B  WHEN Jump = '0' ELSE IN_A;
+
+END ARC_MX_4;
+

MX_5.vhd

+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+--  Complete implementation of Patterson and Hennessy single cycle MIPS processor
+--  Copyright (C) 2015  Darci Luiz Tomasi Junior
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, version 3.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--  Engineer: 	Darci Luiz Tomasi Junior
+--	 E-mail: 	dltj007@gmail.com
+--  Date :    	08/07/2015 - 19:11
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY MX_5 IS
+	PORT(
+		MemtoReg :				IN STD_LOGIC;
+		IN_A :					IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		IN_B :					IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		OUT_A :					OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END MX_5;
+ARCHITECTURE ARC_MX_5 OF MX_5 IS
+
+BEGIN
+	OUT_A <= IN_B  WHEN MemtoReg = '0' ELSE IN_A;
+
+END ARC_MX_5;
+

PC.vhd

+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+--  Complete implementation of Patterson and Hennessy single cycle MIPS processor
+--  Copyright (C) 2015  Darci Luiz Tomasi Junior
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, version 3.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--  Engineer: 	Darci Luiz Tomasi Junior
+--	 E-mail: 	dltj007@gmail.com
+--  Date :    	01/07/2015 - 19:53 
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++  
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY PC IS
+	PORT(
+		CLK :							IN		STD_LOGIC;
+		RESET :						IN		STD_LOGIC;
+		IN_A :						IN 	STD_LOGIC_VECTOR(31 DOWNTO 0);
+		OUT_A :						OUT	STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END PC;
+
+ARCHITECTURE ARC_PC OF PC IS
+	
+BEGIN
+	PROCESS(CLK, RESET)
+	BEGIN
+		IF RESET = '1' THEN
+			OUT_A <= X"00400000";								--Para utilizar com o MARS
+		ELSIF	CLK'EVENT AND CLK = '1' THEN
+			OUT_A <= IN_A;
+		END IF;
+	END PROCESS;
+END ARC_PC;
+

REG.vhd

+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+--  Complete implementation of Patterson and Hennessy single cycle MIPS processor
+--  Copyright (C) 2015  Darci Luiz Tomasi Junior
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, version 3.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--  Engineer: 	Darci Luiz Tomasi Junior
+--	 E-mail: 	dltj007@gmail.com
+--  Date :    	29/06/2015 - 20:31
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+ENTITY REG IS
+	PORT(
+		CLK :					IN STD_LOGIC;
+		RESET :				IN	STD_LOGIC;
+		RegWrite :			IN STD_LOGIC;
+		IN_A :				IN	STD_LOGIC_VECTOR(4 DOWNTO 0);
+		IN_B :				IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		IN_C :				IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		IN_D :				IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		OUT_A	:				OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		OUT_B :				OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END REG;
+
+ARCHITECTURE ARC_REG OF REG IS
+	
+	TYPE 		STD_REG IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
+	SIGNAL	REG_1: STD_REG;
+	SIGNAL	REG_2: STD_REG;
+	
+BEGIN	
+	--REALIZA A LEITURA NO ENDEREO SELECIONADO
+	OUT_A		<=		REG_1(TO_INTEGER(UNSIGNED(IN_A)));
+	OUT_B		<=		REG_2(TO_INTEGER(UNSIGNED(IN_B)));
+	
+	--PROCESSO DE LEITURA
+	PROCESS(CLK, RESET)
+		BEGIN
+			IF RESET = '1' THEN
+				REG_1(0) <= (OTHERS => '0');
+				REG_2(0) <= (OTHERS => '0');
+				
+				--t0
+				REG_1(8) <= (0 => '1', OTHERS => '0');					--NO TEMOS A FUNO ADDI, ENTO
+				REG_2(8) <= (0 => '1', OTHERS => '0');					--TEM QUE SER NA FORA BRUTA
+				
+				--t1
+				REG_1(9) <= (0 => '1', 1 => '1', OTHERS => '0');
+				REG_2(9) <= (0 => '1', 1 => '1', OTHERS => '0');
+				
+				--s1
+				REG_1(17) <= X"FFFF0000";
+				REG_2(17) <= X"FFFF0000";
+			
+			ELSIF CLK'EVENT AND CLK = '0' AND RegWrite = '1' THEN
+				REG_1(TO_INTEGER(UNSIGNED(IN_C))) <= IN_D;
+				REG_2(TO_INTEGER(UNSIGNED(IN_C))) <= IN_D;
+			
+			END IF;
+	END PROCESS;
+
+END ARC_REG;
+
+

SL_1.vhd

+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+--  Complete implementation of Patterson and Hennessy single cycle MIPS processor
+--  Copyright (C) 2015  Darci Luiz Tomasi Junior
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, version 3.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--  Engineer: 	Darci Luiz Tomasi Junior
+--	 E-mail: 	dltj007@gmail.com
+--  Date :    	09/07/2015 - 22:07
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+
+ENTITY SL_1 IS
+	PORT(
+		IN_A :		 		IN  	STD_LOGIC_VECTOR (31 DOWNTO 0);
+		OUT_A  :				OUT	STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END SL_1;
+
+ARCHITECTURE ARC_SL_1 OF SL_1 IS
+
+BEGIN
+	OUT_A	<= STD_LOGIC_VECTOR(UNSIGNED(IN_A) SLL 2);
+
+END ARC_SL_1;
+

SL_2.vhd

+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+--  Complete implementation of Patterson and Hennessy single cycle MIPS processor
+--  Copyright (C) 2015  Darci Luiz Tomasi Junior
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, version 3.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--  Engineer: 	Darci Luiz Tomasi Junior
+--	 E-mail: 	dltj007@gmail.com
+--  Date :    	24/06/2015 - 21:46
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+ENTITY SL_2 IS
+	PORT(
+		IN_A : 			IN  	STD_LOGIC_VECTOR (31 DOWNTO 0);
+		OUT_A	  :		OUT	STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END SL_2;
+
+ARCHITECTURE ARC_SL_2 OF SL_2 IS
+
+BEGIN
+
+	OUT_A	<= STD_LOGIC_VECTOR(UNSIGNED(IN_A) SLL 2);
+
+END ARC_SL_2;
+

TB_MAIN_PROCESSOR.vhd

+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   17:35:44 08/06/2015
+-- Design Name:   
+-- Module Name:   E:/Programas_FPGA/SYNGLE_CYCLE_V3/TB_MAIN_PROCESSOR.vhd
+-- Project Name:  SYNGLE_CYCLE_V3
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: MAIN_PROCESSOR
+-- 
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ 
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+ 
+ENTITY TB_MAIN_PROCESSOR IS
+END TB_MAIN_PROCESSOR;
+ 
+ARCHITECTURE behavior OF TB_MAIN_PROCESSOR IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT MAIN_PROCESSOR
+    PORT(
+         CLK : IN  std_logic;
+         RESET : IN  std_logic
+        );
+    END COMPONENT;
+    
+
+   --Inputs
+   signal CLK : std_logic := '0';
+   signal RESET : std_logic := '0';
+
+   -- Clock period definitions
+   constant CLK_period : time := 10 ns;
+ 
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: MAIN_PROCESSOR PORT MAP (
+          CLK => CLK,
+          RESET => RESET
+        );
+
+   -- Clock process definitions
+   CLK_process :process
+   begin
+		CLK <= '0';
+		wait for CLK_period/2;
+		CLK <= '1';
+		wait for CLK_period/2;
+   end process;
+ 
+
+   -- Stimulus process
+   stim_proc: process
+   begin		
+		RESET <= '1';
+      wait for 10 ns;
+		RESET <= '0';
+		WAIT;
+   end process;
+
+END;

ULA.vhd

+-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+--  Complete implementation of Patterson and Hennessy single cycle MIPS processor
+--  Copyright (C) 2015  Darci Luiz Tomasi Junior
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, version 3.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+--  Engineer: 	Darci Luiz Tomasi Junior
+--	 E-mail: 	dltj007@gmail.com
+--  Date :    	18/06/2015 - 20:12
+-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_ARITH.ALL;
+USE IEEE.STD_LOGIC_SIGNED.ALL;
+
+ENTITY ULA IS
+	PORT(
+			IN_A : 				IN  	STD_LOGIC_VECTOR (31 downto 0);				--RS
+			IN_B : 				IN  	STD_LOGIC_VECTOR (31 downto 0);				--RT
+			IN_C : 				IN 	STD_LOGIC_VECTOR (2 downto 0);
+         OUT_A :		 		OUT  	STD_LOGIC_VECTOR (31 downto 0);
+			ZERO : 				OUT  	STD_LOGIC	
+	);
+	
+END ULA;
+
+ARCHITECTURE ARC_ULA OF ULA IS
+	SIGNAL DATA_RS :				STD_LOGIC_VECTOR(31 DOWNTO 0);
+	SIGNAL DATA_RT :				STD_LOGIC_VECTOR(31 DOWNTO 0);
+	SIGNAL ULA_CTRL :				STD_LOGIC_VECTOR (2 downto 0);
+	SIGNAL DATA_ALU_RESULT :	STD_LOGIC_VECTOR(31 DOWNTO 0);
+	
+BEGIN
+
+	DATA_RS <= IN_A;
+	DATA_RT <= IN_B;
+	ULA_CTRL <= IN_C;
+				  
+	ZERO <= '1' WHEN (DATA_ALU_RESULT = X"00000000") else '0';
+	
+	--PARA A INSTRUO SLT, PEGA O SINAL DO RESULTADO DA SUBTRAO E ADICIONA AO FINAL DO VETOR
+	OUT_A <= (X"0000000" & "000" & DATA_ALU_RESULT(31)) WHEN ULA_CTRL = "111" ELSE
+						DATA_ALU_RESULT;
+						
+	PROCESS(ULA_CTRL, DATA_RS, DATA_RT)
+	BEGIN
+		CASE ULA_CTRL IS
+			WHEN "000" => DATA_ALU_RESULT <= DATA_RS AND DATA_RT;			--AND
+			WHEN "001" => DATA_ALU_RESULT <= DATA_RS OR DATA_RT;			--OR
+			WHEN "010" => DATA_ALU_RESULT <= DATA_RS + DATA_RT;				--ADD
+			WHEN "110" => DATA_ALU_RESULT <= DATA_RS - DATA_RT;				--SUB
+			WHEN "111" => DATA_ALU_RESULT <= DATA_RS - DATA_RT;				--SLT			
+			WHEN OTHERS => DATA_ALU_RESULT <= X"00000000";
+		END CASE;
+	END PROCESS;
+
+END ARC_ULA;
+
+