add_pc.vhd

-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  complete implementation of patterson and hennessy single cycle mips processor
--  copyright (c) 2015  darci luiz tomasi junior
--
--  this program is free software: you can redistribute it and/or modify
--  it under the terms of the gnu general public license as published by
--  the free software foundation, version 3.
--
--  this program is distributed in the hope that it will be useful,
--  but without any warranty; without even the implied warranty of
--  merchantability or fitness for a particular purpose.  see the
--  gnu general public license for more details.
--
--  you should have received a copy of the gnu general public license
--  along with this program.  if not, see <http://www.gnu.org/licenses/>.
--
--  engineer: 	darci luiz tomasi junior
--	 e-mail: 	dltj007@gmail.com
--  date :    	01/07/2015 - 20:00
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity add_pc is
	port(
		in_a :		in 		std_logic_vector(31 downto 0);
		out_a :		out		std_logic_vector(31 downto 0)
	);
end add_pc;

architecture arc_add_pc of add_pc is
	constant pc_increment :			unsigned(31 downto 0):= x"00000004";

begin
	out_a <= std_logic_vector(unsigned(in_a) + pc_increment);

end arc_add_pc;