ula.vhd

-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  complete implementation of patterson and hennessy single cycle mips processor
--  copyright (c) 2015  darci luiz tomasi junior
--
--  this program is free software: you can redistribute it and/or modify
--  it under the terms of the gnu general public license as published by
--  the free software foundation, version 3.
--
--  this program is distributed in the hope that it will be useful,
--  but without any warranty; without even the implied warranty of
--  merchantability or fitness for a particular purpose.  see the
--  gnu general public license for more details.
--
--  you should have received a copy of the gnu general public license
--  along with this program.  if not, see <http://www.gnu.org/licenses/>.
--
--  engineer: 	darci luiz tomasi junior
--	 e-mail: 	dltj007@gmail.com
--  date :    	18/06/2015 - 20:12
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity ula is
	port(
			in_a : 				in  	std_logic_vector (31 downto 0);				--rs
			in_b : 				in  	std_logic_vector (31 downto 0);				--rt
			in_c : 				in 	std_logic_vector (2 downto 0);
         out_a :		 		out  	std_logic_vector (31 downto 0);
			zero : 				out  	std_logic	
	);
	
end ula;

architecture arc_ula of ula is
	signal data_rs :				std_logic_vector(31 downto 0);
	signal data_rt :				std_logic_vector(31 downto 0);
	signal ula_ctrl :				std_logic_vector (2 downto 0);
	signal data_alu_result :	std_logic_vector(31 downto 0);
	
begin

	data_rs <= in_a;
	data_rt <= in_b;
	ula_ctrl <= in_c;
				  
	zero <= '1' when (data_alu_result = x"00000000") else '0';
	
	--para a instruo slt, pega o sinal do resultado da subtrao e adiciona ao final do vetor
	out_a <= (x"0000000" & "000" & data_alu_result(31)) when ula_ctrl = "111" else
						data_alu_result;
						
	process(ula_ctrl, data_rs, data_rt)
	begin
		case ula_ctrl is
			when "000" => data_alu_result <= data_rs and data_rt;			--and
			when "001" => data_alu_result <= data_rs or data_rt;			--or
			when "010" => data_alu_result <= data_rs + data_rt;				--add
			when "110" => data_alu_result <= data_rs - data_rt;				--sub
			when "111" => data_alu_result <= data_rs - data_rt;				--slt			
			when others => data_alu_result <= x"00000000";
		end case;
	end process;

end arc_ula;