reg64.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity reg64 is
    port(
        clk:    in std_logic;
        rst:  in std_logic;
        inp:    in std_logic_vector(63 downto 0);
        outp:   out std_logic_vector(63 downto 0)
    );
end reg64;

architecture arc_reg64 of reg64 is
begin
    process(clk, rst)
        begin
            if rst =  '1' then
                outp <= x"0040000000000000";
            elsif clk'event and clk = '1' then
                outp <= inp;
            end if;
    end process;
end architecture arc_reg64;