Add comparator architecture

compare.vhd

+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity compare is
+    port(
+        inp_a:  in std_logic_vector(31 downto 0);
+        inp_b:  in std_logic_vector(31 downto 0);
+        outp:   out std_logic
+    );
+end compare;
+
+architecture arc_compare of compare is
+begin
+    process(inp_a, inp_b)
+    begin
+        if inp_a = inp_b then
+            outp <= '1';
+        else
+            outp <= '0';
+        end if;
+    end process;
+end architecture arc_compare;

main_cttrl.vhd

@@ -62,6 +62,14 @@ architecture arc_main_processor of main_processor is
 		);
 	end component;
 
+    component compare is
+        port(
+            inp_a:  in std_logic_vector(31 downto 0);
+            inp_b:  in std_logic_vector(31 downto 0);
+            outp:   out std_logic
+        );
+    end component;
+	
 	component ctrl is
 		port(
 			opcode : 		in			std_logic_vector(5 downto 0);
@@ -301,7 +309,8 @@ begin
 	c_reg :					reg port map(clk, reset, s_ctrl_regwrite, s_geral_rs, s_geral_rt, s_mx_1_out_a, s_mx_5_out_a, s_reg_out_a, s_reg_out_b);
 	c_extend_signal :		extend_signal port map(s_geral_i_type, s_extend_signal_out_a);
 	c_add :					add port map(s_add_pc_out_a, s_sl_2_out_a, s_add_out_a);
-	c_ula :					ula port map(s_reg_out_a, s_mx_2_out_a, s_ula_ctrl_out_a, s_ula_out_a, s_ula_zero);
+    c_cmp:                  compare port map (s_reg_out_a, s_reg_out_b, s_ula_zero);
+	c_ula :					ula port map(s_reg_out_a, s_mx_2_out_a, s_ula_ctrl_out_a, s_ula_out_a, open);
 	c_mx_2 :					mx_2 port map(s_ctrl_alusrc, s_reg_out_b, s_extend_signal_out_a, s_mx_2_out_a);
 	c_ula_ctrl :			ula_ctrl port map(s_ctrl_aluop, s_geral_funct, s_ula_ctrl_out_a);
 	c_mx_3 :					mx_3 port map(s_add_pc_out_a, s_add_out_a, s_and_1_out_a, s_mx_3_out_a);