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Commit 6cc54433 authored by Strozzi's avatar Strozzi
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Add primal Hazard detection unity

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hazard.vhd 0 → 100644
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View file @ 6cc54433
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity hazard is
port(
reset : in std_logic;
rs_id : in std_logic_vector(4 downto 0);
rt_id : in std_logic_vector(4 downto 0);
rs_ex : in std_logic_vector(4 downto 0);
rt_ex : in std_logic_vector(4 downto 0);
flush : out std_logic
);
end hazard;
architecture arc_hazard of hazard is
begin
process(reset, rs_id, rt_id, rs_ex, rt_ex)
begin
if reset = '1' then
flush <= '0';
elsif (rs_id = rs_ex) or (rt_id = rt_ex) then
flush <= '1';
else
flush <= '0';
end if;
end process;
end architecture arc_hazard;
main_cttrl.vhd
+ 91
− 61
View file @ 6cc54433
...@@ -99,6 +99,17 @@ architecture arc_main_processor of main_processor is ...@@ -99,6 +99,17 @@ architecture arc_main_processor of main_processor is
); );
end component; end component;
component hazard is
port(
reset : in std_logic;
rs_id : in std_logic_vector(4 downto 0);
rt_id : in std_logic_vector(4 downto 0);
rs_ex : in std_logic_vector(4 downto 0);
rt_ex : in std_logic_vector(4 downto 0);
flush : out std_logic
);
end component;
component mem is component mem is
port( port(
clk : in std_logic; clk : in std_logic;
...@@ -255,6 +266,9 @@ architecture arc_main_processor of main_processor is ...@@ -255,6 +266,9 @@ architecture arc_main_processor of main_processor is
-- cmp -- cmp
signal s_cmp_zero : std_logic; signal s_cmp_zero : std_logic;
-- hazard detection
signal flush : std_logic;
--inst --inst
signal s_inst_out_a : std_logic_vector(31 downto 0); signal s_inst_out_a : std_logic_vector(31 downto 0);
...@@ -325,6 +339,7 @@ begin ...@@ -325,6 +339,7 @@ begin
c_inst : inst port map(s_pc_out_a, s_inst_out_a); c_inst : inst port map(s_pc_out_a, s_inst_out_a);
-- IF/ID -- IF/ID
-- |63 32 | 31 0|
s_if_id_in <= s_add_pc_out_a(31 downto 0) & s_inst_out_a(31 downto 0); s_if_id_in <= s_add_pc_out_a(31 downto 0) & s_inst_out_a(31 downto 0);
c_if_id : reg64 port map(clk, reset, s_if_id_in, s_if_id_out); c_if_id : reg64 port map(clk, reset, s_if_id_in, s_if_id_out);
-- s_add_pc_out é a parte mais significativa do registrador -- s_add_pc_out é a parte mais significativa do registrador
...@@ -338,43 +353,58 @@ begin ...@@ -338,43 +353,58 @@ begin
s_geral_funct <= s_if_id_out(5 downto 0); s_geral_funct <= s_if_id_out(5 downto 0);
s_geral_jump <= s_if_id_out(31 downto 0); s_geral_jump <= s_if_id_out(31 downto 0);
c_hazard : hazard port map(reset, s_geral_rs, s_geral_rt, s_id_ex_out(17 downto 13),
s_id_ex_out(12 downto 8), flush);
c_sl_1 : sl_1 port map(s_geral_jump, s_sl_1_out_a); c_sl_1 : sl_1 port map(s_geral_jump, s_sl_1_out_a);
c_ctrl : ctrl port map(s_geral_opcode, s_ctrl_regdst, s_ctrl_jump, s_ctrl_branch, s_ctrl_memread, s_ctrl_memtoreg, s_ctrl_aluop, c_ctrl : ctrl port map(s_geral_opcode, s_ctrl_regdst, s_ctrl_jump, s_ctrl_branch,
s_ctrl_memwrite, s_ctrl_alusrc, s_ctrl_regwrite); s_ctrl_memread, s_ctrl_memtoreg, s_ctrl_aluop, s_ctrl_memwrite,
s_ctrl_alusrc, s_ctrl_regwrite);
c_concat : concat port map(s_sl_1_out_a, s_geral_pc_4, s_concat_out_a); c_concat : concat port map(s_sl_1_out_a, s_geral_pc_4, s_concat_out_a);
c_sl_2 : sl_2 port map(s_extend_signal_out_a, s_sl_2_out_a); c_sl_2 : sl_2 port map(s_extend_signal_out_a, s_sl_2_out_a);
c_reg : reg port map(clk, reset, s_mm_wb_out(70), s_geral_rs, s_geral_rt, s_mm_wb_out(4 downto 0), s_mx_5_out_a, s_reg_out_a, c_reg : reg port map(clk, reset, s_mm_wb_out(70), s_geral_rs, s_geral_rt,
s_reg_out_b); s_mm_wb_out(4 downto 0), s_mx_5_out_a, s_reg_out_a, s_reg_out_b);
c_extend_signal : extend_signal port map(s_geral_i_type, s_extend_signal_out_a); c_extend_signal : extend_signal port map(s_geral_i_type, s_extend_signal_out_a);
c_add : add port map(s_geral_pc_4, s_sl_2_out_a, s_add_out_a); c_add : add port map(s_geral_pc_4, s_sl_2_out_a, s_add_out_a);
c_cmp: compare port map (s_reg_out_a, s_reg_out_b, s_cmp_zero); c_cmp: compare port map (s_reg_out_a, s_reg_out_b, s_cmp_zero);
c_mx_2 : mx_2 port map(s_ctrl_alusrc, s_reg_out_b, s_extend_signal_out_a, s_mx_2_out_a); c_mx_2 : mx_2 port map(s_ctrl_alusrc, s_reg_out_b, s_extend_signal_out_a,
s_mx_2_out_a);
c_ula_ctrl : ula_ctrl port map(s_ctrl_aluop, s_geral_funct, s_ula_ctrl_out_a); c_ula_ctrl : ula_ctrl port map(s_ctrl_aluop, s_geral_funct, s_ula_ctrl_out_a);
c_mx_3 : mx_3 port map(s_geral_pc_4, s_add_out_a, s_and_1_out_a, s_mx_3_out_a); c_mx_3 : mx_3 port map(s_geral_pc_4, s_add_out_a, s_and_1_out_a, s_mx_3_out_a);
c_and_1 : and_1 port map(s_ctrl_branch, s_cmp_zero, s_and_1_out_a); c_and_1 : and_1 port map(s_ctrl_branch, s_cmp_zero, s_and_1_out_a);
c_mx_4 : mx_4 port map(s_ctrl_jump, s_concat_out_a, s_mx_3_out_a, s_mx_4_out_a); c_mx_4 : mx_4 port map(s_ctrl_jump, s_concat_out_a, s_mx_3_out_a, s_mx_4_out_a);
-- ID/EX 41 zeros to put the input in the least sign & control & reg_out_a & reg_out_b & inp_alu_b & rs & rt & rd & alu_control -- ID/EX 41 zeros to put the input in the least sign & control & reg_out_a & reg_out_b &
-- |127 119 | 118 | 117 | 116 | 115 | 114 | 113 82 -- inp_alu_b & rs & rt & rd & alu_control
s_id_ex_in <= x"00" & '0' & s_ctrl_regwrite & s_ctrl_memtoreg & s_ctrl_memwrite & s_ctrl_memread & s_ctrl_regdst & s_reg_out_a -- |127 119 | 118 | 117 | 116 | 115
-- | 81 50 | 49 18 | 17 13 | 12 8 | 7 3 | 2 0| s_id_ex_in <= x"00" & '0' & s_ctrl_regwrite & s_ctrl_memtoreg & s_ctrl_memwrite & s_ctrl_memread
& s_reg_out_b & s_mx_2_out_a & s_geral_rs & s_geral_rt & s_geral_rd & s_ula_ctrl_out_a; -- | 114 | 113 82 | 81 50 | 49 18 | 17 13
& s_ctrl_regdst & s_reg_out_a & s_reg_out_b & s_mx_2_out_a & s_geral_rs
-- | 12 8 | 7 3 | 2 0|
& s_geral_rt & s_geral_rd & s_ula_ctrl_out_a;
c_id_ex : reg128 port map(clk, reset, s_id_ex_in, s_id_ex_out); c_id_ex : reg128 port map(clk, reset, s_id_ex_in, s_id_ex_out);
c_ula : ula port map(s_id_ex_out(113 downto 82), s_id_ex_out(49 downto 18), s_id_ex_out(2 downto 0), s_ula_out_a, open); c_ula : ula port map(s_id_ex_out(113 downto 82), s_id_ex_out(49 downto 18),
c_mx_1 : mx_1 port map(s_id_ex_out(114), s_id_ex_out(12 downto 8), s_id_ex_out(7 downto 3), s_mx_1_out_a); s_id_ex_out(2 downto 0), s_ula_out_a, open);
c_mx_1 : mx_1 port map(s_id_ex_out(114), s_id_ex_out(12 downto 8), s_id_ex_out(7 downto 3),
s_mx_1_out_a);
-- EX/MM 56 zeros & control & alu_out & inp_alu_b & reg_dst -- EX/MM 56 zeros & control & alu_out & inp_alu_b & reg_dst
-- |127 73 | 72 69 | 68 37 | 36 5 | 4 0| -- |127 73 | 72 69 | 68 37 | 36 5
s_ex_mm_in <= x"0000000000000"& "000" & s_id_ex_out(118 downto 115) & s_ula_out_a & s_id_ex_out(81 downto 50) & s_mx_1_out_a; s_ex_mm_in <= x"0000000000000"& "000" & s_id_ex_out(118 downto 115) & s_ula_out_a & s_id_ex_out(81 downto 50)
-- | 4 0|
& s_mx_1_out_a;
c_ex_mm : reg128 port map(clk, reset, s_ex_mm_in, s_ex_mm_out); c_ex_mm : reg128 port map(clk, reset, s_ex_mm_in, s_ex_mm_out);
c_mem : mem port map(clk, reset, s_ex_mm_out(70), s_ex_mm_out(69), s_ex_mm_out(68 downto 37), s_ex_mm_out(36 downto 5), c_mem : mem port map(clk, reset, s_ex_mm_out(70), s_ex_mm_out(69), s_ex_mm_out(68 downto 37),
s_mem_out_a); s_ex_mm_out(36 downto 5), s_mem_out_a);
-- MM/WB -- MM/WB
-- |127 71 | 70 69 | 68 37 | 36 5 | 4 0| -- |127 71 | 70 69 | 68 37 | 36 5
s_mm_wb_in <= x"00000000000000" & '0' & s_ex_mm_out(72 downto 71) & s_mem_out_a & s_ex_mm_out(68 downto 37) & s_ex_mm_out(4 downto 0); s_mm_wb_in <= x"00000000000000" & '0' & s_ex_mm_out(72 downto 71) & s_mem_out_a & s_ex_mm_out(68 downto 37)
-- | 4 0|
& s_ex_mm_out(4 downto 0);
c_mm_wb : reg128 port map(clk, reset, s_mm_wb_in, s_mm_wb_out); c_mm_wb : reg128 port map(clk, reset, s_mm_wb_in, s_mm_wb_out);
c_mx_5 : mx_5 port map(s_mm_wb_out(69), s_mm_wb_out(68 downto 37), s_mm_wb_out(36 downto 5), s_mx_5_out_a); c_mx_5 : mx_5 port map(s_mm_wb_out(69), s_mm_wb_out(68 downto 37), s_mm_wb_out(36 downto 5), s_mx_5_out_a);
......
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