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Commit 7336fac0 authored by Strozzi's avatar Strozzi
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fix undefined registers

parent d902318c
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Makefile
+ 1
− 1
View file @ 7336fac0
all:
ghdl -a --ieee=synopsys -fexplicit *.vhd
ghdl -e --ieee=synopsys -fexplicit tb_main_processor
./tb_main_processor --stop-time=300ns --vcd=tb.vcd
./tb_main_processor --stop-time=600ns --vcd=tb.vcd
gtk: all
gtkwave tb.vcd
......
inst.vhd
+ 37
− 16
View file @ 7336fac0
......@@ -33,22 +33,43 @@ end inst;
architecture arc_inst of inst is
--deve ser 0 to 255 o array para facilitar a leitura do programa em ordem crescente
type memory is array (0 to 255) of std_logic_vector(31 downto 0);
signal program : memory := ( x"01095024", x"01485025" ,x"014a5020",x"01285022",x"0149582a",x"00004820",x"11490002",x"01284820",x"08100006",x"ae2a0000",x"8e300000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000" );
signal program : memory := ( x"01095024", x"01485025" ,x"014a5020",x"01285022",
x"0149582a",x"00004820",x"11490002",x"01284820",x"08100006",x"ae2a0000",x"8e300000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",
x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000");
begin
--o fator - x"00400000" devido ao incio das instrues no software mars
out_a <= program(to_integer((unsigned(in_a) - x"00400000") srl 2));
......
main_cttrl.vhd
+ 47
− 47
View file @ 7336fac0
reg.vhd
+ 57
− 4
View file @ 7336fac0
......@@ -53,18 +53,71 @@ begin
if reset = '1' then
reg_1(0) <= (others => '0');
reg_2(0) <= (others => '0');
reg_1(1) <= (others => '0');
reg_2(1) <= (others => '0');
reg_1(2) <= (others => '0');
reg_2(2) <= (others => '0');
reg_1(3) <= (others => '0');
reg_2(3) <= (others => '0');
reg_1(4) <= (others => '0');
reg_2(4) <= (others => '0');
reg_1(5) <= (others => '0');
reg_2(5) <= (others => '0');
reg_1(6) <= (others => '0');
reg_2(6) <= (others => '0');
reg_1(7) <= (others => '0');
reg_2(7) <= (others => '0');
--t0
reg_1(8) <= (0 => '1', others => '0'); --no temos a funo addi, ento
reg_2(8) <= (0 => '1', others => '0'); --tem que ser na fora bruta
--t1
reg_1(9) <= (0 => '1', 1 => '1', others => '0');
reg_2(9) <= (0 => '1', 1 => '1', others => '0');
reg_1(10) <= (others => '0');
reg_2(10) <= (others => '0');
reg_1(11) <= (others => '0');
reg_2(11) <= (others => '0');
reg_1(12) <= (others => '0');
reg_2(12) <= (others => '0');
reg_1(13) <= (others => '0');
reg_2(13) <= (others => '0');
reg_1(14) <= (others => '0');
reg_2(14) <= (others => '0');
reg_1(15) <= (others => '0');
reg_2(15) <= (others => '0');
reg_1(16) <= (others => '0');
reg_2(16) <= (others => '0');
--s1
reg_1(17) <= x"ffff0000";
reg_2(17) <= x"ffff0000";
reg_1(18) <= (others => '0');
reg_2(18) <= (others => '0');
reg_1(19) <= (others => '0');
reg_2(19) <= (others => '0');
reg_1(20) <= (others => '0');
reg_2(20) <= (others => '0');
reg_1(21) <= (others => '0');
reg_2(21) <= (others => '0');
reg_1(22) <= (others => '0');
reg_2(22) <= (others => '0');
reg_1(23) <= (others => '0');
reg_2(23) <= (others => '0');
reg_1(24) <= (others => '0');
reg_2(24) <= (others => '0');
reg_1(25) <= (others => '0');
reg_2(25) <= (others => '0');
reg_1(26) <= (others => '0');
reg_2(26) <= (others => '0');
reg_1(27) <= (others => '0');
reg_2(27) <= (others => '0');
reg_1(28) <= (others => '0');
reg_2(28) <= (others => '0');
reg_1(29) <= (others => '0');
reg_2(29) <= (others => '0');
reg_1(30) <= (others => '0');
reg_2(30) <= (others => '0');
reg_1(31) <= (others => '0');
reg_2(31) <= (others => '0');
elsif clk'event and clk = '0' and regwrite = '1' then
reg_1(to_integer(unsigned(in_c))) <= in_d;
......
tb_main_processor.vhd
+ 2
− 2
View file @ 7336fac0
......@@ -52,7 +52,7 @@ architecture behavior of tb_main_processor is
signal reset : std_logic := '0';
-- clock period definitions
constant clk_period : time := 5 ns;
constant clk_period : time := 20 ns;
begin
......@@ -76,7 +76,7 @@ begin
stim_proc: process
begin
reset <= '1';
wait for 5 ns;
wait for 20 ns;
reset <= '0';
wait;
end process;
......
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