pc.vhd

-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  complete implementation of patterson and hennessy single cycle mips processor
--  copyright (c) 2015  darci luiz tomasi junior
--
--  this program is free software: you can redistribute it and/or modify
--  it under the terms of the gnu general public license as published by
--  the free software foundation, version 3.
--
--  this program is distributed in the hope that it will be useful,
--  but without any warranty; without even the implied warranty of
--  merchantability or fitness for a particular purpose.  see the
--  gnu general public license for more details.
--
--  you should have received a copy of the gnu general public license
--  along with this program.  if not, see <http://www.gnu.org/licenses/>.
--
--  engineer: 	darci luiz tomasi junior
--	 e-mail: 	dltj007@gmail.com
--  date :    	01/07/2015 - 19:53 
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++  
library ieee;
use ieee.std_logic_1164.all;

entity pc is
	port(
		clk   :	in	std_logic;
		reset : in	std_logic;
		in_a  : in 	std_logic_vector(31 downto 0);
		out_a : out	std_logic_vector(31 downto 0)
	);
end pc;

architecture arc_pc of pc is
	
begin
	process(clk, reset)
	begin
		if reset = '1' then
			out_a <= x"00400000";								--para utilizar com o mars
		elsif clk'event and clk = '1' then
			out_a <= in_a;
		end if;
	end process;
end arc_pc;