ula_ctrl.vhd

-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
--  complete implementation of patterson and hennessy single cycle mips processor
--  copyright (c) 2015  darci luiz tomasi junior
--
--  this program is free software: you can redistribute it and/or modify
--  it under the terms of the gnu general public license as published by
--  the free software foundation, version 3.
--
--  this program is distributed in the hope that it will be useful,
--  but without any warranty; without even the implied warranty of
--  merchantability or fitness for a particular purpose.  see the
--  gnu general public license for more details.
--
--  you should have received a copy of the gnu general public license
--  along with this program.  if not, see <http://www.gnu.org/licenses/>.
--
--  engineer: 	darci luiz tomasi junior
--	 e-mail: 	dltj007@gmail.com
--  date :    	24/06/2015 - 20:23
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 
library ieee;
use ieee.std_logic_1164.all;

entity ula_ctrl is
    port ( 
				aluop : 			in  std_logic_vector (1 downto 0);
				in_a : 			in  std_logic_vector (5 downto 0);
				out_a : 			out  std_logic_vector (2 downto 0)
			);
end ula_ctrl;

architecture arc_ula_ctrl of ula_ctrl is	

begin
	
	--conforme apndix d do livro texto
	out_a(2) <= aluop(0) or (aluop(1) and in_a(1));
	out_a(1) <= (not aluop(1)) or (not in_a(2));
	out_a(0) <= (aluop(1) and in_a(0)) or (aluop(1) and in_a(3));

end arc_ula_ctrl;