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Commit 02026411 authored by Roberto Hexsel's avatar Roberto Hexsel
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moved repo to github.

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This repository was moved to https://github.com/rhexsel/cmips
This repo will not be updated.
28th april 2017.
cMIPS cMIPS
cMIPS is a synthesizable VHDL model for the 5-stage pipeline, MIPS32r2 core. cMIPS is a synthesizable VHDL model for the 5-stage pipeline, MIPS32r2 core.
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