all exception processing now in stage MM, FPGA timing OK

cMIPS/docs/cMIPS.pdf

cMIPS/docs/figs/circuit1.pdf

cMIPS/docs/figs/circuit2.pdf

cMIPS/docs/figs/circuit3.pdf

cMIPS/docs/installCrosscompiler

cMIPS/include/stop.s

cMIPS/tests/badVAddr.s

cMIPS/tests/badVAddrMM.s

cMIPS/tests/break.s

cMIPS/tests/doTests.sh

cMIPS/tests/ll_sc.s

cMIPS/tests/mfc0CONFIG.s

cMIPS/tests/mmu_context.expected

cMIPS/tests/mmu_context.s

cMIPS/tests/mmu_double.s

cMIPS/tests/mmu_index.expected

cMIPS/tests/mmu_index.s

cMIPS/tests/mmu_inval.s

cMIPS/tests/mmu_inval2.s

cMIPS/tests/mmu_mod.s