Commits · 5ca9543ae455e325f40b6a9089b54b0d33777eeb · Roberto Hexsel / cMIPS

May 16, 2016
- ll-sc test file missing · 5ca9543a
  Roberto Hexsel authored 9 years ago
  
  5ca9543a
May 15, 2016
- SC-nop-branch forwarding was fixed, with thanks to Rafael Soares · 2d5cf5ec
  Roberto Hexsel authored 9 years ago
  
  2d5cf5ec
May 13, 2016
- handlers turned EXL=0 too early accepting interrupts from within selves · 15af2070
  Roberto Hexsel authored 9 years ago
  
  15af2070
May 10, 2016
- fixed data allocation for UART_rx_irq handler · 9782bdeb
  Roberto Hexsel authored 9 years ago
  
  9782bdeb
- improved UART_rx_irq handler · c67b6164
  Roberto Hexsel authored 9 years ago
  
  c67b6164
May 09, 2016
- handler for TLBload e TLBstore · 0def435e
  Roberto Hexsel authored 9 years ago
  
  0def435e
May 08, 2016
- handler for TLBmodified · 7fb756c2
  Roberto Hexsel authored 9 years ago
  
  7fb756c2
May 06, 2016
- new uart_irx.expected · 23de04fe
  Roberto Hexsel authored 9 years ago
  
  23de04fe
- page table walk, several fixes · 791396a2
  Roberto Hexsel authored 9 years ago
  
  791396a2
Apr 22, 2016
- hw interrupts were connected to the wront IRQs · e21ec516
  Roberto Hexsel authored 9 years ago
  
  e21ec516
Apr 13, 2016
- fixed handlers.s · 92800b1d
  Roberto Hexsel authored 9 years ago
  
  92800b1d
- fixed yesterday-s incomplete update · fc3b9232
  Roberto Hexsel authored 9 years ago
  
  fc3b9232
Apr 12, 2016
- added sdram address decoding · f053542d
  Roberto Hexsel authored 9 years ago
  
  f053542d
Apr 11, 2016
- moved IO addresses to include SDRAM · de9f9e78
  Roberto Hexsel authored 9 years ago
  
  de9f9e78
Apr 10, 2016
- small syntax problem in rom,vhd · fbafc894
  Roberto Hexsel authored 9 years ago
  
  fbafc894
Apr 08, 2016
- forward progress holds with simultaneous interrupts · b80a0478
  Roberto Hexsel authored 9 years ago
  
  b80a0478
- remote UART now activated by RTS · bdff9da6
  Roberto Hexsel authored 9 years ago
  
  bdff9da6
Apr 07, 2016
- removed all fake entities · 8cb5a972
  Roberto Hexsel authored 9 years ago
  
  8cb5a972
- added fake_SDRAM_controller · 64d9cccb
  Roberto Hexsel authored 9 years ago
  
  64d9cccb
Apr 05, 2016
- SDRAM controller's state machine written · 2c424a99
  Roberto Hexsel authored 9 years ago
  
  2c424a99
Apr 01, 2016
- incomplete SDRAM controller · eea4da3a
  Roberto Hexsel authored 9 years ago
  
  eea4da3a
Mar 22, 2016
- added tests for interrupt on JR delay slot · 254f4bbb
  Roberto Hexsel authored 9 years ago
  
  254f4bbb
Mar 15, 2016
- interrupt on a J/BR delay slot, with JR stalled, loaded the wrong EPC (thnx Vanessa) · c6cd4046
  Roberto Hexsel authored 9 years ago
  
  c6cd4046
Feb 24, 2016
- increased ROM and RAM sizes · f449ae9a
  Roberto Hexsel authored 9 years ago
  
  f449ae9a
Dec 14, 2015
- Merge branch 'master' of gitlab.c3sl.ufpr.br:roberto/cmips · 6b2b5608
  Roberto Hexsel authored 9 years ago
  
  two commits without a push
  6b2b5608
- added test for lw ra; jr ra (with files) · 7cc43c6e
  Roberto Hexsel authored 9 years ago
  
  7cc43c6e
- added test for lw ra; jr ra · 71218814
  Roberto Hexsel authored 9 years ago
  
  71218814
Dec 11, 2015
- improved text · d861b6c7
  Roberto Hexsel authored 9 years ago
  
  d861b6c7
Dec 08, 2015
- fixed IO address decoding for FPGA · 1aeaf00b
  Roberto Hexsel authored 9 years ago
  
  1aeaf00b
Nov 14, 2015
- added FPU mult test · 0381d09c
  Roberto Hexsel authored 9 years ago
  
  0381d09c
- yet another RAM address decoding scheme · d1d7e39d
  Roberto Hexsel authored 9 years ago
  
  d1d7e39d
Nov 12, 2015
- now reads from stdin, cMIPS.{h,c} · b4baeb66
  Roberto Hexsel authored 9 years ago
  
  b4baeb66
- now reads from stdin, test programs: echo.c stdin_out.s · 23eb0ec4
  Roberto Hexsel authored 9 years ago
  
  23eb0ec4
Nov 11, 2015
- changed run.sh so simulator may read from stdin · c6d65b7c
  Roberto Hexsel authored 9 years ago
  
  c6d65b7c
Oct 16, 2015
- fixed exception priorities · 9e086881
  Roberto Hexsel authored 9 years ago
  
  9e086881
Oct 14, 2015
- fixed signal loop in not_waiting · e913e2e3
  Roberto Hexsel authored 9 years ago
  
  e913e2e3
- ficed timing · 3ce734ff
  Roberto Hexsel authored 9 years ago
  
  3ce734ff
Oct 09, 2015
- timing is no good; improved interrupt processing · baf28927
  Roberto Hexsel authored 9 years ago
  
  baf28927
Oct 07, 2015
- added busError exception · 48d4c9a3
  Roberto Hexsel authored 9 years ago
  
  48d4c9a3
Oct 05, 2015
- fixed wait-states for LCD driver · 57bc994b
  Roberto Hexsel authored 9 years ago
  
  57bc994b