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Vytor Calixto
Killer
Commits
00b691ad
Commit
00b691ad
authored
10 years ago
by
Roberto Hexsel
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updated README
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00b691ad
...
@@ -3,22 +3,21 @@ cMIPS
...
@@ -3,22 +3,21 @@ cMIPS
cMIPS is a synthesizable VHDL model for the 5-stage pipeline, MIPS32r2 core.
cMIPS is a synthesizable VHDL model for the 5-stage pipeline, MIPS32r2 core.
The VHDL model mimics the pipeline design described in Patterson & Hennessy's
The VHDL model mimics the pipeline design described in Patterson & Hennessy's
book (Computer Organisation and Design) and is a
n (almost) complete
book (Computer Organisation and Design) and is a
complete implementation
implementation
of the MIPS32r2 instruction set.
of the MIPS32r2 instruction set.
The model was synthesized for an Altera EP4CE30F23. The model runs at 50 MHz
The model was synthesized for an Altera EP4CE30F23. The model runs at 50 MHz
(top
development
board speed) and uses up 15% of combinational blocks and
(top board speed) and uses up 15% of
the
combinational blocks and
5% of the
5% of
logic registers
i
n the FPGA.
logic registers
o
n the FPGA.
Processor model runs C code, compiled with GCC; there are scripts to
Processor model runs C code, compiled with GCC; there are scripts to
compile and assemble code to run on the simulator or the FPGA.
compile and assemble code to run on the simulator or the FPGA.
Core has all forwarding paths and full interlocks for data and control hazards.
Core has all forwarding paths and full interlocks for data and control hazards.
Coprocessor0 is partially implemented, six hardware interrupts + NMI in
Coprocessor0 supports six hardware interrupts + NMI in "Interrupt
"Interrupt Compatibility Mode"; TLB implementation will be available soon.
Compatibility Mode" and an 8-way fully associative TLB. The control
instructions break, syscall, trap, mfc0, mtc0, eret, ei, di, ll, sc
The control instructions break, syscall, trap, mfc0, mtc0, eret, ei, di, ll, sc
are fully implemented.
are fully implemented.
Partial-word loads and stores (word, half-word, byte) implemented at the
Partial-word loads and stores (word, half-word, byte) implemented at the
...
@@ -26,6 +25,6 @@ processor's memory interface.
...
@@ -26,6 +25,6 @@ processor's memory interface.
Testbench for tests includes processor, RAM, ROM and (simulator) file I/O.
Testbench for tests includes processor, RAM, ROM and (simulator) file I/O.
Top level file for synthesis includes processor, RAM, ROM, LCD display,
Top level file for synthesis includes processor, RAM, ROM, LCD display
2x7segment LED display, keypad and UART. TLB, SDRAM controller, VGA interface
controller, 2x7segment LED display, keypad and UART. SDRAM controller,
are in the works.
VGA interface and Ethernet port are in the works.
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