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Commit 355f7518 authored by Roberto Hexsel's avatar Roberto Hexsel
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UART code with Tstatus plus better TLB init mappings

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cMIPS/docs/cMIPS.pdf
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cMIPS/tests/mmu_double.s
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......@@ -105,7 +105,7 @@ _excp_180: tlbp # probe for the guilty entry
li $30, '\n'
sw $30, x_IO_ADDR_RANGE($20)
eret # return to EPC saved on the first fault
eret # return to the EPC saved on the first fault
.end _excp_180 # the second fault refills TLB
......@@ -118,7 +118,7 @@ _excp_180: tlbp # probe for the guilty entry
## dirty trick: there is not enough memory for a full PT, thus
## we set the PT at the bottom of RAM addresses and have
## Context pointing into that address range
## Context pointing to that address range
.set PTbase, x_DATA_BASE_ADDR
.ent main
......@@ -148,7 +148,7 @@ main: la $20, x_IO_BASE_ADDR
sw $7, 8($4)
sw $0, 0xc($4)
li $5, 7 # 2nd ROM mapping
li $5, 2 # 2nd ROM mapping
mtc0 $5, cop0_Index
nop
tlbr
......@@ -199,8 +199,9 @@ main: la $20, x_IO_BASE_ADDR
nop
nop
##
## cause a TLB miss
##
jal there
nop
......
cMIPS/tests/mmu_refill.s
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− 3
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......@@ -115,7 +115,8 @@ main: la $20, x_IO_BASE_ADDR
sw $7, 8($4)
sw $0, 12($4)
li $5, 7 # 2nd ROM mapping
li $5, 2 # 2nd ROM mapping on 2nd PT element
mtc0 $5, cop0_Index
nop
tlbr
......@@ -125,17 +126,39 @@ main: la $20, x_IO_BASE_ADDR
mfc0 $7, cop0_EntryLo1
# sw $7, 0($20)
# 2nd entry: PPN2 & PPN3 ROM
# 2nd entry: PPN2 & PPN3 I/O
sw $6, 16($4)
sw $0, 20($4)
sw $7, 24($4)
sw $0, 28($4)
li $5, 3 # 3rd ROM mapping on 3rd PT element
mtc0 $5, cop0_Index
nop
tlbr
mfc0 $6, cop0_EntryLo0
# sw $6, 0($20)
mfc0 $7, cop0_EntryLo1
# sw $7, 0($20)
# 2nd entry: PPN4 & PPN5 ROM
sw $6, 32($4)
sw $0, 36($4)
sw $7, 40($4)
sw $0, 44($4)
# load Context with PTbase
mtc0 $4, cop0_Context
## change mapping for 2nd ROM TLB entry, thus causing a miss
li $5, 2 # 2nd ROM mapping
mtc0 $5, cop0_Index
li $9, 0x2000
sll $9, $9, 8
......@@ -147,6 +170,10 @@ main: la $20, x_IO_BASE_ADDR
tlbwi # and write it back to TLB
nop
nop
nop
## cause a TLB miss
jal there
......
cMIPS/tests/mmu_refill2.s
+ 13
− 5
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......@@ -64,9 +64,9 @@ _excp: mfc0 $k1, cop0_Context
mtc0 $k0, cop0_EntryLo0 # EntryLo0 <- k0 = even element
mtc0 $k1, cop0_EntryLo1 # EntryLo1 <- k1 = odd element
##
## cause another miss on 2nd ROM mapping
## cause, on purpose, another miss on 2nd ROM mapping
##
li $k0, 7
li $k0, 2
mtc0 $k0, cop0_Index
ehb
tlbwi # update TLB
......@@ -128,7 +128,7 @@ main: la $20, x_IO_BASE_ADDR
# 2nd entry: PPN2 & PPN3 ROM
li $5, 7 # 2nd ROM mapping
li $5, 2 # 2nd ROM mapping
mtc0 $5, cop0_Index
nop
tlbr
......@@ -145,8 +145,8 @@ main: la $20, x_IO_BASE_ADDR
sw $0, 0x1c($4)
# 1024th entry: PPN4 & PPN5 RAM
li $5, 6 # 3rd RAM mapping
# 1024th entry: PPN6 & PPN7 RAM
li $5, 7 # 3rd RAM mapping
mtc0 $5, cop0_Index
nop
tlbr
......@@ -168,6 +168,8 @@ main: la $20, x_IO_BASE_ADDR
## change mapping for 3rd RAM TLB entry, thus causing a miss
li $5, 7 # 3rd RAM mapping
mtc0 $5, cop0_Index
li $9, 0x8000
sll $9, $9, 8
......@@ -178,8 +180,14 @@ main: la $20, x_IO_BASE_ADDR
tlbwi # and write it back to TLB (Index = 6)
nop
nop
nop
##
## cause miss on the load in the delay slot - miss on 6th RAM page
## then a second miss since handler (purposefully) updates the
## TLB entry for the 2nd ROM page
##
li $15, (x_DATA_BASE_ADDR + 6*4096) # VPN2
......
cMIPS/tests/mmu_tlbwi.expected
+ 4
− 4
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......@@ -28,10 +28,10 @@
0000091b
00000c1b
6
00044000
00001107
00001147
7
00046000
00001187
000011c7
7
00002000
00000087
000000c7
cMIPS/tests/uart_irx.c
+ 12
− 9
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......@@ -8,16 +8,19 @@ typedef struct control { // control register fields (uses only ls byte)
} Tcontrol;
typedef struct status { // status register fields (uses only ls byte)
#if 1
int s;
// int ign : 24, // ignore uppermost bits
// ign7 : 1, // ignored (bit 7)
// txEmpty : 1, // TX register is empty (bit 6)
// rxFull : 1, // octet available from RX register (bit 5)
// int_TX_empt: 1, // interrupt pending on TX empty (bit 4)
// int_RX_full: 1, // interrupt pending on RX full (bit 3)
// ign2 : 1, // ignored (bit 2)
// framing : 1, // framing error (bit 1)
// overun : 1; // overun error (bit 0)
#else
int ign : 24, // ignore uppermost bits
ign7 : 1, // ignored (bit 7)
txEmpty : 1, // TX register is empty (bit 6)
rxFull : 1, // octet available from RX register (bit 5)
int_TX_empt: 1, // interrupt pending on TX empty (bit 4)
int_RX_full: 1, // interrupt pending on RX full (bit 3)
ign2 : 1, // ignored (bit 2)
framing : 1, // framing error (bit 1)
overun : 1; // overun error (bit 0)
#endif
} Tstatus;
#define RXfull 0x00000020
......
cMIPS/tests/uartrx.c
+ 16
− 13
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......@@ -2,7 +2,7 @@
typedef struct control { // control register fields (uses only ls byte)
int ign : 24, // ignore uppermost bits
rts : 1, // Request to Send
rts : 1, // Request to Send out (bit 7)
ign2 : 2, // bits 6,5 ignored
intTX : 1, // interrupt on TX buffer empty (bit 4)
intRX : 1, // interrupt on RX buffer full (bit 3)
......@@ -10,16 +10,19 @@ typedef struct control { // control register fields (uses only ls byte)
} Tcontrol;
typedef struct status { // status register fields (uses only ls byte)
#if 0
int s;
// int ign : 24, // ignore uppermost bits
// ign7 : 1, // ignored (bit 7)
// txEmpty : 1, // TX register is empty (bit 6)
// rxFull : 1, // octet available from RX register (bit 5)
// int_TX_empt: 1, // interrupt pending on TX empty (bit 4)
// int_RX_full: 1, // interrupt pending on RX full (bit 3)
// ign2 : 1, // ignored (bit 2)
// framing : 1, // framing error (bit 1)
// overun : 1; // overun error (bit 0)
#else
int ign : 24, // ignore uppermost 3 bytes
cts : 1, // Clear To Send inp=1 (bit 7)
txEmpty : 1, // TX register is empty (bit 6)
rxFull : 1, // octet available from RX register (bit 5)
int_TX_empt: 1, // interrupt pending on TX empty (bit 4)
int_RX_full: 1, // interrupt pending on RX full (bit 3)
ign2 : 1, // ignored (bit 2)
framing : 1, // framing error (bit 1)
overun : 1; // overun error (bit 0)
#endif
} Tstatus;
#define RXfull 0x00000020
......@@ -70,9 +73,9 @@ int main(void) { // receive a string through the UART serial interface
do {
i = i+1;
// while ( (state = uart->cs.stat.txEmpty) != 1 )
while ( ! ( (state = uart->cs.stat.s) & RXfull ) )
;
// while ( ! ( (state = uart->cs.stat.s) & RXfull ) )
while ( (state = (int)uart->cs.stat.rxFull) == 0 )
if (state == 0) cmips_delay(1); // just do something with state
s[i] = (char)uart->d.rx;
to_stdout( s[i] );
......
cMIPS/tests/uarttx.c
+ 16
− 13
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......@@ -3,7 +3,7 @@
typedef struct control { // control register fields (uses only ls byte)
int ign : 24, // ignore uppermost bits
rts : 1, // Request to Send
rts : 1, // Request to Send out (bit 7)
ign2 : 2, // bits 6,5 ignored
intTX : 1, // interrupt on TX buffer empty (bit 4)
intRX : 1, // interrupt on RX buffer full (bit 3)
......@@ -11,16 +11,19 @@ typedef struct control { // control register fields (uses only ls byte)
} Tcontrol;
typedef struct status { // status register fields (uses only ls byte)
#if 0
int s;
// int ign : 24, // ignore uppermost bits
// ign7 : 1, // ignored (bit 7)
// txEmpty : 1, // TX register is empty (bit 6)
// rxFull : 1, // octet available from RX register (bit 5)
// int_TX_empt: 1, // interrupt pending on TX empty (bit 4)
// int_RX_full: 1, // interrupt pending on RX full (bit 3)
// ign2 : 1, // ignored (bit 2)
// framing : 1, // framing error (bit 1)
// overun : 1; // overun error (bit 0)
#else
int ign : 24, // ignore uppermost 3 bytes
cts : 1, // Clear To Send inp=1 (bit 7)
txEmpty : 1, // TX register is empty (bit 6)
rxFull : 1, // octet available from RX register (bit 5)
int_TX_empt: 1, // interrupt pending on TX empty (bit 4)
int_RX_full: 1, // interrupt pending on RX full (bit 3)
ign2 : 1, // ignored (bit 2)
framing : 1, // framing error (bit 1)
overun : 1; // overun error (bit 0)
#endif
} Tstatus;
#define RXfull 0x00000020
......@@ -96,9 +99,9 @@ int main(void) { // send a string through the UART serial interface
do {
i = i+1;
// while ( (state = uart->cs.stat.txEmpty) != 1 )
while ( ! ( (state = uart->cs.stat.s) & TXempty ) )
;
// while ( ! ( (state = uart->cs.stat.s) & TXempty ) )
while ( (state = (int)uart->cs.stat.txEmpty) == 0 )
if (state == 1) cmips_delay(2); // just do something with state
uart->d.tx = (int)s[i];
} while (s[i] != '\0'); // '\0' is transmitted in previous line
......
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