script

CTRL.vhd

@@ -23,6 +23,7 @@ USE IEEE.STD_LOGIC_1164.ALL;
 
 ENTITY CTRL IS
 	PORT(
+        Instr :             IN      STD_LOGIC_VECTOR(31 DOWNTO 0);
 		OPCode : 			IN		STD_LOGIC_VECTOR(5 DOWNTO 0);
         Func   :            IN      STD_LOGIC_VECTOR(5 DOWNTO 0);
 		RegDst :	    	OUT		STD_LOGIC;
@@ -100,10 +101,6 @@ BEGIN
 									ALUOp(0) <=		'1';	
 									
 		END CASE;
-        IF FUNC = "000000" THEN
-            RegWrite <= '0';
-        END IF;
 	END PROCESS;
-
 END ARC_CTRL;
 

FORWARD.vhd

@@ -43,19 +43,27 @@ BEGIN
         ELSIF CLK'EVENT AND CLK = '1' THEN
             IF Rd_M = Reg_rs THEN
                 forw_a(1) <= '1';
-                forw_b(1) <= '0';
-            ELSIF Rd_M = Reg_rt THEN
-                forw_b(1) <= '1';
+            ELSIF
                 forw_a(1) <= '0';
             END IF;
 
+            IF Rd_M = Reg_rt THEN
+                forw_b(1) <= '1';
+            ELSIF
+                forw_b(1) <= '0';
+            END IF;
+
             IF Rd_W = Reg_rs THEN
                 forw_a(0) <= '1';
-                forw_b(0) <= '0';
-            ELSIF Rd_W = Reg_rt THEN
-                forw_b(0) <= '1';
+            ELSIF
                 forw_a(0) <= '0';
             END IF;
+
+            IF Rd_W = Reg_rt THEN
+                forw_b(0) <= '1';
+            ELSIF
+                forw_b(0) <= '0';
+            END IF;
             --forw_a(1) <= '1' WHEN Rd_M = Reg_rs ELSE '0';
             --forw_a(0) <= '1' WHEN Rd_W = Reg_rs ELSE '0';
             --forw_b(1) <= '1' WHEN Rd_M = Reg_rt ELSE '0';

IF_ID_PIPE.vhd

@@ -5,9 +5,7 @@ ENTITY IF_ID_PIPE IS
 		PORT (CLK     : IN STD_LOGIC;
 			  RESET   : IN STD_LOGIC;
 			  INSTR   : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-			  PC4_IN  : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
 
-			  PC4_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
 			  INSTR_OUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
               OPCODE  : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
 			  REG_RS  : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
@@ -25,12 +23,10 @@ BEGIN
 	PROCESS (CLK, RESET)
 	BEGIN
 		IF RESET = '1' THEN
-			PC4_OUT <= X"00400000"; -- MARS
 			OPCODE <= "000000";	REG_RS <= "00000"; REG_RT <= "00000";
 			REG_RD <= "00000";	SHAMT <= "00000";  FUNC <= "000000";
 			IMMED <= "0000000000000000";
 		ELSIF CLK'EVENT AND CLK = '1' THEN
-			PC4_OUT <= PC4_IN;
 			OPCODE <= INSTR(31 DOWNTO 26);
             REG_RS <= INSTR(25 DOWNTO 21);
             REG_RT <= INSTR(20 DOWNTO 16);	

MAIN_CTTRL.vhd

@@ -63,6 +63,7 @@ ARCHITECTURE ARC_MAIN_PROCESSOR OF MAIN_PROCESSOR IS
 	
 	COMPONENT CTRL IS
 		PORT(
+            Instr  :        IN      STD_LOGIC_VECTOR(31 DOWNTO 0);
 			OPCode : 		IN		STD_LOGIC_VECTOR(5 DOWNTO 0);
             Func   :        IN      STD_LOGIC_VECTOR(5 DOWNTO 0);
 			RegDst :		OUT		STD_LOGIC;
@@ -208,9 +209,7 @@ ARCHITECTURE ARC_MAIN_PROCESSOR OF MAIN_PROCESSOR IS
         PORT (CLK     : IN STD_LOGIC;
               RESET   : IN STD_LOGIC;
               INSTR   : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
-              PC4_IN  : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
 
-              PC4_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
               INSTR_OUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
               OPCODE  : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
               REG_RS  : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
@@ -396,15 +395,14 @@ BEGIN
 	C_ADD_PC :			ADD_PC PORT MAP(PC_OUT, PC_ADD4);
 	C_INST :			INST PORT MAP(PC_OUT, INSTRUCTION);
 	P_IFID :            IF_ID_PIPE PORT MAP(CLK, RESET, INSTRUCTION, 
-                                            PC_ADD4,
-											PC4_ID, INSTRUCTION_ID, OPCODE_ID, RS_ID,
+											INSTRUCTION_ID, OPCODE_ID, RS_ID,
 											RT_ID, RD_ID, OPEN,
 											FUNC_ID, IMMED_ID);
 						-- nao usa o shamt
 	---------------------------------------------------------------------------
 	C_EXTEND_SIGNAL :	EXTEND_SIGNAL PORT MAP(IMMED_ID, 
                                                EXTENDED_IMMED);
-	C_CTRL :			CTRL PORT MAP(OPCODE_ID, FUNC_ID, CTRL_SEL_RDRT, CTRL_JUMP,
+	C_CTRL :			CTRL PORT MAP(INSTRUCTION_ID, OPCODE_ID, FUNC_ID, CTRL_SEL_RDRT, CTRL_JUMP,
                                       CTRL_BRANCH, CTRL_MEMREAD,
                                       CTRL_MEMTOREG, CTRL_ALUOP, 
                                       CTRL_MEMWRITE, CTRL_ALUSRC_EXT_B,
@@ -416,7 +414,7 @@ BEGIN
 	-- jump addr
 	C_SL_1 :			SL_1 PORT MAP(INSTRUCTION_ID, SH_L_JUMP); 
                         -- jump 00 aligned
-	C_CONCAT :			CONCAT PORT MAP(SH_L_JUMP, PC4_ID,
+	C_CONCAT :			CONCAT PORT MAP(SH_L_JUMP, PC_ADD4,
                                         JUMP_ADDR);
 
 	-- branch addr
@@ -427,8 +425,9 @@ BEGIN
     C_SUB_BR :          SUB_BR PORT MAP(REG_A_OUT, REG_B_OUT, RT_RD_EQ);
     C_AND_1 :			AND_1 PORT MAP(CTRL_BRANCH, RT_RD_EQ, TAKE_BRANCH);
     
-    C_MX_3 :			MX_3 PORT MAP(PC4_ID, BRANCH_ADDR, TAKE_BRANCH, 
+    C_MX_3 :			MX_3 PORT MAP(PC_ADD4, BRANCH_ADDR, TAKE_BRANCH, 
                                       SEL_BR_PC4);
+    -- jump take
 	C_MX_4 :			MX_4 PORT MAP(CTRL_JUMP, JUMP_ADDR, SEL_BR_PC4,
                                       NOVO_PC);