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Strozzi
cMIPS
Commits
97877001
Commit
97877001
authored
9 years ago
by
Jedian
Browse files
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Probleminhas do jedi
Signed-off-by:
Jedian
<
jmb15@c3sl.ufpr.br
>
parent
fa4bf4f8
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2 changed files
cMIPS/tests/handlerUARTjedi.s
+10
-10
10 additions, 10 deletions
cMIPS/tests/handlerUARTjedi.s
cMIPS/tests/handlerUARTjedi2.s
+66
-0
66 additions, 0 deletions
cMIPS/tests/handlerUARTjedi2.s
with
76 additions
and
10 deletions
cMIPS/tests/handlerUARTjedi.s
+
10
−
10
View file @
97877001
...
@@ -5,7 +5,7 @@
...
@@ -5,7 +5,7 @@
#
k0
=
_uart_buff
#
k0
=
_uart_buff
andi
$a1
,
$k1
,
UART_rx_irq
#
Is
this
reception
?
andi
$a1
,
$k1
,
UART_rx_irq
#
Is
this
reception
?
beq
$a1
,
$zero
,
UART
interr2
#
no
,
maybe
transmission
?
beq
$a1
,
$zero
,
UART
ret
#
no
,
maybe
transmission
?
nop
nop
#
handle
reception
#
handle
reception
...
@@ -29,7 +29,7 @@
...
@@ -29,7 +29,7 @@
lw
$
7
,
0
(
$
5
)
lw
$
7
,
0
(
$
5
)
###
#
stores
on
queue
on
calculated
new
head
###
#
stores
on
queue
on
head
lui
$
6
,
%
hi
(
rx_q
)
#
get
queue
address
lui
$
6
,
%
hi
(
rx_q
)
#
get
queue
address
ori
$
6
,
$
6
,
%
lo
(
rx_q
)
ori
$
6
,
$
6
,
%
lo
(
rx_q
)
...
@@ -39,24 +39,24 @@
...
@@ -39,24 +39,24 @@
nop
nop
sw
$
7
,
0
(
$
6
)
#
and
store
it
!
sw
$
7
,
0
(
$
6
)
#
and
store
it
!
###
#
process
rx_hd
###
#
process
rx_hd
--
updates
head
lw
$
7
,
0
(
$
5
)
lw
$
7
,
0
(
$
5
)
nop
addiu
$
7
,
$
7
,
1
#
increment
in
1
the
head
of
the
circular
queue
addiu
$
7
,
$
7
,
1
#
increment
in
1
the
head
of
the
circular
queue
li
$
6
,
16
#
calculate
mod
16
andi
$
7
,
$
7
,
0xf
#
%
16
div
$
7
,
$
6
mfhi
$
7
sw
$
7
,
0
(
$
5
)
sw
$
7
,
0
(
$
5
)
#
FIZ
TUDO
ERRADO
,
ERA
NO
TAIL
QUE
EU
TINHA
QUE
MUDAR
,
EXEMPLO
NA
APOSTILA
PAG
142
#
loading
back
used
registers
#
loading
back
used
registers
lw
$
5
,
9
*
4
(
$k0
)
lw
$
5
,
9
*
4
(
$k0
)
lw
$
6
,
10
*
4
(
$k0
)
lw
$
6
,
10
*
4
(
$k0
)
lw
$
7
,
11
*
4
(
$k0
)
lw
$
7
,
11
*
4
(
$k0
)
UARTinterr2
:
#
UARTinterr2
:
andi
$a1
,
$k1
,
UART_tx_irq
#
Is
this
transmission
?
#
andi
$a1
,
$k1
,
UART_tx_irq
#
Is
this
transmission
?
beq
$a1
,
$zero
,
UARTret
#
no
,
ignore
it
and
return
#
beq
$a1
,
$zero
,
UARTret
#
no
,
ignore
it
and
return
nop
#
nop
#
handle
transmission
#
handle
transmission
#
...
TODO
#
...
TODO
...
...
This diff is collapsed.
Click to expand it.
cMIPS/tests/handlerUARTjedi2.s
0 → 100644
+
66
−
0
View file @
97877001
#
UARTinterr
:
#
There
is
space
on
_uart_buff
#
_uart_buff
[
0
]=
UARTstatus
,
[
1
]=
UARTcontrol
,
[
2
]=
data_inp
,
[
3
]=
new
,
#
[
4
]=
$ra
,
[
5
]=
$a0
,
[
6
]=
$a1
,
[
7
]=
$a2
,
[
8
]=
$a3
#
k0
=
_uart_buff
andi
$a1
,
$k1
,
UART_rx_irq
#
Is
this
reception
?
beq
$a1
,
$zero
,
UARTret
#
no
,
maybe
transmission
?
nop
#
handle
reception
lw
$a1
,
4
(
$a0
)
#
Read
data
from
device
nop
#
and
store
it
to
UART
's buffer
sw
$a1
,
2
*
4
(
$k0
)
#
and
return
from
interrupt
addiu
$a1
,
$zero
,
1
sw
$a1
,
3
*
4
(
$k0
)
#
Signal
new
arrival
#
Jedian
:
when
a
new
char
is
on
the
UART
's buffer,
#
i
have
to
enqueue
it
and
update
nrx
.
#
ACHO
QUE
ELE
NAO
TA
RESETANDO
O
INTERRUPTION
REQUEST
,
AI
FICA
TRAVADAO
#
saving
used
registers
on
_uart_buff
sw
$
5
,
9
*
4
(
$k0
)
sw
$
6
,
10
*
4
(
$k0
)
sw
$
7
,
11
*
4
(
$k0
)
#
enqueue
lui
$
5
,
%
hi
(
rx_hd
)
#
get
rx
head
address
ori
$
5
,
$
5
,
%
lo
(
rx_hd
)
lw
$
7
,
0
(
$
5
)
###
#
stores
on
queue
on
head
lui
$
6
,
%
hi
(
rx_q
)
#
get
queue
address
ori
$
6
,
$
6
,
%
lo
(
rx_q
)
sll
$
7
,
$
7
,
2
#
multiply
by
4
addu
$
6
,
$
7
,
$
6
#
calculate
address
to
move
new
char
lw
$
7
,
2
*
4
(
$k0
)
#
get
char
to
be
stored
nop
sw
$
7
,
0
(
$
6
)
#
and
store
it
!
###
#
process
rx_hd
--
updates
head
lw
$
7
,
0
(
$
5
)
nop
addiu
$
7
,
$
7
,
1
#
increment
in
1
the
head
of
the
circular
queue
andi
$
7
,
$
7
,
0xf
#
%
16
sw
$
7
,
0
(
$
5
)
#
FIZ
TUDO
ERRADO
,
ERA
NO
TAIL
QUE
EU
TINHA
QUE
MUDAR
,
EXEMPLO
NA
APOSTILA
PAG
142
#
loading
back
used
registers
lw
$
5
,
9
*
4
(
$k0
)
lw
$
6
,
10
*
4
(
$k0
)
lw
$
7
,
11
*
4
(
$k0
)
#
UARTinterr2
:
#
andi
$a1
,
$k1
,
UART_tx_irq
#
Is
this
transmission
?
#
beq
$a1
,
$zero
,
UARTret
#
no
,
ignore
it
and
return
#
nop
#
handle
transmission
#
...
TODO
#
Lembrar
de
inicializar
os
hd
e
tl
com
0
no
comeco
do
main
#
UARTret
:
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