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Commit b3c5d69b authored by Roberto Hexsel's avatar Roberto Hexsel
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fixed cacheError exception vector entry address

parent 668622ac
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cMIPS/bin/edMemory.sh
+ 1
− 1
View file @ b3c5d69b
...@@ -58,7 +58,7 @@ asm="${include}"/cMIPS.s ...@@ -58,7 +58,7 @@ asm="${include}"/cMIPS.s
VARIABLES="x_INST_BASE_ADDR x_INST_MEM_SZ x_DATA_BASE_ADDR x_DATA_MEM_SZ x_IO_BASE_ADDR x_IO_MEM_SZ x_IO_ADDR_RANGE" VARIABLES="x_INST_BASE_ADDR x_INST_MEM_SZ x_DATA_BASE_ADDR x_DATA_MEM_SZ x_IO_BASE_ADDR x_IO_MEM_SZ x_IO_ADDR_RANGE"
EXCEPTION_VECTORS="x_EXCEPTION_0000 x_EXCEPTION_0100 x_EXCEPTION_0180 x_EXCEPTION_0200 x_ENTRY_POINT" EXCEPTION_VECTORS="x_EXCEPTION_0000 x_EXCEPTION_0100 x_EXCEPTION_0180 x_EXCEPTION_0200 x_EXCEPTION_BFC0 x_ENTRY_POINT"
if [ "${dfn}" -nt "${lnk}" ] || [ "${dfn}" -nt "${asm}" ] || [ "${dfn}" -nt "${hdr}" ] ; if [ "${dfn}" -nt "${lnk}" ] || [ "${dfn}" -nt "${asm}" ] || [ "${dfn}" -nt "${hdr}" ] ;
then then
......
cMIPS/include/cMIPS.s
+ 8
− 7
View file @ b3c5d69b
# see vhdl/packageMemory.vhd for addresses # see vhdl/packageMemory.vhd for addresses
.set x_INST_BASE_ADDR,0x00000000 .set x_INST_BASE_ADDR,0x00000000
.set x_INST_MEM_SZ,0x00004000 .set x_INST_MEM_SZ,0x00008000
.set x_DATA_BASE_ADDR,0x00040000 .set x_DATA_BASE_ADDR,0x00040000
.set x_DATA_MEM_SZ,0x00040000 .set x_DATA_MEM_SZ,0x00008000
.set x_IO_BASE_ADDR,0x0F000000 .set x_IO_BASE_ADDR,0x0F000000
.set x_IO_MEM_SZ,0x00002000 .set x_IO_MEM_SZ,0x00002000
...@@ -18,11 +18,12 @@ ...@@ -18,11 +18,12 @@
.set HW_lcd_addr, (x_IO_BASE_ADDR + 11 * x_IO_ADDR_RANGE) .set HW_lcd_addr, (x_IO_BASE_ADDR + 11 * x_IO_ADDR_RANGE)
# see vhdl/packageMemory.vhd for addresses # see vhdl/packageMemory.vhd for addresses
.set x_EXCEPTION_0000,0x00000080 .set x_EXCEPTION_0000,0x00000130
.set x_EXCEPTION_0100,0x000000A0 .set x_EXCEPTION_0100,0x00000200
.set x_EXCEPTION_0180,0x00000180 .set x_EXCEPTION_0180,0x00000280
.set x_EXCEPTION_0200,0x00000280 .set x_EXCEPTION_0200,0x00000400
.set x_ENTRY_POINT, 0x00000400 .set x_EXCEPTION_BFC0,0x000004E0
.set x_ENTRY_POINT, 0x00000500
.set cop0_Index, $0 .set cop0_Index, $0
.set cop0_Random, $1 .set cop0_Random, $1
......
cMIPS/include/start.s
+ 57
− 34
View file @ b3c5d69b
...@@ -94,46 +94,27 @@ _exit: nop # flush pipeline ...@@ -94,46 +94,27 @@ _exit: nop # flush pipeline
.end _start .end _start
#---------------------------------------------------------------- ##----------------------------------------------------------------
.global _excp_0000 .global _excp_0000
.global excp_0000
.global _excp_0100 .global _excp_0100
.global excp_0100
.global _excp_0180 .global _excp_0180
.global excp_0180
.global _excp_0200 .global _excp_0200
.global excp_0200 .global _excp_0200
.global _excp_BFC0
## ##
##================================================================ ##================================================================
## ##
.org x_EXCEPTION_0000,0 # exception vector_0000
.ent _excp_0000
excp_0000:
_excp_0000:
# li $k0, 0x1000ff01 # enable interrupts, user mode
# mtc0 $k0, cop0_STATUS
# eret
#----------------------------------------------------------------
# handler for NMI or soft-reset -- simply abort simulation
mfc0 $k1,cop0_CAUSE # read CAUSE
nop
wait 0x38 # abort simulation, no code in Table 8-25
nop #
# j excp_0000ret # OR do something else
.end _excp_0000
## ##
##================================================================ ##================================================================
## exception vector_0100 TLBrefill, from See MIPS Run pg 145 ## exception vector_0000 TLBrefill, from See MIPS Run pg 145
## ##
.org x_EXCEPTION_0100,0 .org x_EXCEPTION_0000,0
.ent _excp_0100 .ent _excp_0000
_excp_0000:
.set noreorder .set noreorder
.set noat .set noat
excp_0100:
_excp_0100:
mfc0 $k1, cop0_Context mfc0 $k1, cop0_Context
lw $k0, 0($k1) # k0 <- TP[Context.lo] lw $k0, 0($k1) # k0 <- TP[Context.lo]
lw $k1, 8($k1) # k1 <- TP[Context.hi] lw $k1, 8($k1) # k1 <- TP[Context.hi]
...@@ -142,6 +123,27 @@ _excp_0100: ...@@ -142,6 +123,27 @@ _excp_0100:
ehb ehb
tlbwr # update TLB tlbwr # update TLB
eret eret
.end _excp_0000
##
##================================================================
## exception vector_0100 Cache Error (hw not implemented)
##
.org x_EXCEPTION_0100,0
.ent _excp_0100
_excp_0100:
.set noreorder
.set noat
la $k0, x_IO_BASE_ADDR
mfc0 $k1, cop0_CAUSE
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
nop
wait 0x01
nop
.end _excp_0100 .end _excp_0100
...@@ -149,17 +151,18 @@ _excp_0100: ...@@ -149,17 +151,18 @@ _excp_0100:
##================================================================ ##================================================================
## handler for all exceptions except interrupts and TLBrefill ## handler for all exceptions except interrupts and TLBrefill
## ##
## area to save up to 16 registers
.bss .bss
.align 2 .align 2
.comm _excp_saves 16*4 # area to save up to 16 registers .comm _excp_saves 16*4
# _excp_saves[0]=CAUSE, [1]=STATUS, [2]=ASID, # _excp_saves[0]=CAUSE, [1]=STATUS, [2]=ASID,
# [8]=$ra, [9]=$a0, [10]=$a1, [11]=$a2, [12]=$a3 # [8]=$ra, [9]=$a0, [10]=$a1, [11]=$a2, [12]=$a3
.text .text
.set noreorder .set noreorder
.set noat
.org x_EXCEPTION_0180,0 # exception vector_180 .org x_EXCEPTION_0180,0 # exception vector_180
.ent _excp_0180 .ent _excp_0180
excp_0180:
_excp_0180: _excp_0180:
mfc0 $k0, cop0_STATUS mfc0 $k0, cop0_STATUS
lui $k1, %hi(_excp_saves) lui $k1, %hi(_excp_saves)
...@@ -320,9 +323,29 @@ excp_0200ret: ...@@ -320,9 +323,29 @@ excp_0200ret:
#---------------------------------------------------------------- #----------------------------------------------------------------
.org x_EXCEPTION_BFC0,0
.ent _excp_BFC0
_excp_BFC0:
##
##================================================================
## exception vector_BFC0 NMI or soft-reset
##
.set noreorder
.set noat
la $k0, x_IO_BASE_ADDR
mfc0 $k1, cop0_CAUSE
sw $k1, 0($k0) # print CAUSE, flush pipe and stop simulation
nop
nop
nop
wait 0x38
nop
.end _excp_BFC0
#----------------------------------------------------------------
# normal code starts here -- do not edit next line
.org x_ENTRY_POINT,0
##
##===============================================================
## main(), normal code starts below -- do not edit next line
.org x_ENTRY_POINT,0
cMIPS/vhdl/core.vhd
+ 7
− 6
View file @ b3c5d69b
...@@ -760,11 +760,12 @@ begin ...@@ -760,11 +760,12 @@ begin
with excp_PCsel select with excp_PCsel select
PCinp <= PCinp_noExcp when PCsel_EXC_none, -- no exception PCinp <= PCinp_noExcp when PCsel_EXC_none, -- no exception
EPC when PCsel_EXC_EPC, -- ERET EPC when PCsel_EXC_EPC, -- ERET
x_EXCEPTION_0100 when PCsel_EXC_0100, -- TLBmiss entry point x_EXCEPTION_0000 when PCsel_EXC_0000, -- TLBrefill entry point
x_EXCEPTION_0180 when PCsel_EXC_0180, -- single exception handler x_EXCEPTION_0180 when PCsel_EXC_0180, -- general exception handler
x_EXCEPTION_0200 when PCsel_EXC_0200, -- separate interrupt handler x_EXCEPTION_0200 when PCsel_EXC_0200, -- separate interrupt handler
x_EXCEPTION_0000 when PCsel_EXC_0000, -- NMI or soft-reset handler x_EXCEPTION_BFC0 when PCsel_EXC_BFC0, -- NMI or soft-reset handler
(others => 'X') when others; (others => 'X') when others;
-- x_EXCEPTION_0100 when PCsel_EXC_0100, -- Cache Error
PC_abort <= PC(1 downto 0) /= b"00"; PC_abort <= PC(1 downto 0) /= b"00";
...@@ -2192,7 +2193,7 @@ begin ...@@ -2192,7 +2193,7 @@ begin
if ( (MM_nmi = '1') and (STATUS(STATUS_ERL) = '0') ) then if ( (MM_nmi = '1') and (STATUS(STATUS_ERL) = '0') ) then
-- non maskable interrupt -- non maskable interrupt
i_excp_PCsel := PCsel_EXC_0180; -- PC <= 0xBFC0.0000 i_excp_PCsel := PCsel_EXC_BFC0; -- PC <= 0xBFC0.0000
elsif ( (STATUS(STATUS_EXL) = '0') and (STATUS(STATUS_ERL) = '0') and elsif ( (STATUS(STATUS_EXL) = '0') and (STATUS(STATUS_ERL) = '0') and
(STATUS(STATUS_IE) = '1') and (MM_interrupt = '1') and (STATUS(STATUS_IE) = '1') and (MM_interrupt = '1') and
......
cMIPS/vhdl/packageExcp.vhd
+ 6
− 5
View file @ b3c5d69b
...@@ -138,10 +138,11 @@ package p_EXCEPTION is ...@@ -138,10 +138,11 @@ package p_EXCEPTION is
-- Sources of Exception Handler's addresses; signal excp_PCsel -- Sources of Exception Handler's addresses; signal excp_PCsel
constant PCsel_EXC_none : reg3 := b"000"; -- no exception constant PCsel_EXC_none : reg3 := b"000"; -- no exception
constant PCsel_EXC_EPC : reg3 := b"001"; -- ERET constant PCsel_EXC_EPC : reg3 := b"001"; -- ERET
constant PCsel_EXC_0180 : reg3 := b"010"; -- general exception handler constant PCsel_EXC_0000 : reg3 := b"010"; -- TLBmiss entry point
constant PCsel_EXC_0200 : reg3 := b"011"; -- separate interrupt handler constant PCsel_EXC_0100 : reg3 := b"011"; -- Cache Error
constant PCsel_EXC_0100 : reg3 := b"100"; -- TLBmiss entry point constant PCsel_EXC_0180 : reg3 := b"100"; -- general exception handler
constant PCsel_EXC_0000 : reg3 := b"110"; -- NMI or soft-reset handler constant PCsel_EXC_0200 : reg3 := b"101"; -- separate interrupt handler
constant PCsel_EXC_BFC0 : reg3 := b"110"; -- NMI or soft-reset handler
-- Sources for EPC; signal EPC_source -- Sources for EPC; signal EPC_source
constant EPC_src_PC : reg3 := b"000"; -- from PC constant EPC_src_PC : reg3 := b"000"; -- from PC
......
cMIPS/vhdl/packageMemory.vhd
+ 11
− 10
View file @ b3c5d69b
...@@ -36,25 +36,26 @@ package p_MEMORY is ...@@ -36,25 +36,26 @@ package p_MEMORY is
-- x_IO_ADDR_RANGE can have only ONE bit set, thus being a power of 2. -- x_IO_ADDR_RANGE can have only ONE bit set, thus being a power of 2.
-- ACHTUNG: changing the above number may break some of the test programs. -- ACHTUNG: changing that definition may break some of the test programs.
-- begin DO NOT change these names as several scripts depend on them -- -- begin DO NOT change these names as several scripts depend on them --
-- you may change the values, not names nor formatting -- -- you may change the values, not names neither formatting --
constant x_INST_BASE_ADDR : reg32 := x"00000000"; constant x_INST_BASE_ADDR : reg32 := x"00000000";
constant x_INST_MEM_SZ : reg32 := x"00004000"; constant x_INST_MEM_SZ : reg32 := x"00004000";
constant x_DATA_BASE_ADDR : reg32 := x"00040000"; constant x_DATA_BASE_ADDR : reg32 := x"00040000";
constant x_DATA_MEM_SZ : reg32 := x"00004000"; constant x_DATA_MEM_SZ : reg32 := x"00008000";
constant x_IO_BASE_ADDR : reg32 := x"0F000000"; constant x_IO_BASE_ADDR : reg32 := x"0F000000";
constant x_IO_MEM_SZ : reg32 := x"00002000"; constant x_IO_MEM_SZ : reg32 := x"00002000";
constant x_IO_ADDR_RANGE : reg32 := x"00000020"; constant x_IO_ADDR_RANGE : reg32 := x"00000020";
constant x_EXCEPTION_0000 : reg32 := x"000000E0"; constant x_EXCEPTION_0000 : reg32 := x"00000130"; -- TLB refill
constant x_EXCEPTION_0100 : reg32 := x"00000180"; constant x_EXCEPTION_0100 : reg32 := x"00000200"; -- Cache Error
constant x_EXCEPTION_0180 : reg32 := x"00000280"; constant x_EXCEPTION_0180 : reg32 := x"00000280"; -- general exc hndlr
constant x_EXCEPTION_0200 : reg32 := x"00000400"; constant x_EXCEPTION_0200 : reg32 := x"00000400"; -- separ interr hndlr
constant x_ENTRY_POINT : reg32 := x"00000500"; constant x_EXCEPTION_BFC0 : reg32 := x"000004E0"; -- NMI, soft-reset
constant x_ENTRY_POINT : reg32 := x"00000500"; -- main()
-- end DO NOT change these names -- -- end DO NOT change these names --
constant INST_BASE_ADDR : integer := to_integer(signed(x_INST_BASE_ADDR)); constant INST_BASE_ADDR : integer := to_integer(signed(x_INST_BASE_ADDR));
constant INST_MEM_SZ : integer := to_integer(signed(x_INST_MEM_SZ)); constant INST_MEM_SZ : integer := to_integer(signed(x_INST_MEM_SZ));
constant DATA_BASE_ADDR : integer := to_integer(signed(x_DATA_BASE_ADDR)); constant DATA_BASE_ADDR : integer := to_integer(signed(x_DATA_BASE_ADDR));
......
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