Merge branch 'jedian' into Strozzi

cMIPS/tests/handlerUART.s

+#UARTinterr:
+    # There is space on _uart_buff
+    # _uart_buff[0]=UARTstatus, [1]=UARTcontrol, [2]=data_inp, [3]=new,
+    #           [4]=$ra, [5]=$a0, [6]=$a1, [7]=$a2, [8]=$a3
+    #k0 = _uart_buff
+
+    andi  $a1, $k1, UART_rx_irq # Is this reception?
+    beq   $a1, $zero, UARTret   #   no, maybe transmission?
+    nop
+
+    #handle reception
+    lw    $a1, 4($a0)           # Read data from device
+    nop                         #   and store it to UART's buffer
+    sw    $a1, 2*4($k0)         #   and return from interrupt
+    addiu $a1, $zero, 1
+    sw    $a1, 3*4($k0)         # Signal new arrival
+                                # Jedian: when a new char is on the UART's buffer, 
+                                #         i have to enqueue it and update nrx.
+
+    # saving used registers on _uart_buff
+    sw    $5, 9*4($k0)
+    sw    $6, 10*4($k0)
+    sw    $7, 11*4($k0)
+    
+    # check if queue is full, maybe increment
+    lui   $5, %hi(nrx)
+    ori   $5, $5, %lo(nrx)
+    lw    $7, 0($5)
+    slti  $6, $7, 16
+    beq   $6, $zero, overrun
+    nop
+    addiu $7, $7, 1
+    sw    $7, 0($5)
+
+    # enqueue
+    lui   $5, %hi(rx_tl)        # get rx tail address
+    ori   $5, $5, %lo(rx_tl)    
+
+    lw    $7, 0($5)
+    nop
+    addiu $7, $7, 1             # increment in 1 the tail of the circular queue
+    andi  $7, $7, 0xf           # % 16
+    sw    $7, 0($5)
+
+    #### stores on queue on tail
+    lui   $6, %hi(rx_q)         # get queue address
+    ori   $6, $6, %lo(rx_q)
+
+    addu  $6, $7, $6            # calculate address to move new char
+    lw    $7, 2*4($k0)          # get char to be stored
+    nop
+    sb    $7, 0($6)             # and store it!
+
+    #### process rx_tl -- update tail
+    #lw   $7, 0($5)
+    #nop
+
+overrun:
+
+    # do something if queue is full
+    #... (doing absolutely nothing besides stacking and unstacking regs)
+
+    # loading back used registers
+    lw    $5, 9*4($k0)
+    lw    $6, 10*4($k0)
+    lw    $7, 11*4($k0)
+
+    #Precisa coisar o nrx (incrementar)
+
+#UARTinterr2:
+#    andi  $a1, $k1, UART_tx_irq # Is this transmission?
+#    beq   $a1, $zero, UARTret   # no, ignore it and return
+#    nop
+
+    #handle transmission
+    # ... TODO
+
+    # Lembrar de inicializar os hd e tl com 0 no comeco do main
+
+#UARTret: 

cMIPS/tests/handlerUARTjedi2.s

@@ -22,6 +22,16 @@
     sw    $6, 10*4($k0)
     sw    $7, 11*4($k0)
     
+    # check if queue is full, maybe increment
+    lui   $5, %hi(nrx)
+    ori   $5, $5, %lo(nrx)
+    lw    $7, 0($5)
+    slti  $6, $7, 16
+    beq   $6, $zero, overrun
+    nop
+    addiu $7, $7, 1
+    sw    $7, 0($5)
+
     # enqueue
     lui   $5, %hi(rx_tl)        # get rx tail address
     ori   $5, $5, %lo(rx_tl)    
@@ -45,6 +55,11 @@
     #lw   $7, 0($5)
     #nop
 
+overrun:
+
+    # do something if queue is full
+    #... (doing absolutely nothing besides stacking and unstacking regs)
+
     # loading back used registers
     lw    $5, 9*4($k0)
     lw    $6, 10*4($k0)

cMIPS/tests/jedidafu.c

+#include "cMIPS.h"
+
+typedef struct UARTdriver {
+int rx_hd ; // reception queue head index
+int rx_tl ; // reception queue tail index
+char rx_q [16]; // reception queue
+int tx_hd ; // transmission queue head index
+int tx_tl ; // transmission queue tail index
+char tx_q [16]; // transmission queue
+int nrx ; // number of characters in rx_queue
+int ntx ; // number of spaces in tx_queue
+} UARTdriver ;
+extern UARTdriver Ud ;
+
+
+typedef struct control { // control register fields (uses only ls byte)
+  int ign   : 24,        // ignore uppermost bits
+    rts     : 1,         // Request to Send output (bit 7)
+    ign2    : 2,         // bits 6,5 ignored
+    intTX   : 1,         // interrupt on TX buffer empty (bit 4)
+    intRX   : 1,         // interrupt on RX buffer full (bit 3)
+    speed   : 3;         // 4,8,16..256 tx-rx clock data rates  (bits 0..2)
+} Tcontrol;
+
+typedef struct status {  // status register fields (uses only ls byte)
+  unsigned int ign : 24, // ignore uppermost 3 bytes
+  cts     : 1,           // Clear To Send input=1 (bit 7)
+  txEmpty : 1,           // TX register is empty (bit 6)
+  rxFull  : 1,           // octet available from RX register (bit 5)
+  int_TX_empt: 1,        // interrupt pending on TX empty (bit 4)
+  int_RX_full: 1,        // interrupt pending on RX full (bit 3)
+  ign1    : 1,           // ignored (bit 2)
+  framing : 1,           // framing error (bit 1)
+  overun  : 1;           // overun error (bit 0)
+} Tstatus;
+
+
+typedef union ctlStat { // control + status on same address
+  Tcontrol  ctl;        // write-only
+  Tstatus   stat;       // read-only
+} TctlStat;
+
+typedef union data {    // data registers on same address
+  int tx;               // write-only
+  int rx;               // read-only
+} Tdata;
+
+typedef struct serial {
+  TctlStat cs;
+  Tdata    d;
+} Tserial;
+
+char Getc () {
+    char c ;
+    if ( Ud.nrx > 0) {
+        disableInterr();
+        // exclui handler enquanto altera Ud
+        Ud.nrx -= 1;
+        c = Ud.rx_q [ Ud.rx_hd ];
+        Ud.rx_hd = (Ud.rx_hd + 1) & 15; // modulo 16
+        enableInterr();
+    } else {
+        c = 0;
+    }
+    return c ;
+}
+
+
+int main(void) { // receive a string through the UART serial interface
+  int i, j;
+  volatile int state;
+  volatile Tserial *uart;  // tell GCC not to optimize away code
+  volatile Tstatus status;
+  Tcontrol ctrl;
+
+  uart = (void *)IO_UART_ADDR; // bottom of UART address range
+
+  ctrl.ign   = 0;
+  ctrl.rts   = 0;   // make RTS=0 to hold RemoteUnit
+  ctrl.ign2  = 0;
+  ctrl.intTX = 0;
+  ctrl.intRX = 1;
+  ctrl.speed = 1;   // operate at the second highest data rate
+  uart->cs.ctl = ctrl;
+
+  i = -1;
+
+  ctrl.ign   = 0;
+  ctrl.rts   = 1;   // make RTS=1 to activate RemoteUnit
+  ctrl.ign2  = 0;
+  ctrl.intTX = 0;
+  ctrl.intRX = 1;
+  ctrl.speed = 1;   // operate at the second highest data rate
+  uart->cs.ctl = ctrl;
+
+  do {
+    state = i = i+1;
+    while(Ud.rx_tl == Ud.rx_hd){ to_stdout('d'); state = 1- state;}
+
+    j = -1;
+    to_stdout('=');
+    do{
+        j = j + 1;
+        //to_stdout(Ud.rx_q[j]);
+        to_stdout(Getc());
+        if(Ud.rx_q[j] == '\n')
+            print(Ud.nrx); //nada ou string completa
+    }while(j<15);
+    to_stdout( '-');
+
+  } while (i<5);
+
+  return(state+i);
+
+}