update on resource usage

README

@@ -7,8 +7,8 @@ book (Computer Organisation and Design) and is a complete implementation
 of the MIPS32r2 instruction set.
 
 The model was synthesized for an Altera EP4CE30F23.  The model runs at 50 MHz
-(top board speed) and uses up 15% of the combinational blocks and 5% of the
-logic registers on the FPGA.
+(top board speed) and uses up 22% of the combinational blocks, 9% of the
+logic registers, and 33% of the memory bits on the FPGA.
 
 Processor model runs C code, compiled with GCC;  there are scripts to
 compile and assemble code to run on the simulator or the FPGA.