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Commit 9d0ced85 authored by Roberto Hexsel's avatar Roberto Hexsel
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what is wrong with teq_tlt?

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cMIPS/bin/compile.sh
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...@@ -33,7 +33,7 @@ OPTIONS: ...@@ -33,7 +33,7 @@ OPTIONS:
-h Show this message -h Show this message
-O n Optimization level, defaults to n=1 {0,1,2,3} -O n Optimization level, defaults to n=1 {0,1,2,3}
-v Verbose, creates memory map: source.map -v Verbose, creates memory map: source.map
-W GIve -Wall to GCC -W Pass -Wall on to GCC
-mif Generate output file ROM.mif for Altera's FPGAs -mif Generate output file ROM.mif for Altera's FPGAs
-syn Compile for synthesis, else for simulation -syn Compile for synthesis, else for simulation
EOF EOF
...@@ -127,9 +127,11 @@ dat=data.bin ...@@ -127,9 +127,11 @@ dat=data.bin
if [ $verbose = true ]; then memory_map="-Map ${inp}.map" ; fi if [ $verbose = true ]; then memory_map="-Map ${inp}.map" ; fi
if [ $synth = true ]; if [ $synth = true ]; then
then S="-D FOR_SYNTHESIS" ; S="-D FOR_SYNTHESIS" ;
else S="-U FOR_SYNTHESIS" ; fi else
S="-U FOR_SYNTHESIS" ;
fi
(mips-gcc -O${level} $warn -DcMIPS -mno-gpopt -I"${include}" \ (mips-gcc -O${level} $warn -DcMIPS -mno-gpopt -I"${include}" \
-S ${src} $S -o ${asm} || exit 1) && \ -S ${src} $S -o ${asm} || exit 1) && \
......
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