pipe

CTRL.vhd

@@ -23,7 +23,6 @@ USE IEEE.STD_LOGIC_1164.ALL;
 
 ENTITY CTRL IS
 	PORT(
-        Instr :             IN      STD_LOGIC_VECTOR(31 DOWNTO 0);
 		OPCode : 			IN		STD_LOGIC_VECTOR(5 DOWNTO 0);
         Func   :            IN      STD_LOGIC_VECTOR(5 DOWNTO 0);
 		RegDst :	    	OUT		STD_LOGIC;

CTRL_WB.vhd

+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+ENTITY CTRL_WB IS
+        PORT (INSTR   : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+              WB      :OUT STD_LOGIC
+        );
+END CTRL_WB;
+
+ARCHITECTURE ARC_CTRL_WB OF CTRL_WB IS
+
+BEGIN
+    PROCESS(INSTR)
+    BEGIN
+        IF INSTR = X"00000000" THEN
+            WB <= '0';
+        ELSE
+            WB <= '1';
+        END IF;
+    END PROCESS;
+END ARC_CTRL_WB;
+
+

EX_MEM_PIPE.vhd

@@ -32,7 +32,7 @@ BEGIN
             ALU_OUT <= X"00000000"; MTR_OUT <= '0';
             REGB_OUT <= X"00000000";
             DST_OUT <= "00000";
-		ELSIF CLK'EVENT AND CLK = '1' THEN
+		ELSIF CLK'EVENT AND CLK = '0' THEN
 			WB_OUT <= WB_IN;  MEM_R_OUT <= MEM_R_IN;
             MEM_W_OUT <= MEM_W_IN; MTR_OUT <= MTR_IN;
             REGB_OUT <= REGB_IN; ALU_OUT <= ALU_RESULT_IN;

FORWARD.vhd

@@ -43,25 +43,25 @@ BEGIN
         ELSIF CLK'EVENT AND CLK = '1' THEN
             IF Rd_M = Reg_rs THEN
                 forw_a(1) <= '1';
-            ELSIF
+            ELSE
                 forw_a(1) <= '0';
             END IF;
 
             IF Rd_M = Reg_rt THEN
                 forw_b(1) <= '1';
-            ELSIF
+            ELSE
                 forw_b(1) <= '0';
             END IF;
 
             IF Rd_W = Reg_rs THEN
                 forw_a(0) <= '1';
-            ELSIF
+            ELSE
                 forw_a(0) <= '0';
             END IF;
 
             IF Rd_W = Reg_rt THEN
                 forw_b(0) <= '1';
-            ELSIF
+            ELSE
                 forw_b(0) <= '0';
             END IF;
             --forw_a(1) <= '1' WHEN Rd_M = Reg_rs ELSE '0';

ID_EX_PIPE.vhd

@@ -49,7 +49,7 @@ BEGIN
             ALU_SRC_OUT <= '0';
             REGDST_OUT <= '0';
             RS_OUT <= "00000"; RT_OUT <= "00000"; RD_OUT <= "00000";
-		ELSIF CLK'EVENT AND CLK = '1' THEN
+		ELSIF CLK'EVENT AND CLK = '0' THEN
 			WB_OUT <= WB_IN;  MEM_R_OUT <= MEM_R_IN;
             MEM_W_OUT <= MEM_W_IN; FUNC_OUT <= FUNC_IN;
             ALU_OP_OUT <= ALU_OP_IN; MTR_OUT <= MTR_IN;

IF_ID_PIPE.vhd

@@ -25,8 +25,10 @@ BEGIN
 		IF RESET = '1' THEN
 			OPCODE <= "000000";	REG_RS <= "00000"; REG_RT <= "00000";
 			REG_RD <= "00000";	SHAMT <= "00000";  FUNC <= "000000";
-			IMMED <= "0000000000000000";
-		ELSIF CLK'EVENT AND CLK = '1' THEN
+			IMMED <= X"0000";
+            INSTR_OUT <= X"00000000";
+		ELSIF CLK'EVENT AND CLK = '0' THEN
+            INSTR_OUT <= INSTR;
 			OPCODE <= INSTR(31 DOWNTO 26);
             REG_RS <= INSTR(25 DOWNTO 21);
             REG_RT <= INSTR(20 DOWNTO 16);	

INST.vhd

@@ -35,8 +35,8 @@ ARCHITECTURE ARC_INST OF INST IS
 	TYPE MEMORY IS ARRAY (0 TO 255) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
 	SIGNAL PROGRAM : MEMORY := (X"00000000",X"00000000",X"00000000",
                                 X"012A4820",X"012A4820",X"012A4820",
-                                X"00000000",X"00000000",X"00000000",
-                                X"00000000",X"00000000",X"00000000",
+                                X"012A4820",X"012A4820",X"012A4820",
+                                X"012A4820",X"012A4820",X"012A4820",
                                 X"00000000",X"00000000",X"00000000",
                                 X"00000000",X"00000000",X"00000000",
                                 X"00000000",X"00000000",X"00000000",

MAIN_CTTRL.vhd

@@ -63,7 +63,6 @@ ARCHITECTURE ARC_MAIN_PROCESSOR OF MAIN_PROCESSOR IS
 	
 	COMPONENT CTRL IS
 		PORT(
-            Instr  :        IN      STD_LOGIC_VECTOR(31 DOWNTO 0);
 			OPCode : 		IN		STD_LOGIC_VECTOR(5 DOWNTO 0);
             Func   :        IN      STD_LOGIC_VECTOR(5 DOWNTO 0);
 			RegDst :		OUT		STD_LOGIC;
@@ -313,6 +312,13 @@ ARCHITECTURE ARC_MAIN_PROCESSOR OF MAIN_PROCESSOR IS
         );  
     END COMPONENT SUB_BR;
 
+    COMPONENT CTRL_WB IS
+        PORT (INSTR   : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+              WB      : OUT STD_LOGIC
+        );
+    END COMPONENT;
+
+
     SIGNAL NOVO_PC               :    STD_LOGIC_VECTOR(31 DOWNTO 0);
     SIGNAL PC_OUT               :    STD_LOGIC_VECTOR(31 DOWNTO 0);
     SIGNAL PC4_ID                :    STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -328,6 +334,8 @@ ARCHITECTURE ARC_MAIN_PROCESSOR OF MAIN_PROCESSOR IS
     SIGNAL CTRL_ALUOP         :    STD_LOGIC_VECTOR(1 DOWNTO 0);
     SIGNAL CTRL_ALUSRC_EXT_B        :    STD_LOGIC;
     SIGNAL CTRL_REGWRITE      :    STD_LOGIC;
+    SIGNAL WB_CTRL            :    STD_LOGIC;
+    SIGNAL WRITEBACK      :    STD_LOGIC;
 
     SIGNAL OPCODE_ID       :    STD_LOGIC_VECTOR(5 DOWNTO 0);
     SIGNAL INSTRUCTION_ID              :    STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -402,11 +410,15 @@ BEGIN
 	---------------------------------------------------------------------------
 	C_EXTEND_SIGNAL :	EXTEND_SIGNAL PORT MAP(IMMED_ID, 
                                                EXTENDED_IMMED);
-	C_CTRL :			CTRL PORT MAP(INSTRUCTION_ID, OPCODE_ID, FUNC_ID, CTRL_SEL_RDRT, CTRL_JUMP,
+	C_CTRL :			CTRL PORT MAP(OPCODE_ID, FUNC_ID, CTRL_SEL_RDRT, CTRL_JUMP,
                                       CTRL_BRANCH, CTRL_MEMREAD,
                                       CTRL_MEMTOREG, CTRL_ALUOP, 
                                       CTRL_MEMWRITE, CTRL_ALUSRC_EXT_B,
                                       CTRL_REGWRITE);
+    -- regwrite
+    C_WB_CTRL:          CTRL_WB PORT MAP(INSTRUCTION_ID, WB_CTRL);
+    AND_WB:             AND_1 PORT MAP(WB_CTRL, CTRL_REGWRITE, WRITEBACK);
+
 	C_REG :				REG PORT MAP(CLK, RESET, REGWRITE_WB, RS_ID, 
                                      RT_ID, REG_DST_WB, VALUE_WRREG, 
                                      REG_A_OUT, REG_B_OUT);
@@ -431,7 +443,7 @@ BEGIN
 	C_MX_4 :			MX_4 PORT MAP(CTRL_JUMP, JUMP_ADDR, SEL_BR_PC4,
                                       NOVO_PC);
 
-	P_IDEX :            ID_EX_PIPE PORT MAP(CLK, RESET, CTRL_REGWRITE,
+	P_IDEX :            ID_EX_PIPE PORT MAP(CLK, RESET, WRITEBACK,
                                             CTRL_MEMREAD, CTRL_MEMWRITE,
                                             CTRL_MEMTOREG, CTRL_ALUOP, 
                                             CTRL_ALUSRC_EXT_B,
@@ -456,12 +468,12 @@ BEGIN
     C_MX_2 :			MX_2 PORT MAP(ALUSRC_EXT_B_EX, REG_B_OUT_EX, 
                                       EXT_IMMED_EX, 
                                       SEL_ALU_EXT_B);
-    P_FRWD_M_B :        MX_2 PORT MAP(FRWD_B(1), ALU_OUT_MEM, SEL_ALU_EXT_B, FRWD_B_OUT);
-    P_FRWD_B :          MX_2 PORT MAP(FRWD_B(0), ALU_OUT_WB, FRWD_B_OUT, ALU_SRC_B);
+    P_FRWD_M_B :        MX_2 PORT MAP(FRWD_B(0), SEL_ALU_EXT_B, ALU_OUT_WB, FRWD_B_OUT);
+    P_FRWD_B :          MX_2 PORT MAP(FRWD_B(1), FRWD_B_OUT, ALU_OUT_MEM, ALU_SRC_B);
 
     -- ALU src a
-    P_FRWD_M_A :        MX_2 PORT MAP(FRWD_A(1), ALU_OUT_MEM, REG_A_OUT_EX, FRWD_A_OUT);
-    P_FRWD_A :          MX_2 PORT MAP(FRWD_A(0), ALU_OUT_WB, FRWD_A_OUT, ALU_SRC_A);
+    P_FRWD_M_A :        MX_2 PORT MAP(FRWD_A(0), REG_A_OUT_EX, ALU_OUT_WB, FRWD_A_OUT);
+    P_FRWD_A :          MX_2 PORT MAP(FRWD_A(1), FRWD_A_OUT, ALU_OUT_MEM, ALU_SRC_A);
 
 	C_ULA_CTRL :		ULA_CTRL PORT MAP(ALUOP_EX, FUNC_EX, ULA_CTRL_OUT);
 	C_ULA :				ULA PORT MAP(ALU_SRC_A, ALU_SRC_B, ULA_CTRL_OUT, 

MEM_WB_PIPE.vhd

@@ -27,7 +27,7 @@ BEGIN
 			WB_OUT <= '0'; MTR_OUT <= '0';
             MEM_OUT <= X"00000000"; ALU_OUT <= X"00000000";
             RD_OUT <= "00000";
-		ELSIF CLK'EVENT AND CLK = '1' THEN
+		ELSIF CLK'EVENT AND CLK = '0' THEN
 			WB_OUT <= WB_IN; MEM_OUT <= MEM_RES_IN; 
             ALU_OUT <= ALU_RES_IN; MTR_OUT <= MTR_IN;
             RD_OUT <= RD_IN;

compile.sh

@@ -4,7 +4,7 @@ if [ $# -eq 3 ]; then
     ghdl -a --ieee=synopsys -fexplicit *.vhd
     ghdl -e --ieee=synopsys -fexplicit TB_MAIN_PROCESSOR
     ./tb_main_processor --stop-time=$1ns --vcd=$2
-    gtkwave $2 $3
+    gtkwave $2 $3 > /dev/null 2>&1
 else
     echo "Uso: $0 <time> <dump>.vcd <config>.sav"
 fi