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Strozzi
cMIPS
Commits
3f25a0d9
Commit
3f25a0d9
authored
9 years ago
by
Jedian
Browse files
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Embonitando tudo, parece funcional por enquanto
Signed-off-by:
Jedian
<
jmb15@c3sl.ufpr.br
>
parent
5e5dcead
Branches
Branches containing commit
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Changes
4
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4 changed files
cMIPS/include/structUart.h
+25
-31
25 additions, 31 deletions
cMIPS/include/structUart.h
cMIPS/serial.inp
+1
-0
1 addition, 0 deletions
cMIPS/serial.inp
cMIPS/tests/handlerUART.s
+1
-1
1 addition, 1 deletion
cMIPS/tests/handlerUART.s
cMIPS/tests/jedidafu.c
+126
-166
126 additions, 166 deletions
cMIPS/tests/jedidafu.c
with
153 additions
and
198 deletions
cMIPS/include/structUart.h
+
25
−
31
View file @
3f25a0d9
...
...
@@ -13,7 +13,7 @@ int ntx ; // number of spaces in tx_queue
}
UARTdriver
;
typedef
struct
control
{
// control register fields (uses only ls byte)
int
ign
:
24
,
// ignore uppermost bits
unsigned
int
ign
:
24
,
// ignore uppermost bits
rts
:
1
,
// Request to Send output (bit 7)
ign2
:
2
,
// bits 6,5 ignored
intTX
:
1
,
// interrupt on TX buffer empty (bit 4)
...
...
@@ -22,7 +22,7 @@ typedef struct control { // control register fields (uses only ls byte)
}
Tcontrol
;
typedef
struct
status
{
// status register fields (uses only ls byte)
int
ign
:
24
,
// ignore uppermost bits
unsigned
int
ign
:
24
,
// ignore uppermost bits
ign7
:
1
,
// ignored (bit 7)
txEmpty
:
1
,
// TX register is empty (bit 6)
rxFull
:
1
,
// octet available from RX register (bit 5)
...
...
@@ -43,12 +43,6 @@ typedef union data { // data registers on same address
int
rx
;
// read-only
}
Tdata
;
/*****************************************************
?typedef struct serial { **
? TctlStat cs; // @ (int *)IO_UART_ADDR **
?} **
*****************************************************/
typedef
struct
serial
{
TctlStat
cs
;
// @ (int *)IO_UART_ADDR
Tdata
d
;
// @ (int *)(IO_UART_ADDR+1)
...
...
This diff is collapsed.
Click to expand it.
cMIPS/serial.inp
+
1
−
0
View file @
3f25a0d9
...
...
@@ -44,3 +44,4 @@ f
2a
2b
This diff is collapsed.
Click to expand it.
cMIPS/tests/handlerUART.s
+
1
−
1
View file @
3f25a0d9
...
...
@@ -107,7 +107,7 @@ UARTrxinter:
overrun
:
jal
print
li
$a0
,
111
li
$a0
,
64017
#
move
$a0
,
$
7
#
do
something
if
rx
queue
is
full
or
tx
is
empty
#
set
overrun
bit
on
uart
statusReg
...
...
This diff is collapsed.
Click to expand it.
cMIPS/tests/jedidafu.c
+
126
−
166
View file @
3f25a0d9
#include
"cMIPS.h"
#include
"../include/vetorFib.h"
#include
"../include/structUart.h"
#define MAXPOW 7
typedef
struct
UARTdriver
{
int
rx_hd
;
// reception queue head index
int
rx_tl
;
// reception queue tail index
char
rx_q
[
16
];
// reception queue
int
tx_hd
;
// transmission queue head index
int
tx_tl
;
// transmission queue tail index
char
tx_q
[
16
];
// transmission queue
int
nrx
;
// number of characters in rx_queue
int
ntx
;
// number of spaces in tx_queue
}
UARTdriver
;
extern
UARTdriver
Ud
;
volatile
Tserial
*
uart
;
// tell GCC not to optimize away code
int
proberx
()
{
return
Ud
.
nrx
;
}
typedef
struct
control
{
// control register fields (uses only ls byte)
int
ign
:
24
,
// ignore uppermost bits
rts
:
1
,
// Request to Send output (bit 7)
ign2
:
2
,
// bits 6,5 ignored
intTX
:
1
,
// interrupt on TX buffer empty (bit 4)
intRX
:
1
,
// interrupt on RX buffer full (bit 3)
speed
:
3
;
// 4,8,16..256 tx-rx clock data rates (bits 0..2)
}
Tcontrol
;
typedef
struct
status
{
// status register fields (uses only ls byte)
unsigned
int
ign
:
24
,
// ignore uppermost 3 bytes
cts
:
1
,
// Clear To Send input=1 (bit 7)
txEmpty
:
1
,
// TX register is empty (bit 6)
rxFull
:
1
,
// octet available from RX register (bit 5)
int_TX_empt:
1
,
// interrupt pending on TX empty (bit 4)
int_RX_full:
1
,
// interrupt pending on RX full (bit 3)
ign1
:
1
,
// ignored (bit 2)
framing
:
1
,
// framing error (bit 1)
overun
:
1
;
// overun error (bit 0)
}
Tstatus
;
typedef
union
ctlStat
{
// control + status on same address
Tcontrol
ctl
;
// write-only
Tstatus
stat
;
// read-only
}
TctlStat
;
typedef
union
data
{
// data registers on same address
int
tx
;
// write-only
int
rx
;
// read-only
}
Tdata
;
typedef
struct
serial
{
TctlStat
cs
;
Tdata
d
;
}
Tserial
;
int
probetx
()
{
return
Ud
.
ntx
;
}
int
ctrl_util
(
int
speed
,
int
trx
,
int
ttx
,
int
rts
)
{
int
ctl
=
0
;
ctl
|=
speed
;
ctl
|=
trx
<<
3
;
ctl
|=
ttx
<<
4
;
ctl
|=
rts
<<
6
;
return
ctl
;
}
void
ioctl
(
int
ctl
){
Tcontrol
aux
;
aux
.
speed
=
ctl
;
aux
.
intRX
=
ctl
>>
3
;
aux
.
intTX
=
ctl
>>
4
;
aux
.
rts
=
ctl
>>
6
;
uart
->
cs
.
ctl
=
aux
;
}
int
iostat
(){
int
stat
=
0
;
stat
|=
uart
->
cs
.
stat
.
overun
;
stat
|=
uart
->
cs
.
stat
.
framing
<<
1
;
stat
|=
uart
->
cs
.
stat
.
int_RX_full
<<
3
;
stat
|=
uart
->
cs
.
stat
.
int_TX_empt
<<
4
;
stat
|=
uart
->
cs
.
stat
.
rxFull
<<
5
;
stat
|=
uart
->
cs
.
stat
.
txEmpty
<<
6
;
return
stat
;
}
int
Putc
(
char
c
)
{
int
ntx
=
Ud
.
ntx
;
if
(
ntx
==
0
)
return
0
;
if
(
ntx
==
16
&&
uart
->
cs
.
stat
.
txEmpty
)
// Empty Q && Tx
uart
->
d
.
tx
=
(
unsigned
int
)
c
;
// 32-bits
else
{
// Sending smthng
disableInterr
();
Ud
.
ntx
--
;
// INCREMENTS AND THEN STORE
Ud
.
tx_tl
=
(
Ud
.
tx_tl
+
1
)
&
0xF
;
// modulo 16
Ud
.
tx_q
[
Ud
.
tx_tl
]
=
c
;
enableInterr
();
}
return
1
;
}
volatile
Tserial
*
uart
;
// tell GCC not to optimize away code
char
Getc
()
{
char
c
;
if
(
Ud
.
nrx
>
0
)
{
...
...
@@ -68,9 +76,6 @@ char Getc () {
return
c
;
}
int
proberx
()
{
return
Ud
.
nrx
;
}
int
Strlen
(
char
*
c
)
{
int
i
=
0
;
while
(
c
[
i
++
]
-
10
);
...
...
@@ -85,28 +90,9 @@ int pow16 (int ex) {
return
(
ex
%
2
?
ret
*
16
:
ret
);
}
int
hex2int
(
char
*
hex
)
{
int
s
=
Strlen
(
hex
),
i
,
ans
=
0
;
#if 0
Test Signal...
switch (hex[0]) {
case 'F':
case 'f':
case 'E':
case 'e':
case 'D':
case 'd':
case 'C':
case 'c':
case 'B':
case 'b':
case 'A':
case 'a':
case '9':
ans = hex[0]*pow16(s-1);
}
#endif
for
(
i
=
0
;
i
<
s
;
i
++
)
{
int
hex2int
(
int
tam
,
char
*
hex
)
{
int
i
,
ans
=
0
;
for
(
i
=
0
;
i
<
tam
;
i
++
)
{
hex
[
i
]
-=
48
;
if
(
hex
[
i
]
>
9
)
hex
[
i
]
-=
7
;
...
...
@@ -114,10 +100,11 @@ int hex2int (char *hex) {
hex
[
i
]
-=
32
;
if
(
hex
[
i
]
<
0
)
hex
[
i
]
=
0
;
ans
+=
hex
[
i
]
*
pow16
(
s
-
(
i
+
1
));
ans
+=
hex
[
i
]
*
pow16
(
tam
-
(
i
+
1
));
}
return
ans
;
}
int
int2hex
(
char
*
c
,
int
i
)
{
int
j
=
0
,
val
;
int
p
;
...
...
@@ -138,22 +125,7 @@ int int2hex (char *c, int i) {
c
[
j
]
=
0
;
return
j
-
1
;
}
int
Putc
(
char
c
)
{
int
ntx
=
Ud
.
ntx
;
if
(
ntx
==
0
)
return
0
;
if
(
ntx
==
16
&&
uart
->
cs
.
stat
.
txEmpty
)
// Empty Q && Tx
uart
->
d
.
tx
=
(
unsigned
int
)
c
;
// 32-bits
else
{
// Sending smthng
disableInterr
();
Ud
.
ntx
--
;
// INCREMENTS AND THEN STORE
Ud
.
tx_tl
=
(
Ud
.
tx_tl
+
1
)
&
0xF
;
// modulo 16
Ud
.
tx_q
[
Ud
.
tx_tl
]
=
c
;
enableInterr
();
}
return
1
;
}
int
main
(
void
)
{
// receive a string through the UART serial interface
...
...
@@ -165,29 +137,15 @@ int main(void) { // receive a string through the UART serial interface
int
tlona
=
0
;
int
filonx
=
0
;
int
valfib
,
qt
,
rxz
,
q
;
int
fim
=
0
;
char
p
[
15
];
Tcontrol
ctrl
;
uart
=
(
void
*
)
IO_UART_ADDR
;
// bottom of UART address range
ctrl
.
ign
=
0
;
ctrl
.
rts
=
0
;
// make RTS=0 to hold RemoteUnit
ctrl
.
ign2
=
0
;
ctrl
.
intTX
=
1
;
ctrl
.
intRX
=
1
;
ctrl
.
speed
=
2
;
// operate at the second highest data rate
uart
->
cs
.
ctl
=
ctrl
;
i
=
-
1
;
ctrl
.
ign
=
0
;
ctrl
.
rts
=
1
;
// make RTS=1 to activate RemoteUnit
ctrl
.
ign2
=
0
;
ctrl
.
intTX
=
1
;
ctrl
.
intRX
=
1
;
ctrl
.
speed
=
2
;
// operate at the second highest data rate
uart
->
cs
.
ctl
=
ctrl
;
ioctl
(
ctrl_util
(
2
,
1
,
1
,
1
));
Ud
.
ntx
=
16
;
do
{
state
=
i
=
i
+
1
;
// se tirar fode (b520 vira 15)
...
...
@@ -209,11 +167,10 @@ int main(void) { // receive a string through the UART serial interface
}
while
(
filonx
>
0
){
qt
=
Strlen
(
filona
+
hdona
);
valfib
=
hex2int
((
filona
+
hdona
));
valfib
=
hex2int
(
qt
,
(
filona
+
hdona
));
valfib
=
buf
[
valfib
];
hdona
+=
qt
+
1
;
hdona
%=
145
;
//print(valfib);
qt
=
int2hex
(
p
,
valfib
);
j
=
-
1
;
do
{
...
...
@@ -234,7 +191,10 @@ int main(void) { // receive a string through the UART serial interface
}
while
(
p
[
j
]
!=
0
);
filonx
--
;
}
if
(
filonx
==
0
&&
!
fim
)
fim
=
1
;
else
if
(
filonx
==
0
&&
fim
)
return
state
+
i
;
}
while
(
i
<
20
);
return
(
state
+
i
);
...
...
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